* [PATCH v6 1/4] dt-bindings: pci: qcom: Document PCIe bindings for SC7280
2021-09-09 17:40 [PATCH v6 0/4] Add DT bindings and DT nodes for PCIe and PHY in SC7280 Prasad Malisetty
@ 2021-09-09 17:40 ` Prasad Malisetty
2021-09-09 17:40 ` [PATCH v6 2/4] arm64: dts: qcom: sc7280: Add PCIe and PHY related nodes Prasad Malisetty
` (2 subsequent siblings)
3 siblings, 0 replies; 7+ messages in thread
From: Prasad Malisetty @ 2021-09-09 17:40 UTC (permalink / raw)
To: agross, bjorn.andersson, bhelgaas, robh+dt, swboyd,
lorenzo.pieralisi, svarbanov
Cc: devicetree, linux-arm-msm, linux-usb, linux-kernel, dianders,
mka, vbadigan, sallenki, manivannan.sadhasivam, Prasad Malisetty
Document the PCIe DT bindings for SC7280 SoC.The PCIe IP is similar
to the one used on SM8250. Add the compatible for SC7280.
Signed-off-by: Prasad Malisetty <pmaliset@codeaurora.org>
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
---
Documentation/devicetree/bindings/pci/qcom,pcie.txt | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.txt b/Documentation/devicetree/bindings/pci/qcom,pcie.txt
index 3f64687..ff423cd 100644
--- a/Documentation/devicetree/bindings/pci/qcom,pcie.txt
+++ b/Documentation/devicetree/bindings/pci/qcom,pcie.txt
@@ -12,6 +12,7 @@
- "qcom,pcie-ipq4019" for ipq4019
- "qcom,pcie-ipq8074" for ipq8074
- "qcom,pcie-qcs404" for qcs404
+ - "qcom,pcie-sc7280" for sc7280
- "qcom,pcie-sdm845" for sdm845
- "qcom,pcie-sm8250" for sm8250
- "qcom,pcie-ipq6018" for ipq6018
@@ -144,6 +145,22 @@
- "slave_bus" AXI Slave clock
- clock-names:
+ Usage: required for sc7280
+ Value type: <stringlist>
+ Definition: Should contain the following entries
+ - "aux" Auxiliary clock
+ - "cfg" Configuration clock
+ - "bus_master" Master AXI clock
+ - "bus_slave" Slave AXI clock
+ - "slave_q2a" Slave Q2A clock
+ - "tbu" PCIe TBU clock
+ - "ddrss_sf_tbu" PCIe SF TBU clock
+ - "pipe" PIPE clock
+ - "pipe_mux" PIPE MUX
+ - "phy_pipe" PIPE output clock
+ - "ref" REFERENCE clock
+
+- clock-names:
Usage: required for sdm845
Value type: <stringlist>
Definition: Should contain the following entries
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH v6 2/4] arm64: dts: qcom: sc7280: Add PCIe and PHY related nodes
2021-09-09 17:40 [PATCH v6 0/4] Add DT bindings and DT nodes for PCIe and PHY in SC7280 Prasad Malisetty
2021-09-09 17:40 ` [PATCH v6 1/4] dt-bindings: pci: qcom: Document PCIe bindings for SC7280 Prasad Malisetty
@ 2021-09-09 17:40 ` Prasad Malisetty
2021-09-09 19:15 ` Stephen Boyd
2021-09-09 17:40 ` [PATCH v6 3/4] arm64: dts: qcom: sc7280: Add PCIe nodes for IDP board Prasad Malisetty
2021-09-09 17:40 ` [PATCH v6 4/4] PCI: qcom: Switch pcie_1_pipe_clk_src after PHY init in SC7280 Prasad Malisetty
3 siblings, 1 reply; 7+ messages in thread
From: Prasad Malisetty @ 2021-09-09 17:40 UTC (permalink / raw)
To: agross, bjorn.andersson, bhelgaas, robh+dt, swboyd,
lorenzo.pieralisi, svarbanov
Cc: devicetree, linux-arm-msm, linux-usb, linux-kernel, dianders,
mka, vbadigan, sallenki, manivannan.sadhasivam, Prasad Malisetty
Add PCIe controller and PHY nodes for sc7280 SOC.
Signed-off-by: Prasad Malisetty <pmaliset@codeaurora.org>
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 121 +++++++++++++++++++++++++++++++++++
1 file changed, 121 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 53a21d0..422c112 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -7,6 +7,7 @@
#include <dt-bindings/clock/qcom,gcc-sc7280.h>
#include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interconnect/qcom,sc7280.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/mailbox/qcom-ipcc.h>
@@ -586,6 +587,119 @@
qcom,bcm-voters = <&apps_bcm_voter>;
};
+ pcie1: pci@1c08000 {
+ compatible = "qcom,pcie-sc7280", "qcom,pcie-sm8250";
+ reg = <0 0x01c08000 0 0x3000>,
+ <0 0x40000000 0 0xf1d>,
+ <0 0x40000f20 0 0xa8>,
+ <0 0x40001000 0 0x1000>,
+ <0 0x40100000 0 0x100000>;
+
+ reg-names = "parf", "dbi", "elbi", "atu", "config";
+ device_type = "pci";
+ linux,pci-domain = <1>;
+ bus-range = <0x00 0xff>;
+ num-lanes = <2>;
+ pipe-clk-source-switch;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>,
+ <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
+
+ interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
+ <&gcc GCC_PCIE_1_PIPE_CLK_SRC>,
+ <&pcie1_lane 0>,
+ <&rpmhcc RPMH_CXO_CLK>,
+ <&gcc GCC_PCIE_1_AUX_CLK>,
+ <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
+ <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
+ <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
+ <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
+ <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
+ <&gcc GCC_DDRSS_PCIE_SF_CLK>;
+
+ clock-names = "pipe",
+ "pipe_mux",
+ "phy_pipe",
+ "ref",
+ "aux",
+ "cfg",
+ "bus_master",
+ "bus_slave",
+ "slave_q2a",
+ "tbu",
+ "ddrss_sf_tbu";
+
+ assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
+ assigned-clock-rates = <19200000>;
+
+ resets = <&gcc GCC_PCIE_1_BCR>;
+ reset-names = "pci";
+
+ power-domains = <&gcc GCC_PCIE_1_GDSC>;
+
+ phys = <&pcie1_lane>;
+ phy-names = "pciephy";
+
+ perst-gpio = <&tlmm 2 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie1_default_state>;
+
+ iommus = <&apps_smmu 0x1c80 0x1>;
+
+ iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
+ <0x100 &apps_smmu 0x1c81 0x1>;
+
+ status = "disabled";
+ };
+
+ pcie1_phy: phy@1c0e000 {
+ compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy";
+ reg = <0 0x01c0e000 0 0x1c0>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
+ <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
+ <&gcc GCC_PCIE_CLKREF_EN>,
+ <&gcc GCC_PCIE1_PHY_RCHNG_CLK>;
+ clock-names = "aux", "cfg_ahb", "ref", "refgen";
+
+ resets = <&gcc GCC_PCIE_1_PHY_BCR>;
+ reset-names = "phy";
+
+ assigned-clocks = <&gcc GCC_PCIE1_PHY_RCHNG_CLK>;
+ assigned-clock-rates = <100000000>;
+
+ status = "disabled";
+
+ pcie1_lane: lanes@1c0e200 {
+ reg = <0 0x01c0e200 0 0x170>,
+ <0 0x01c0e400 0 0x200>,
+ <0 0x01c0ea00 0 0x1f0>,
+ <0 0x01c0e600 0 0x170>,
+ <0 0x01c0e800 0 0x200>,
+ <0 0x01c0ee00 0 0xf4>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "pipe0";
+
+ #phy-cells = <0>;
+ #clock-cells = <1>;
+ clock-output-names = "pcie_1_pipe_clk";
+ };
+ };
+
ipa: ipa@1e40000 {
compatible = "qcom,sc7280-ipa";
@@ -1598,6 +1712,13 @@
bias-bus-hold;
};
};
+
+ pcie1_default_state: pcie1-default-state {
+ clkreq {
+ pins = "gpio79";
+ function = "pcie1_clkreqn";
+ };
+ };
};
apps_smmu: iommu@15000000 {
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [flat|nested] 7+ messages in thread* Re: [PATCH v6 2/4] arm64: dts: qcom: sc7280: Add PCIe and PHY related nodes
2021-09-09 17:40 ` [PATCH v6 2/4] arm64: dts: qcom: sc7280: Add PCIe and PHY related nodes Prasad Malisetty
@ 2021-09-09 19:15 ` Stephen Boyd
0 siblings, 0 replies; 7+ messages in thread
From: Stephen Boyd @ 2021-09-09 19:15 UTC (permalink / raw)
To: Prasad Malisetty, agross, bhelgaas, bjorn.andersson,
lorenzo.pieralisi, robh+dt, svarbanov
Cc: devicetree, linux-arm-msm, linux-usb, linux-kernel, dianders,
mka, vbadigan, sallenki, manivannan.sadhasivam
Quoting Prasad Malisetty (2021-09-09 10:40:43)
> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> index 53a21d0..422c112 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> @@ -7,6 +7,7 @@
>
> #include <dt-bindings/clock/qcom,gcc-sc7280.h>
> #include <dt-bindings/clock/qcom,rpmh.h>
> +#include <dt-bindings/gpio/gpio.h>
> #include <dt-bindings/interconnect/qcom,sc7280.h>
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> #include <dt-bindings/mailbox/qcom-ipcc.h>
> @@ -586,6 +587,119 @@
> qcom,bcm-voters = <&apps_bcm_voter>;
> };
>
> + pcie1: pci@1c08000 {
> + compatible = "qcom,pcie-sc7280", "qcom,pcie-sm8250";
Can you please drop pcie-sm8250?
> + reg = <0 0x01c08000 0 0x3000>,
> + <0 0x40000000 0 0xf1d>,
> + <0 0x40000f20 0 0xa8>,
> + <0 0x40001000 0 0x1000>,
> + <0 0x40100000 0 0x100000>;
> +
> + reg-names = "parf", "dbi", "elbi", "atu", "config";
> + device_type = "pci";
> + linux,pci-domain = <1>;
> + bus-range = <0x00 0xff>;
> + num-lanes = <2>;
> + pipe-clk-source-switch;
I thought this property was going away?
> +
> + #address-cells = <3>;
> + #size-cells = <2>;
> +
> + ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>,
> + <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
> +
> + interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "msi";
> + #interrupt-cells = <1>;
> + interrupt-map-mask = <0 0 0 0x7>;
> + interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>;
> +
> + clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
> + <&gcc GCC_PCIE_1_PIPE_CLK_SRC>,
> + <&pcie1_lane 0>,
> + <&rpmhcc RPMH_CXO_CLK>,
> + <&gcc GCC_PCIE_1_AUX_CLK>,
> + <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
> + <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
> + <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
> + <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
> + <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
> + <&gcc GCC_DDRSS_PCIE_SF_CLK>;
> +
> + clock-names = "pipe",
> + "pipe_mux",
> + "phy_pipe",
> + "ref",
> + "aux",
> + "cfg",
> + "bus_master",
> + "bus_slave",
> + "slave_q2a",
> + "tbu",
> + "ddrss_sf_tbu";
> +
> + assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
> + assigned-clock-rates = <19200000>;
> +
> + resets = <&gcc GCC_PCIE_1_BCR>;
> + reset-names = "pci";
> +
> + power-domains = <&gcc GCC_PCIE_1_GDSC>;
> +
> + phys = <&pcie1_lane>;
> + phy-names = "pciephy";
> +
> + perst-gpio = <&tlmm 2 GPIO_ACTIVE_LOW>;
This should move to the board file because it's a plain old gpio.
> + pinctrl-names = "default";
> + pinctrl-0 = <&pcie1_default_state>;
> +
> + iommus = <&apps_smmu 0x1c80 0x1>;
> +
> + iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
> + <0x100 &apps_smmu 0x1c81 0x1>;
> +
> + status = "disabled";
> + };
> +
> + pcie1_phy: phy@1c0e000 {
> + compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy";
sc7280-qmp-gen3x2-pcie-phy?
> + reg = <0 0x01c0e000 0 0x1c0>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> + clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
> + <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
> + <&gcc GCC_PCIE_CLKREF_EN>,
> + <&gcc GCC_PCIE1_PHY_RCHNG_CLK>;
> + clock-names = "aux", "cfg_ahb", "ref", "refgen";
> +
> + resets = <&gcc GCC_PCIE_1_PHY_BCR>;
> + reset-names = "phy";
> +
> + assigned-clocks = <&gcc GCC_PCIE1_PHY_RCHNG_CLK>;
> + assigned-clock-rates = <100000000>;
> +
> + status = "disabled";
> +
> + pcie1_lane: lanes@1c0e200 {
> + reg = <0 0x01c0e200 0 0x170>,
> + <0 0x01c0e400 0 0x200>,
> + <0 0x01c0ea00 0 0x1f0>,
> + <0 0x01c0e600 0 0x170>,
> + <0 0x01c0e800 0 0x200>,
> + <0 0x01c0ee00 0 0xf4>;
> + clocks = <&rpmhcc RPMH_CXO_CLK>;
> + clock-names = "pipe0";
> +
> + #phy-cells = <0>;
> + #clock-cells = <1>;
> + clock-output-names = "pcie_1_pipe_clk";
> + };
> + };
> +
> ipa: ipa@1e40000 {
> compatible = "qcom,sc7280-ipa";
>
> @@ -1598,6 +1712,13 @@
> bias-bus-hold;
> };
> };
> +
> + pcie1_default_state: pcie1-default-state {
> + clkreq {
Drop clkreq node and just put the pin and function directly inside
please.
> + pins = "gpio79";
> + function = "pcie1_clkreqn";
> + };
> + };
> };
>
> apps_smmu: iommu@15000000 {
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH v6 3/4] arm64: dts: qcom: sc7280: Add PCIe nodes for IDP board
2021-09-09 17:40 [PATCH v6 0/4] Add DT bindings and DT nodes for PCIe and PHY in SC7280 Prasad Malisetty
2021-09-09 17:40 ` [PATCH v6 1/4] dt-bindings: pci: qcom: Document PCIe bindings for SC7280 Prasad Malisetty
2021-09-09 17:40 ` [PATCH v6 2/4] arm64: dts: qcom: sc7280: Add PCIe and PHY related nodes Prasad Malisetty
@ 2021-09-09 17:40 ` Prasad Malisetty
2021-09-09 17:40 ` [PATCH v6 4/4] PCI: qcom: Switch pcie_1_pipe_clk_src after PHY init in SC7280 Prasad Malisetty
3 siblings, 0 replies; 7+ messages in thread
From: Prasad Malisetty @ 2021-09-09 17:40 UTC (permalink / raw)
To: agross, bjorn.andersson, bhelgaas, robh+dt, swboyd,
lorenzo.pieralisi, svarbanov
Cc: devicetree, linux-arm-msm, linux-usb, linux-kernel, dianders,
mka, vbadigan, sallenki, manivannan.sadhasivam, Prasad Malisetty
Add PCIe and PHY nodes for sc7280 IDP board.
Signed-off-by: Prasad Malisetty <pmaliset@codeaurora.org>
---
arch/arm64/boot/dts/qcom/sc7280-idp.dts | 39 +++++++++++++++++++++++++++++++++
1 file changed, 39 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dts b/arch/arm64/boot/dts/qcom/sc7280-idp.dts
index 64fc22a..b249ca1 100644
--- a/arch/arm64/boot/dts/qcom/sc7280-idp.dts
+++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dts
@@ -61,6 +61,45 @@
modem-init;
};
+&pcie1 {
+ status = "okay";
+
+ vdda-supply = <&vreg_l10c_0p8>;
+};
+
+&pcie1_phy {
+ status = "okay";
+
+ vdda-phy-supply = <&vreg_l10c_0p8>;
+ vdda-pll-supply = <&vreg_l6b_1p2>;
+};
+
+&pcie1_default_state {
+ clkreq {
+ bias-pull-up;
+ };
+
+ reset-n {
+ pins = "gpio2";
+ function = "gpio";
+
+ drive-strength = <16>;
+ output-low;
+ bias-disable;
+ };
+
+ wake-n {
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ nvme-n {
+ pins = "gpio19";
+ function = "gpio";
+ bias-pull-up;
+ };
+};
+
&pmk8350_vadc {
pmr735a_die_temp {
reg = <PMR735A_ADC7_DIE_TEMP>;
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH v6 4/4] PCI: qcom: Switch pcie_1_pipe_clk_src after PHY init in SC7280
2021-09-09 17:40 [PATCH v6 0/4] Add DT bindings and DT nodes for PCIe and PHY in SC7280 Prasad Malisetty
` (2 preceding siblings ...)
2021-09-09 17:40 ` [PATCH v6 3/4] arm64: dts: qcom: sc7280: Add PCIe nodes for IDP board Prasad Malisetty
@ 2021-09-09 17:40 ` Prasad Malisetty
2021-09-09 19:16 ` Stephen Boyd
3 siblings, 1 reply; 7+ messages in thread
From: Prasad Malisetty @ 2021-09-09 17:40 UTC (permalink / raw)
To: agross, bjorn.andersson, bhelgaas, robh+dt, swboyd,
lorenzo.pieralisi, svarbanov
Cc: devicetree, linux-arm-msm, linux-usb, linux-kernel, dianders,
mka, vbadigan, sallenki, manivannan.sadhasivam, Prasad Malisetty
On the SC7280, By default the clock source for pcie_1_pipe is
TCXO for gdsc enable. But after the PHY is initialized, the clock
source must be switched to gcc_pcie_1_pipe_clk from TCXO.
Signed-off-by: Prasad Malisetty <pmaliset@codeaurora.org>
---
drivers/pci/controller/dwc/pcie-qcom.c | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index 8a7a300..db62b3c 100644
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -166,6 +166,8 @@ struct qcom_pcie_resources_2_7_0 {
struct regulator_bulk_data supplies[2];
struct reset_control *pci_reset;
struct clk *pipe_clk;
+ struct clk *gcc_pcie_1_pipe_clk_src;
+ struct clk *phy_pipe_clk;
};
union qcom_pcie_resources {
@@ -1167,6 +1169,16 @@ static int qcom_pcie_get_resources_2_7_0(struct qcom_pcie *pcie)
if (ret < 0)
return ret;
+ if (of_device_is_compatible(dev->of_node, "qcom,pcie-sc7280")) {
+ res->gcc_pcie_1_pipe_clk_src = devm_clk_get(dev, "pipe_mux");
+ if (IS_ERR(res->gcc_pcie_1_pipe_clk_src))
+ return PTR_ERR(res->gcc_pcie_1_pipe_clk_src);
+
+ res->phy_pipe_clk = devm_clk_get(dev, "phy_pipe");
+ if (IS_ERR(res->phy_pipe_clk))
+ return PTR_ERR(res->phy_pipe_clk);
+ }
+
res->pipe_clk = devm_clk_get(dev, "pipe");
return PTR_ERR_OR_ZERO(res->pipe_clk);
}
@@ -1255,6 +1267,12 @@ static void qcom_pcie_deinit_2_7_0(struct qcom_pcie *pcie)
static int qcom_pcie_post_init_2_7_0(struct qcom_pcie *pcie)
{
struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0;
+ struct dw_pcie *pci = pcie->pci;
+ struct device *dev = pci->dev;
+ struct device_node *node = dev->of_node;
+
+ if (res->gcc_pcie_1_pipe_clk_src != NULL)
+ clk_set_parent(res->gcc_pcie_1_pipe_clk_src, res->phy_pipe_clk);
return clk_prepare_enable(res->pipe_clk);
}
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [flat|nested] 7+ messages in thread* Re: [PATCH v6 4/4] PCI: qcom: Switch pcie_1_pipe_clk_src after PHY init in SC7280
2021-09-09 17:40 ` [PATCH v6 4/4] PCI: qcom: Switch pcie_1_pipe_clk_src after PHY init in SC7280 Prasad Malisetty
@ 2021-09-09 19:16 ` Stephen Boyd
0 siblings, 0 replies; 7+ messages in thread
From: Stephen Boyd @ 2021-09-09 19:16 UTC (permalink / raw)
To: Prasad Malisetty, agross, bhelgaas, bjorn.andersson,
lorenzo.pieralisi, robh+dt, svarbanov
Cc: devicetree, linux-arm-msm, linux-usb, linux-kernel, dianders,
mka, vbadigan, sallenki, manivannan.sadhasivam
Quoting Prasad Malisetty (2021-09-09 10:40:45)
> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
> index 8a7a300..db62b3c 100644
> --- a/drivers/pci/controller/dwc/pcie-qcom.c
> +++ b/drivers/pci/controller/dwc/pcie-qcom.c
> @@ -1167,6 +1169,16 @@ static int qcom_pcie_get_resources_2_7_0(struct qcom_pcie *pcie)
> if (ret < 0)
> return ret;
>
> + if (of_device_is_compatible(dev->of_node, "qcom,pcie-sc7280")) {
What happened to the approach discussed in v5 of this series where this
is all baked into the device match data?
> + res->gcc_pcie_1_pipe_clk_src = devm_clk_get(dev, "pipe_mux");
> + if (IS_ERR(res->gcc_pcie_1_pipe_clk_src))
> + return PTR_ERR(res->gcc_pcie_1_pipe_clk_src);
> +
> + res->phy_pipe_clk = devm_clk_get(dev, "phy_pipe");
> + if (IS_ERR(res->phy_pipe_clk))
> + return PTR_ERR(res->phy_pipe_clk);
> + }
> +
> res->pipe_clk = devm_clk_get(dev, "pipe");
> return PTR_ERR_OR_ZERO(res->pipe_clk);
> }
^ permalink raw reply [flat|nested] 7+ messages in thread