* [PATCH 01/10] arm64: dts: freescale: Add the top level dtsi support for imx8dxl
2021-09-13 8:47 [PATCH 00/10] arm64: dts: Add i.MX8DXL initial support Abel Vesa
@ 2021-09-13 8:47 ` Abel Vesa
2021-09-13 8:47 ` [PATCH 02/10] arm64: dts: imx8-ss-lsio: Add mu5a mailbox Abel Vesa
` (8 subsequent siblings)
9 siblings, 0 replies; 15+ messages in thread
From: Abel Vesa @ 2021-09-13 8:47 UTC (permalink / raw)
To: Rob Herring, Dong Aisheng, Shawn Guo, Sascha Hauer,
Greg Kroah-Hartman, Fabio Estevam
Cc: Pengutronix Kernel Team, linux-i2c, linux-serial, NXP Linux Team,
Linux Kernel Mailing List, linux-arm-kernel, Abel Vesa,
Jacky Bai
From: Jacky Bai <ping.bai@nxp.com>
The i.MX8DXL is a device targeting the automotive and industrial
market segments. The flexibility of the architecture allows for
use in a wide variety of general embedded applications. The chip
is designed to achieve both high performance and low power consumption.
The chip relies on the power efficient dual (2x) Cortex-A35 cluster.
Add the reserved memory node property for dsp reserved memory,
the wakeup-irq property for SCU node, the imx ion, the rpmsg and the
cm4 rproc support.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
---
arch/arm64/boot/dts/freescale/imx8dxl.dtsi | 245 +++++++++++++++++++++
1 file changed, 245 insertions(+)
create mode 100644 arch/arm64/boot/dts/freescale/imx8dxl.dtsi
diff --git a/arch/arm64/boot/dts/freescale/imx8dxl.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl.dtsi
new file mode 100644
index 000000000000..f16f88882c39
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8dxl.dtsi
@@ -0,0 +1,245 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019-2021 NXP
+ */
+
+#include <dt-bindings/clock/imx8-clock.h>
+#include <dt-bindings/firmware/imx/rsrc.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pinctrl/pads-imx8dxl.h>
+#include <dt-bindings/thermal/thermal.h>
+
+/ {
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ aliases {
+ ethernet0 = &fec1;
+ ethernet1 = &eqos;
+ gpio0 = &lsio_gpio0;
+ gpio1 = &lsio_gpio1;
+ gpio2 = &lsio_gpio2;
+ gpio3 = &lsio_gpio3;
+ gpio4 = &lsio_gpio4;
+ gpio5 = &lsio_gpio5;
+ gpio6 = &lsio_gpio6;
+ gpio7 = &lsio_gpio7;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ mmc0 = &usdhc1;
+ mmc1 = &usdhc2;
+ mu1 = &lsio_mu1;
+ serial0 = &lpuart0;
+ serial1 = &lpuart1;
+ serial2 = &lpuart2;
+ serial3 = &lpuart3;
+ };
+
+ cpus: cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ /* We have 1 clusters with 2 Cortex-A35 cores */
+ A35_0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a35";
+ reg = <0x0 0x0>;
+ enable-method = "psci";
+ next-level-cache = <&A35_L2>;
+ clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>;
+ #cooling-cells = <2>;
+ operating-points-v2 = <&a35_opp_table>;
+ };
+
+ A35_1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a35";
+ reg = <0x0 0x1>;
+ enable-method = "psci";
+ next-level-cache = <&A35_L2>;
+ clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>;
+ #cooling-cells = <2>;
+ operating-points-v2 = <&a35_opp_table>;
+ };
+
+ A35_L2: l2-cache0 {
+ compatible = "cache";
+ };
+ };
+
+ a35_opp_table: opp-table {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-900000000 {
+ opp-hz = /bits/ 64 <900000000>;
+ opp-microvolt = <1000000>;
+ clock-latency-ns = <150000>;
+ };
+
+ opp-1200000000 {
+ opp-hz = /bits/ 64 <1200000000>;
+ opp-microvolt = <1100000>;
+ clock-latency-ns = <150000>;
+ opp-suspend;
+ };
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ dsp_reserved: dsp@92400000 {
+ reg = <0 0x92400000 0 0x2000000>;
+ no-map;
+ };
+ };
+
+ gic: interrupt-controller@51a00000 {
+ compatible = "arm,gic-v3";
+ reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */
+ <0x0 0x51b00000 0 0xc0000>; /* GICR (RD_base + SGI_base) */
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ pmu {
+ compatible = "arm,armv8-pmuv3";
+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ scu {
+ compatible = "fsl,imx-scu";
+ mbox-names = "tx0",
+ "rx0",
+ "gip3";
+ mboxes = <&lsio_mu1 0 0
+ &lsio_mu1 1 0
+ &lsio_mu1 3 3>;
+
+ pd: imx8dxl-pd {
+ compatible = "fsl,imx8dxl-scu-pd", "fsl,scu-pd";
+ #power-domain-cells = <1>;
+ };
+
+ clk: clock-controller {
+ compatible = "fsl,imx8dxl-clk", "fsl,scu-clk";
+ #clock-cells = <2>;
+ clocks = <&xtal32k &xtal24m>;
+ clock-names = "xtal_32KHz", "xtal_24Mhz";
+ };
+
+ iomuxc: pinctrl {
+ compatible = "fsl,imx8dxl-iomuxc";
+ };
+
+ ocotp: imx8qx-ocotp {
+ compatible = "fsl,imx8dxl-scu-ocotp", "fsl,imx8qxp-scu-ocotp";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ fec_mac0: mac@2c4 {
+ reg = <0x2c4 6>;
+ };
+
+ fec_mac1: mac@2c6 {
+ reg = <0x2c6 6>;
+ };
+ };
+
+ watchdog {
+ compatible = "fsl,imx-sc-wdt";
+ timeout-sec = <60>;
+ };
+
+ tsens: thermal-sensor {
+ compatible = "fsl,imx-sc-thermal";
+ #thermal-sensor-cells = <1>;
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */
+ };
+
+ thermal_zones: thermal-zones {
+ cpu-thermal0 {
+ polling-delay-passive = <250>;
+ polling-delay = <2000>;
+ thermal-sensors = <&tsens IMX_SC_R_SYSTEM>;
+
+ trips {
+ cpu_alert0: trip0 {
+ temperature = <107000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+ cpu_crit0: trip1 {
+ temperature = <127000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+ cooling-maps {
+ map0 {
+ trip = <&cpu_alert0>;
+ cooling-device =
+ <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+ };
+
+ clk_dummy: clock-dummy {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ clock-output-names = "clk_dummy";
+ };
+
+ xtal32k: clock-xtal32k {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ clock-output-names = "xtal_32KHz";
+ };
+
+ xtal24m: clock-xtal24m {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24000000>;
+ clock-output-names = "xtal_24MHz";
+ };
+
+ sc_pwrkey: sc-powerkey {
+ compatible = "fsl,imx8-pwrkey";
+ linux,keycode = <KEY_POWER>;
+ wakeup-source;
+ };
+
+ /* sorted in register address */
+ #include "imx8-ss-adma.dtsi"
+ #include "imx8-ss-conn.dtsi"
+ #include "imx8-ss-ddr.dtsi"
+ #include "imx8-ss-lsio.dtsi"
+};
+
+#include "imx8dxl-ss-adma.dtsi"
+#include "imx8dxl-ss-conn.dtsi"
+#include "imx8dxl-ss-lsio.dtsi"
+#include "imx8dxl-ss-ddr.dtsi"
--
2.31.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH 02/10] arm64: dts: imx8-ss-lsio: Add mu5a mailbox
2021-09-13 8:47 [PATCH 00/10] arm64: dts: Add i.MX8DXL initial support Abel Vesa
2021-09-13 8:47 ` [PATCH 01/10] arm64: dts: freescale: Add the top level dtsi support for imx8dxl Abel Vesa
@ 2021-09-13 8:47 ` Abel Vesa
2021-09-13 8:47 ` [PATCH 03/10] arm64: dts: freescale: Add adma subsystem dtsi for imx8dxl Abel Vesa
` (7 subsequent siblings)
9 siblings, 0 replies; 15+ messages in thread
From: Abel Vesa @ 2021-09-13 8:47 UTC (permalink / raw)
To: Rob Herring, Dong Aisheng, Shawn Guo, Sascha Hauer,
Greg Kroah-Hartman, Fabio Estevam
Cc: Pengutronix Kernel Team, linux-i2c, linux-serial, NXP Linux Team,
Linux Kernel Mailing List, linux-arm-kernel, Abel Vesa
The mailbox of the lsio mu5a is used by rpmsg on imx8qxp and
imx8dxl platforms.
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
---
arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi
index ee4e585a9c39..76abdab40c75 100644
--- a/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi
@@ -141,6 +141,13 @@ lsio_mu4: mailbox@5d1f0000 {
status = "disabled";
};
+ lsio_mu5: mailbox@5d200000 {
+ reg = <0x5d200000 0x10000>;
+ interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <2>;
+ power-domains = <&pd IMX_SC_R_MU_5A>;
+ };
+
lsio_mu13: mailbox@5d280000 {
reg = <0x5d280000 0x10000>;
interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
--
2.31.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH 03/10] arm64: dts: freescale: Add adma subsystem dtsi for imx8dxl
2021-09-13 8:47 [PATCH 00/10] arm64: dts: Add i.MX8DXL initial support Abel Vesa
2021-09-13 8:47 ` [PATCH 01/10] arm64: dts: freescale: Add the top level dtsi support for imx8dxl Abel Vesa
2021-09-13 8:47 ` [PATCH 02/10] arm64: dts: imx8-ss-lsio: Add mu5a mailbox Abel Vesa
@ 2021-09-13 8:47 ` Abel Vesa
2021-09-13 8:47 ` [PATCH 04/10] arm64: dts: freescale: Add the imx8dxl connectivity subsys dtsi Abel Vesa
` (6 subsequent siblings)
9 siblings, 0 replies; 15+ messages in thread
From: Abel Vesa @ 2021-09-13 8:47 UTC (permalink / raw)
To: Rob Herring, Dong Aisheng, Shawn Guo, Sascha Hauer,
Greg Kroah-Hartman, Fabio Estevam
Cc: Pengutronix Kernel Team, linux-i2c, linux-serial, NXP Linux Team,
Linux Kernel Mailing List, linux-arm-kernel, Abel Vesa,
Clark Wang, Jacky Bai
Override the I2Cs, LPUARTs, audio_ipg_clk and dma_ipg_clk with
the i.MX8DXL specific properties.
Signed-off-by: Clark Wang <xiaoning.wang@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
---
.../boot/dts/freescale/imx8dxl-ss-adma.dtsi | 53 +++++++++++++++++++
1 file changed, 53 insertions(+)
create mode 100644 arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi
diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi
new file mode 100644
index 000000000000..12ccbc6587ca
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi
@@ -0,0 +1,53 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019-2021 NXP
+ */
+
+&audio_ipg_clk {
+ clock-frequency = <160000000>;
+};
+
+&dma_ipg_clk {
+ clock-frequency = <160000000>;
+};
+
+&i2c0 {
+ compatible = "fsl,imx8dxl-lpi2c", "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
+ interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&i2c1 {
+ compatible = "fsl,imx8dxl-lpi2c", "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
+ interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&i2c2 {
+ compatible = "fsl,imx8dxl-lpi2c", "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
+ interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&i2c3 {
+ compatible = "fsl,imx8dxl-lpi2c", "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
+ interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&lpuart0 {
+ compatible = "fsl,imx8dxl-lpuart", "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
+ interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&lpuart1 {
+ compatible = "fsl,imx8dxl-lpuart", "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
+ interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&lpuart2 {
+ compatible = "fsl,imx8dxl-lpuart", "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
+ interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&lpuart3 {
+ compatible = "fsl,imx8dxl-lpuart", "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
+ interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
+};
+
--
2.31.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH 04/10] arm64: dts: freescale: Add the imx8dxl connectivity subsys dtsi
2021-09-13 8:47 [PATCH 00/10] arm64: dts: Add i.MX8DXL initial support Abel Vesa
` (2 preceding siblings ...)
2021-09-13 8:47 ` [PATCH 03/10] arm64: dts: freescale: Add adma subsystem dtsi for imx8dxl Abel Vesa
@ 2021-09-13 8:47 ` Abel Vesa
2021-09-13 8:47 ` [PATCH 05/10] arm64: dts: freescale: Add ddr subsys dtsi for imx8dxl Abel Vesa
` (5 subsequent siblings)
9 siblings, 0 replies; 15+ messages in thread
From: Abel Vesa @ 2021-09-13 8:47 UTC (permalink / raw)
To: Rob Herring, Dong Aisheng, Shawn Guo, Sascha Hauer,
Greg Kroah-Hartman, Fabio Estevam
Cc: Pengutronix Kernel Team, linux-i2c, linux-serial, NXP Linux Team,
Linux Kernel Mailing List, linux-arm-kernel, Abel Vesa,
Jacky Bai
From: Jacky Bai <ping.bai@nxp.com>
On i.MX8DXL, the Connectivity subsystem includes below peripherals:
1x ENET with AVB support, 1x ENET with TSN support, 2x USB OTG,
1x eMMC, 2x SD, 1x NAND.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
---
.../boot/dts/freescale/imx8dxl-ss-conn.dtsi | 137 ++++++++++++++++++
1 file changed, 137 insertions(+)
create mode 100644 arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi
diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi
new file mode 100644
index 000000000000..b0059296a03f
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi
@@ -0,0 +1,137 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019-2021 NXP
+ */
+
+/delete-node/ &enet1_lpcg;
+/delete-node/ &fec2;
+
+&conn_subsys {
+ conn_enet0_root_clk: clock-conn-enet0-root {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <250000000>;
+ clock-output-names = "conn_enet0_root_clk";
+ };
+
+ eqos: ethernet@5b050000 {
+ compatible = "nxp,imx8dxl-dwmac-eqos", "snps,dwmac-5.10a";
+ reg = <0x5b050000 0x10000>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "eth_wake_irq", "macirq";
+ clocks = <&eqos_lpcg IMX_LPCG_CLK_2>,
+ <&eqos_lpcg IMX_LPCG_CLK_4>,
+ <&eqos_lpcg IMX_LPCG_CLK_0>,
+ <&eqos_lpcg IMX_LPCG_CLK_3>,
+ <&eqos_lpcg IMX_LPCG_CLK_1>;
+ clock-names = "stmmaceth", "pclk", "ptp_ref", "tx", "mem";
+ assigned-clocks = <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>;
+ assigned-clock-rates = <125000000>;
+ power-domains = <&pd IMX_SC_R_ENET_1>;
+ clk_csr = <0>;
+ status = "disabled";
+ };
+
+ usbotg2: usb@5b0e0000 {
+ compatible = "fsl,imx8dxl-usb", "fsl,imx7ulp-usb";
+ reg = <0x5b0e0000 0x200>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
+ fsl,usbphy = <&usbphy2>;
+ fsl,usbmisc = <&usbmisc2 0>;
+ /*
+ * usbotg1 and usbotg2 share one clcok
+ * scfw disable clock access and keep it always on
+ * in case other core (M4) use one of these.
+ */
+ clocks = <&clk_dummy>;
+ ahb-burst-config = <0x0>;
+ tx-burst-size-dword = <0x10>;
+ rx-burst-size-dword = <0x10>;
+ #stream-id-cells = <1>;
+ power-domains = <&pd IMX_SC_R_USB_1>;
+ status = "disabled";
+ };
+
+ usbmisc2: usbmisc@5b0e0200 {
+ #index-cells = <1>;
+ compatible = "fsl,imx8dxl-usbmisc", "fsl,imx7ulp-usbmisc";
+ reg = <0x5b0e0200 0x200>;
+ };
+
+ usbphy2: usbphy@0x5b110000 {
+ compatible = "fsl,imx8dxl-usbphy", "fsl,imx7ulp-usbphy";
+ reg = <0x5b110000 0x1000>;
+ clocks = <&usb2_2_lpcg IMX_LPCG_CLK_7>;
+ status = "disabled";
+ };
+
+ eqos_lpcg: clock-controller@5b240000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5b240000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&conn_enet0_root_clk>,
+ <&conn_axi_clk>,
+ <&conn_axi_clk>,
+ <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>,
+ <&conn_ipg_clk>;
+ clock-indices = <IMX_LPCG_CLK_0>,
+ <IMX_LPCG_CLK_2>,
+ <IMX_LPCG_CLK_4>,
+ <IMX_LPCG_CLK_5>,
+ <IMX_LPCG_CLK_6>;
+ clock-output-names = "eqos_ptp",
+ "eqos_mem_clk",
+ "eqos_aclk",
+ "eqos_clk",
+ "eqos_csr_clk";
+ power-domains = <&pd IMX_SC_R_ENET_1>;
+ };
+
+ usb2_2_lpcg: clock-controller@5b280000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5b280000 0x10000>;
+ #clock-cells = <1>;
+
+ clock-indices = <IMX_LPCG_CLK_7>;
+ clocks = <&conn_ipg_clk>;
+ clock-output-names = "usboh3_2_phy_ipg_clk";
+ };
+
+};
+
+&enet0_lpcg {
+ clocks = <&conn_enet0_root_clk>,
+ <&conn_enet0_root_clk>,
+ <&conn_axi_clk>,
+ <&clk IMX_SC_R_ENET_0 IMX_SC_C_TXCLK>,
+ <&conn_ipg_clk>,
+ <&conn_ipg_clk>;
+};
+
+&fec1 {
+ compatible = "fsl,imx8dxl-fec", "fsl,imx8qm-fec";
+ interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
+ assigned-clocks = <&clk IMX_SC_R_ENET_0 IMX_SC_C_CLKDIV>;
+ assigned-clock-rates = <125000000>;
+};
+
+&usdhc1 {
+ compatible = "fsl,imx8dxl-usdhc", "fsl,imx8qxp-usdhc";
+ interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&usdhc2 {
+ compatible = "fsl,imx8dxl-usdhc", "fsl,imx8qxp-usdhc";
+ interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&usdhc3 {
+ compatible = "fsl,imx8dxl-usdhc", "fsl,imx8qxp-usdhc";
+ interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+};
--
2.31.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH 05/10] arm64: dts: freescale: Add ddr subsys dtsi for imx8dxl
2021-09-13 8:47 [PATCH 00/10] arm64: dts: Add i.MX8DXL initial support Abel Vesa
` (3 preceding siblings ...)
2021-09-13 8:47 ` [PATCH 04/10] arm64: dts: freescale: Add the imx8dxl connectivity subsys dtsi Abel Vesa
@ 2021-09-13 8:47 ` Abel Vesa
2021-09-13 8:47 ` [PATCH 06/10] arm64: dts: freescale: Add lsio " Abel Vesa
` (4 subsequent siblings)
9 siblings, 0 replies; 15+ messages in thread
From: Abel Vesa @ 2021-09-13 8:47 UTC (permalink / raw)
To: Rob Herring, Dong Aisheng, Shawn Guo, Sascha Hauer,
Greg Kroah-Hartman, Fabio Estevam
Cc: Pengutronix Kernel Team, linux-i2c, linux-serial, NXP Linux Team,
Linux Kernel Mailing List, linux-arm-kernel, Abel Vesa,
Jacky Bai
From: Jacky Bai <ping.bai@nxp.com>
Add the ddr subsys dtsi for i.MX8DXL. Additional db pmu is added
compared to i.MX8QXP.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
---
.../boot/dts/freescale/imx8dxl-ss-ddr.dtsi | 36 +++++++++++++++++++
1 file changed, 36 insertions(+)
create mode 100644 arch/arm64/boot/dts/freescale/imx8dxl-ss-ddr.dtsi
diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-ddr.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-ss-ddr.dtsi
new file mode 100644
index 000000000000..75b482966d94
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-ddr.dtsi
@@ -0,0 +1,36 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2021 NXP
+ */
+
+&ddr_subsys {
+ db_ipg_clk: clock-db-ipg {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <456000000>;
+ clock-output-names = "db_ipg_clk";
+ };
+
+ db_pmu0: db-pmu@5ca40000 {
+ compatible = "fsl,imx8dxl-db-pmu";
+ reg = <0x5ca40000 0x10000>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&db_pmu0_lpcg IMX_LPCG_CLK_0>,
+ <&db_pmu0_lpcg IMX_LPCG_CLK_1>;
+ clock-names = "ipg", "cnt";
+ power-domains = <&pd IMX_SC_R_PERF>;
+ };
+
+ db_pmu0_lpcg: clock-controller@5cae0000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5cae0000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&db_ipg_clk>, <&db_ipg_clk>;
+ clock-indices = <IMX_LPCG_CLK_0>,
+ <IMX_LPCG_CLK_1>;
+ clock-output-names = "perf_lpcg_cnt_clk",
+ "perf_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_PERF>;
+ };
+};
--
2.31.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH 06/10] arm64: dts: freescale: Add lsio subsys dtsi for imx8dxl
2021-09-13 8:47 [PATCH 00/10] arm64: dts: Add i.MX8DXL initial support Abel Vesa
` (4 preceding siblings ...)
2021-09-13 8:47 ` [PATCH 05/10] arm64: dts: freescale: Add ddr subsys dtsi for imx8dxl Abel Vesa
@ 2021-09-13 8:47 ` Abel Vesa
2021-09-13 8:47 ` [PATCH 07/10] arm64: dts: imx8dxl: Add i.MX8DXL evk board support Abel Vesa
` (3 subsequent siblings)
9 siblings, 0 replies; 15+ messages in thread
From: Abel Vesa @ 2021-09-13 8:47 UTC (permalink / raw)
To: Rob Herring, Dong Aisheng, Shawn Guo, Sascha Hauer,
Greg Kroah-Hartman, Fabio Estevam
Cc: Pengutronix Kernel Team, linux-i2c, linux-serial, NXP Linux Team,
Linux Kernel Mailing List, linux-arm-kernel, Abel Vesa,
Jacky Bai
From: Jacky Bai <ping.bai@nxp.com>
On i.MX8DXL, the LSIO subsystem includes below devices:
1x Inline Encryption Engine (IEE)
1x FlexSPI
4x Pulse Width Modulator (PWM)
5x General Purpose Timer (GPT)
8x GPIO
14x Message Unit (MU)
256KB On-Chip Memory (OCRAM)
compared to the common imx8-ss-lsio dtsi, some nodes' interrupt
property need to be updated.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
---
.../boot/dts/freescale/imx8dxl-ss-lsio.dtsi | 78 +++++++++++++++++++
1 file changed, 78 insertions(+)
create mode 100644 arch/arm64/boot/dts/freescale/imx8dxl-ss-lsio.dtsi
diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-lsio.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-ss-lsio.dtsi
new file mode 100644
index 000000000000..d90602bab384
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-lsio.dtsi
@@ -0,0 +1,78 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019-2021 NXP
+ */
+&lsio_gpio0 {
+ compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";
+ interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&lsio_gpio1 {
+ compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";
+ interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&lsio_gpio2 {
+ compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";
+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&lsio_gpio3 {
+ compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";
+ interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&lsio_gpio4 {
+ compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";
+ interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&lsio_gpio5 {
+ compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";
+ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&lsio_gpio6 {
+ compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";
+ interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&lsio_gpio7 {
+ compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";
+ interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&lsio_mu0 {
+ compatible = "fsl,imx8dxl-mu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&lsio_mu1 {
+ compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
+ interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&lsio_mu2 {
+ compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
+ interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&lsio_mu3 {
+ compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
+ interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&lsio_mu4 {
+ compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
+ interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&lsio_mu5 {
+ compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
+ interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&lsio_mu13 {
+ compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
+ interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+};
--
2.31.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH 07/10] arm64: dts: imx8dxl: Add i.MX8DXL evk board support
2021-09-13 8:47 [PATCH 00/10] arm64: dts: Add i.MX8DXL initial support Abel Vesa
` (5 preceding siblings ...)
2021-09-13 8:47 ` [PATCH 06/10] arm64: dts: freescale: Add lsio " Abel Vesa
@ 2021-09-13 8:47 ` Abel Vesa
2021-09-13 8:47 ` [PATCH 08/10] dt-bindings: fsl: scu: add i.MX8DXL ocotp binding Abel Vesa
` (2 subsequent siblings)
9 siblings, 0 replies; 15+ messages in thread
From: Abel Vesa @ 2021-09-13 8:47 UTC (permalink / raw)
To: Rob Herring, Dong Aisheng, Shawn Guo, Sascha Hauer,
Greg Kroah-Hartman, Fabio Estevam
Cc: Pengutronix Kernel Team, linux-i2c, linux-serial, NXP Linux Team,
Linux Kernel Mailing List, linux-arm-kernel, Abel Vesa,
Jacky Bai
From: Jacky Bai <ping.bai@nxp.com>
Add i.MX8DXL EVK board support.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
---
arch/arm64/boot/dts/freescale/Makefile | 1 +
arch/arm64/boot/dts/freescale/imx8dxl-evk.dts | 266 ++++++++++++++++++
2 files changed, 267 insertions(+)
create mode 100644 arch/arm64/boot/dts/freescale/imx8dxl-evk.dts
diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
index db9e36ebe932..81619db8ac23 100644
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -65,6 +65,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mq-pico-pi.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mq-thor96.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mq-zii-ultra-rmb3.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mq-zii-ultra-zest.dtb
+dtb-$(CONFIG_ARCH_MXC) += imx8dxl-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8qm-mek.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8qxp-ai_ml.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8qxp-colibri-eval-v3.dtb
diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts
new file mode 100644
index 000000000000..c0ba90efc7a1
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts
@@ -0,0 +1,266 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019-2021 NXP
+ */
+
+/dts-v1/;
+
+#include "imx8dxl.dtsi"
+
+/ {
+ model = "Freescale i.MX8DXL EVK";
+ compatible = "fsl,imx8dxl-evk", "fsl,imx8dxl";
+
+ chosen {
+ stdout-path = &lpuart0;
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x00000000 0x80000000 0 0x40000000>;
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ /*
+ * 0x8800_0000 ~ 0x8FFF_FFFF is reserved for M4
+ * Shouldn't be used at A core and Linux side.
+ *
+ */
+ m4_reserved: m4@0x88000000 {
+ no-map;
+ reg = <0 0x88000000 0 0x8000000>;
+ };
+
+ /* global autoconfigured region for contiguous allocations */
+ linux,cma {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0 0x14000000>;
+ alloc-ranges = <0 0x98000000 0 0x14000000>;
+ linux,cma-default;
+ };
+ };
+
+ reg_usdhc2_vmmc: usdhc2-vmmc {
+ compatible = "regulator-fixed";
+ regulator-name = "SD1_SPWR";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ gpio = <&lsio_gpio4 30 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ off-on-delay-us = <3480>;
+ };
+};
+
+&lpuart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lpuart0>;
+ status = "okay";
+};
+
+&lpuart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lpuart1>;
+ status = "okay";
+};
+
+&lsio_gpio4 {
+ status = "okay";
+};
+
+&lsio_gpio5 {
+ status = "okay";
+};
+
+&thermal_zones {
+ pmic-thermal0 {
+ polling-delay-passive = <250>;
+ polling-delay = <2000>;
+ thermal-sensors = <&tsens IMX_SC_R_PMIC_0>;
+ trips {
+ pmic_alert0: trip0 {
+ temperature = <110000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+ pmic_crit0: trip1 {
+ temperature = <125000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+ cooling-maps {
+ map0 {
+ trip = <&pmic_alert0>;
+ cooling-device =
+ <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+};
+
+&usdhc1 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc1>;
+ pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+ bus-width = <8>;
+ no-sd;
+ no-sdio;
+ non-removable;
+ status = "okay";
+};
+
+&usdhc2 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
+ bus-width = <4>;
+ vmmc-supply = <®_usdhc2_vmmc>;
+ cd-gpios = <&lsio_gpio5 1 GPIO_ACTIVE_LOW>;
+ wp-gpios = <&lsio_gpio5 0 GPIO_ACTIVE_HIGH>;
+ max-frequency = <100000000>;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hog>;
+
+ pinctrl_hog: hoggrp {
+ fsl,pins = <
+ IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD 0x000514a0
+ IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHK_PAD 0x000014a0
+ IMX8DXL_SPI3_CS0_ADMA_ACM_MCLK_OUT1 0x0600004c
+ IMX8DXL_SNVS_TAMPER_OUT1_LSIO_GPIO2_IO05_IN 0x0600004c
+ >;
+ };
+
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ IMX8DXL_SPI1_SCK_ADMA_I2C2_SDA 0x06000021
+ IMX8DXL_SPI1_SDO_ADMA_I2C2_SCL 0x06000021
+ >;
+ };
+
+ pinctrl_i2c3: i2c3grp {
+ fsl,pins = <
+ IMX8DXL_SPI1_CS0_ADMA_I2C3_SDA 0x06000021
+ IMX8DXL_SPI1_SDI_ADMA_I2C3_SCL 0x06000021
+ >;
+ };
+
+ pinctrl_lpuart0: lpuart0grp {
+ fsl,pins = <
+ IMX8DXL_UART0_RX_ADMA_UART0_RX 0x06000020
+ IMX8DXL_UART0_TX_ADMA_UART0_TX 0x06000020
+ >;
+ };
+
+ pinctrl_lpuart1: lpuart1grp {
+ fsl,pins = <
+ IMX8DXL_UART1_TX_ADMA_UART1_TX 0x06000020
+ IMX8DXL_UART1_RX_ADMA_UART1_RX 0x06000020
+ IMX8DXL_UART1_RTS_B_ADMA_UART1_RTS_B 0x06000020
+ IMX8DXL_UART1_CTS_B_ADMA_UART1_CTS_B 0x06000020
+ >;
+ };
+
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ IMX8DXL_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
+ IMX8DXL_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021
+ IMX8DXL_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021
+ IMX8DXL_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021
+ IMX8DXL_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021
+ IMX8DXL_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021
+ IMX8DXL_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021
+ IMX8DXL_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021
+ IMX8DXL_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021
+ IMX8DXL_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021
+ IMX8DXL_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041
+ >;
+ };
+
+ pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
+ fsl,pins = <
+ IMX8DXL_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
+ IMX8DXL_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021
+ IMX8DXL_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021
+ IMX8DXL_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021
+ IMX8DXL_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021
+ IMX8DXL_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021
+ IMX8DXL_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021
+ IMX8DXL_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021
+ IMX8DXL_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021
+ IMX8DXL_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021
+ IMX8DXL_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041
+ >;
+ };
+
+ pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
+ fsl,pins = <
+ IMX8DXL_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
+ IMX8DXL_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021
+ IMX8DXL_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021
+ IMX8DXL_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021
+ IMX8DXL_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021
+ IMX8DXL_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021
+ IMX8DXL_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021
+ IMX8DXL_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021
+ IMX8DXL_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021
+ IMX8DXL_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021
+ IMX8DXL_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041
+ >;
+ };
+
+ pinctrl_usdhc2_gpio: usdhc2gpiogrp {
+ fsl,pins = <
+ IMX8DXL_ENET0_RGMII_TX_CTL_LSIO_GPIO4_IO30 0x00000040 /* RESET_B */
+ IMX8DXL_ENET0_RGMII_TXD1_LSIO_GPIO5_IO00 0x00000021 /* WP */
+ IMX8DXL_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01 0x00000021 /* CD */
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ IMX8DXL_ENET0_RGMII_RXC_CONN_USDHC1_CLK 0x06000041
+ IMX8DXL_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD 0x00000021
+ IMX8DXL_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0 0x00000021
+ IMX8DXL_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1 0x00000021
+ IMX8DXL_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2 0x00000021
+ IMX8DXL_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3 0x00000021
+ IMX8DXL_ENET0_RGMII_TXD0_CONN_USDHC1_VSELECT 0x00000021
+ >;
+ };
+
+ pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
+ fsl,pins = <
+ IMX8DXL_ENET0_RGMII_RXC_CONN_USDHC1_CLK 0x06000041
+ IMX8DXL_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD 0x00000021
+ IMX8DXL_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0 0x00000021
+ IMX8DXL_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1 0x00000021
+ IMX8DXL_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2 0x00000021
+ IMX8DXL_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3 0x00000021
+ IMX8DXL_ENET0_RGMII_TXD0_CONN_USDHC1_VSELECT 0x00000021
+ >;
+ };
+
+ pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
+ fsl,pins = <
+ IMX8DXL_ENET0_RGMII_RXC_CONN_USDHC1_CLK 0x06000041
+ IMX8DXL_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD 0x00000021
+ IMX8DXL_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0 0x00000021
+ IMX8DXL_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1 0x00000021
+ IMX8DXL_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2 0x00000021
+ IMX8DXL_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3 0x00000021
+ IMX8DXL_ENET0_RGMII_TXD0_CONN_USDHC1_VSELECT 0x00000021
+ >;
+ };
+};
--
2.31.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH 08/10] dt-bindings: fsl: scu: add i.MX8DXL ocotp binding
2021-09-13 8:47 [PATCH 00/10] arm64: dts: Add i.MX8DXL initial support Abel Vesa
` (6 preceding siblings ...)
2021-09-13 8:47 ` [PATCH 07/10] arm64: dts: imx8dxl: Add i.MX8DXL evk board support Abel Vesa
@ 2021-09-13 8:47 ` Abel Vesa
2021-09-14 8:41 ` Abel Vesa
2021-09-13 8:47 ` [PATCH 09/10] dt-bindings: i2c: imx-lpi2c: Add i.MX8DXL compatible match Abel Vesa
2021-09-13 8:47 ` [PATCH 10/10] dt-bindings: serial: fsl-lpuart: Add i.MX8DXL compatible Abel Vesa
9 siblings, 1 reply; 15+ messages in thread
From: Abel Vesa @ 2021-09-13 8:47 UTC (permalink / raw)
To: Rob Herring, Dong Aisheng, Shawn Guo, Sascha Hauer,
Greg Kroah-Hartman, Fabio Estevam
Cc: Pengutronix Kernel Team, linux-i2c, linux-serial, NXP Linux Team,
Linux Kernel Mailing List, linux-arm-kernel, Abel Vesa
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
---
Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt b/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt
index fd0061712443..f1470d562156 100644
--- a/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt
+++ b/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt
@@ -141,7 +141,8 @@ OCOTP bindings based on SCU Message Protocol
Required properties:
- compatible: Should be one of:
"fsl,imx8qm-scu-ocotp",
- "fsl,imx8qxp-scu-ocotp".
+ "fsl,imx8qxp-scu-ocotp",
+ "fsl,imx8dxl-scu-ocotp".
- #address-cells: Must be 1. Contains byte index
- #size-cells: Must be 1. Contains byte length
--
2.31.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* Re: [PATCH 08/10] dt-bindings: fsl: scu: add i.MX8DXL ocotp binding
2021-09-13 8:47 ` [PATCH 08/10] dt-bindings: fsl: scu: add i.MX8DXL ocotp binding Abel Vesa
@ 2021-09-14 8:41 ` Abel Vesa
0 siblings, 0 replies; 15+ messages in thread
From: Abel Vesa @ 2021-09-14 8:41 UTC (permalink / raw)
To: Rob Herring, Dong Aisheng, Shawn Guo, Sascha Hauer,
Greg Kroah-Hartman, Fabio Estevam
Cc: Pengutronix Kernel Team, linux-i2c, linux-serial, NXP Linux Team,
Linux Kernel Mailing List, linux-arm-kernel
On 21-09-13 11:47:52, Abel Vesa wrote:
> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Please ignore. Will resend with proper commit message.
> ---
> Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt b/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt
> index fd0061712443..f1470d562156 100644
> --- a/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt
> +++ b/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt
> @@ -141,7 +141,8 @@ OCOTP bindings based on SCU Message Protocol
> Required properties:
> - compatible: Should be one of:
> "fsl,imx8qm-scu-ocotp",
> - "fsl,imx8qxp-scu-ocotp".
> + "fsl,imx8qxp-scu-ocotp",
> + "fsl,imx8dxl-scu-ocotp".
> - #address-cells: Must be 1. Contains byte index
> - #size-cells: Must be 1. Contains byte length
>
> --
> 2.31.1
>
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH 09/10] dt-bindings: i2c: imx-lpi2c: Add i.MX8DXL compatible match
2021-09-13 8:47 [PATCH 00/10] arm64: dts: Add i.MX8DXL initial support Abel Vesa
` (7 preceding siblings ...)
2021-09-13 8:47 ` [PATCH 08/10] dt-bindings: fsl: scu: add i.MX8DXL ocotp binding Abel Vesa
@ 2021-09-13 8:47 ` Abel Vesa
2021-09-14 8:40 ` Abel Vesa
2021-09-13 8:47 ` [PATCH 10/10] dt-bindings: serial: fsl-lpuart: Add i.MX8DXL compatible Abel Vesa
9 siblings, 1 reply; 15+ messages in thread
From: Abel Vesa @ 2021-09-13 8:47 UTC (permalink / raw)
To: Rob Herring, Dong Aisheng, Shawn Guo, Sascha Hauer,
Greg Kroah-Hartman, Fabio Estevam
Cc: Pengutronix Kernel Team, linux-i2c, linux-serial, NXP Linux Team,
Linux Kernel Mailing List, linux-arm-kernel, Abel Vesa
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
---
Documentation/devicetree/bindings/i2c/i2c-imx-lpi2c.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/i2c/i2c-imx-lpi2c.yaml b/Documentation/devicetree/bindings/i2c/i2c-imx-lpi2c.yaml
index 29b9447f3b84..3505577082d7 100644
--- a/Documentation/devicetree/bindings/i2c/i2c-imx-lpi2c.yaml
+++ b/Documentation/devicetree/bindings/i2c/i2c-imx-lpi2c.yaml
@@ -18,7 +18,9 @@ properties:
- enum:
- fsl,imx7ulp-lpi2c
- fsl,imx8qm-lpi2c
+ - fsl,imx8dxl-lpi2c
- items:
+ - const: fsl,imx8dxl-lpi2c
- const: fsl,imx8qxp-lpi2c
- const: fsl,imx7ulp-lpi2c
--
2.31.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* Re: [PATCH 09/10] dt-bindings: i2c: imx-lpi2c: Add i.MX8DXL compatible match
2021-09-13 8:47 ` [PATCH 09/10] dt-bindings: i2c: imx-lpi2c: Add i.MX8DXL compatible match Abel Vesa
@ 2021-09-14 8:40 ` Abel Vesa
0 siblings, 0 replies; 15+ messages in thread
From: Abel Vesa @ 2021-09-14 8:40 UTC (permalink / raw)
To: Rob Herring, Dong Aisheng, Shawn Guo, Sascha Hauer,
Greg Kroah-Hartman, Fabio Estevam
Cc: Pengutronix Kernel Team, linux-i2c, linux-serial, NXP Linux Team,
Linux Kernel Mailing List, linux-arm-kernel
On 21-09-13 11:47:53, Abel Vesa wrote:
> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Please ignore. Will resend with proper commit message.
> ---
> Documentation/devicetree/bindings/i2c/i2c-imx-lpi2c.yaml | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/i2c/i2c-imx-lpi2c.yaml b/Documentation/devicetree/bindings/i2c/i2c-imx-lpi2c.yaml
> index 29b9447f3b84..3505577082d7 100644
> --- a/Documentation/devicetree/bindings/i2c/i2c-imx-lpi2c.yaml
> +++ b/Documentation/devicetree/bindings/i2c/i2c-imx-lpi2c.yaml
> @@ -18,7 +18,9 @@ properties:
> - enum:
> - fsl,imx7ulp-lpi2c
> - fsl,imx8qm-lpi2c
> + - fsl,imx8dxl-lpi2c
> - items:
> + - const: fsl,imx8dxl-lpi2c
> - const: fsl,imx8qxp-lpi2c
> - const: fsl,imx7ulp-lpi2c
>
> --
> 2.31.1
>
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH 10/10] dt-bindings: serial: fsl-lpuart: Add i.MX8DXL compatible
2021-09-13 8:47 [PATCH 00/10] arm64: dts: Add i.MX8DXL initial support Abel Vesa
` (8 preceding siblings ...)
2021-09-13 8:47 ` [PATCH 09/10] dt-bindings: i2c: imx-lpi2c: Add i.MX8DXL compatible match Abel Vesa
@ 2021-09-13 8:47 ` Abel Vesa
2021-09-14 8:04 ` Greg Kroah-Hartman
9 siblings, 1 reply; 15+ messages in thread
From: Abel Vesa @ 2021-09-13 8:47 UTC (permalink / raw)
To: Rob Herring, Dong Aisheng, Shawn Guo, Sascha Hauer,
Greg Kroah-Hartman, Fabio Estevam
Cc: Pengutronix Kernel Team, linux-i2c, linux-serial, NXP Linux Team,
Linux Kernel Mailing List, linux-arm-kernel, Abel Vesa
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
---
Documentation/devicetree/bindings/serial/fsl-lpuart.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/serial/fsl-lpuart.yaml b/Documentation/devicetree/bindings/serial/fsl-lpuart.yaml
index a90c971b4f1f..d84bb33f3b4c 100644
--- a/Documentation/devicetree/bindings/serial/fsl-lpuart.yaml
+++ b/Documentation/devicetree/bindings/serial/fsl-lpuart.yaml
@@ -22,6 +22,7 @@ properties:
- fsl,imx7ulp-lpuart
- fsl,imx8qm-lpuart
- items:
+ - const: fsl,imx8dxl-lpuart
- const: fsl,imx8qxp-lpuart
- const: fsl,imx7ulp-lpuart
--
2.31.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* Re: [PATCH 10/10] dt-bindings: serial: fsl-lpuart: Add i.MX8DXL compatible
2021-09-13 8:47 ` [PATCH 10/10] dt-bindings: serial: fsl-lpuart: Add i.MX8DXL compatible Abel Vesa
@ 2021-09-14 8:04 ` Greg Kroah-Hartman
2021-09-14 8:39 ` Abel Vesa
0 siblings, 1 reply; 15+ messages in thread
From: Greg Kroah-Hartman @ 2021-09-14 8:04 UTC (permalink / raw)
To: Abel Vesa
Cc: Rob Herring, Dong Aisheng, Shawn Guo, Sascha Hauer,
Fabio Estevam, Pengutronix Kernel Team, linux-i2c, linux-serial,
NXP Linux Team, Linux Kernel Mailing List, linux-arm-kernel
On Mon, Sep 13, 2021 at 11:47:54AM +0300, Abel Vesa wrote:
> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
I can not take patches without any changelog text at all, sorry.
greg k-h
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 10/10] dt-bindings: serial: fsl-lpuart: Add i.MX8DXL compatible
2021-09-14 8:04 ` Greg Kroah-Hartman
@ 2021-09-14 8:39 ` Abel Vesa
0 siblings, 0 replies; 15+ messages in thread
From: Abel Vesa @ 2021-09-14 8:39 UTC (permalink / raw)
To: Greg Kroah-Hartman
Cc: Rob Herring, Dong Aisheng, Shawn Guo, Sascha Hauer,
Fabio Estevam, Pengutronix Kernel Team, linux-i2c, linux-serial,
NXP Linux Team, Linux Kernel Mailing List, linux-arm-kernel
On 21-09-14 10:04:05, Greg Kroah-Hartman wrote:
> On Mon, Sep 13, 2021 at 11:47:54AM +0300, Abel Vesa wrote:
> > Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
>
> I can not take patches without any changelog text at all, sorry.
Oups, my bad. Will resend with commit message.
>
> greg k-h
^ permalink raw reply [flat|nested] 15+ messages in thread