* [PATCH 0/5] clk: uniphier: Introduce some clock features and NX1 support
@ 2021-10-05 2:08 Kunihiko Hayashi
2021-10-05 2:08 ` [PATCH 1/5] clk: uniphier: Add audio system and video input clock control for PXs3 Kunihiko Hayashi
` (4 more replies)
0 siblings, 5 replies; 8+ messages in thread
From: Kunihiko Hayashi @ 2021-10-05 2:08 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Rob Herring, Masami Hiramatsu
Cc: linux-clk, devicetree, linux-arm-kernel, linux-kernel, Kunihiko Hayashi
This series includes the patches to add audio/video clock control for PXs3,
SoC-glue clock source selector for Pro4, and basic clock controls for new
UniPhier NX1 SoC. NX1 SoC also has the same kinds of clock controls as the
other UniPhier SoCs.
Kunihiko Hayashi (5):
clk: uniphier: Add audio system and video input clock control for PXs3
dt-bindings: clock: uniphier: Add NX1 clock binding
clk: uniphier: Add NX1 clock support
dt-bindings: clock: uniphier: Add clock binding for SoC-glue
clk: uniphier: Add SoC-glue clock source selector support for Pro4
.../bindings/clock/socionext,uniphier-clock.yaml | 19 +++++++++
drivers/clk/uniphier/clk-uniphier-core.c | 17 ++++++++
drivers/clk/uniphier/clk-uniphier-sys.c | 47 ++++++++++++++++++++++
drivers/clk/uniphier/clk-uniphier.h | 6 +++
4 files changed, 89 insertions(+)
--
2.7.4
^ permalink raw reply [flat|nested] 8+ messages in thread* [PATCH 1/5] clk: uniphier: Add audio system and video input clock control for PXs3 2021-10-05 2:08 [PATCH 0/5] clk: uniphier: Introduce some clock features and NX1 support Kunihiko Hayashi @ 2021-10-05 2:08 ` Kunihiko Hayashi 2021-10-05 2:08 ` [PATCH 2/5] dt-bindings: clock: uniphier: Add NX1 clock binding Kunihiko Hayashi ` (3 subsequent siblings) 4 siblings, 0 replies; 8+ messages in thread From: Kunihiko Hayashi @ 2021-10-05 2:08 UTC (permalink / raw) To: Michael Turquette, Stephen Boyd, Rob Herring, Masami Hiramatsu Cc: linux-clk, devicetree, linux-arm-kernel, linux-kernel, Kunihiko Hayashi Add clocks for audio subsystem (AIO) and video input subsystem (EXIV) on UniPhier PXs3 SoC. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> --- drivers/clk/uniphier/clk-uniphier-sys.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/clk/uniphier/clk-uniphier-sys.c b/drivers/clk/uniphier/clk-uniphier-sys.c index 32b3017..0ec28eb 100644 --- a/drivers/clk/uniphier/clk-uniphier-sys.c +++ b/drivers/clk/uniphier/clk-uniphier-sys.c @@ -288,6 +288,8 @@ const struct uniphier_clk_data uniphier_pxs3_sys_clk_data[] = { UNIPHIER_CLK_GATE("sata0", 28, NULL, 0x210c, 7), UNIPHIER_CLK_GATE("sata1", 29, NULL, 0x210c, 8), UNIPHIER_CLK_GATE("sata-phy", 30, NULL, 0x210c, 21), + UNIPHIER_LD11_SYS_CLK_AIO(40), + UNIPHIER_LD11_SYS_CLK_EXIV(42), /* CPU gears */ UNIPHIER_CLK_DIV4("cpll", 2, 3, 4, 8), UNIPHIER_CLK_DIV4("spll", 2, 3, 4, 8), -- 2.7.4 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH 2/5] dt-bindings: clock: uniphier: Add NX1 clock binding 2021-10-05 2:08 [PATCH 0/5] clk: uniphier: Introduce some clock features and NX1 support Kunihiko Hayashi 2021-10-05 2:08 ` [PATCH 1/5] clk: uniphier: Add audio system and video input clock control for PXs3 Kunihiko Hayashi @ 2021-10-05 2:08 ` Kunihiko Hayashi 2021-10-05 2:08 ` [PATCH 3/5] clk: uniphier: Add NX1 clock support Kunihiko Hayashi ` (2 subsequent siblings) 4 siblings, 0 replies; 8+ messages in thread From: Kunihiko Hayashi @ 2021-10-05 2:08 UTC (permalink / raw) To: Michael Turquette, Stephen Boyd, Rob Herring, Masami Hiramatsu Cc: linux-clk, devicetree, linux-arm-kernel, linux-kernel, Kunihiko Hayashi Update clock binding document for UniPhier NX1 SoC. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> --- Documentation/devicetree/bindings/clock/socionext,uniphier-clock.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/socionext,uniphier-clock.yaml b/Documentation/devicetree/bindings/clock/socionext,uniphier-clock.yaml index c3930ed..ee8d16a 100644 --- a/Documentation/devicetree/bindings/clock/socionext,uniphier-clock.yaml +++ b/Documentation/devicetree/bindings/clock/socionext,uniphier-clock.yaml @@ -23,6 +23,7 @@ properties: - socionext,uniphier-ld11-clock - socionext,uniphier-ld20-clock - socionext,uniphier-pxs3-clock + - socionext,uniphier-nx1-clock - description: Media I/O (MIO) clock, SD clock enum: - socionext,uniphier-ld4-mio-clock @@ -33,6 +34,7 @@ properties: - socionext,uniphier-ld11-mio-clock - socionext,uniphier-ld20-sd-clock - socionext,uniphier-pxs3-sd-clock + - socionext,uniphier-nx1-sd-clock - description: Peripheral clock enum: - socionext,uniphier-ld4-peri-clock @@ -43,6 +45,7 @@ properties: - socionext,uniphier-ld11-peri-clock - socionext,uniphier-ld20-peri-clock - socionext,uniphier-pxs3-peri-clock + - socionext,uniphier-nx1-peri-clock "#clock-cells": const: 1 -- 2.7.4 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH 3/5] clk: uniphier: Add NX1 clock support 2021-10-05 2:08 [PATCH 0/5] clk: uniphier: Introduce some clock features and NX1 support Kunihiko Hayashi 2021-10-05 2:08 ` [PATCH 1/5] clk: uniphier: Add audio system and video input clock control for PXs3 Kunihiko Hayashi 2021-10-05 2:08 ` [PATCH 2/5] dt-bindings: clock: uniphier: Add NX1 clock binding Kunihiko Hayashi @ 2021-10-05 2:08 ` Kunihiko Hayashi 2021-10-05 2:08 ` [PATCH 4/5] dt-bindings: clock: uniphier: Add clock binding for SoC-glue Kunihiko Hayashi 2021-10-05 2:08 ` [PATCH 5/5] clk: uniphier: Add SoC-glue clock source selector support for Pro4 Kunihiko Hayashi 4 siblings, 0 replies; 8+ messages in thread From: Kunihiko Hayashi @ 2021-10-05 2:08 UTC (permalink / raw) To: Michael Turquette, Stephen Boyd, Rob Herring, Masami Hiramatsu Cc: linux-clk, devicetree, linux-arm-kernel, linux-kernel, Kunihiko Hayashi Add basic clock data for UniPhier NX1 SoC. This includes PLL and clock division data for cpufreq support. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> --- drivers/clk/uniphier/clk-uniphier-core.c | 12 ++++++++++++ drivers/clk/uniphier/clk-uniphier-sys.c | 28 ++++++++++++++++++++++++++++ drivers/clk/uniphier/clk-uniphier.h | 5 +++++ 3 files changed, 45 insertions(+) diff --git a/drivers/clk/uniphier/clk-uniphier-core.c b/drivers/clk/uniphier/clk-uniphier-core.c index 1238023..0a947e7 100644 --- a/drivers/clk/uniphier/clk-uniphier-core.c +++ b/drivers/clk/uniphier/clk-uniphier-core.c @@ -132,6 +132,10 @@ static const struct of_device_id uniphier_clk_match[] = { .compatible = "socionext,uniphier-pxs3-clock", .data = uniphier_pxs3_sys_clk_data, }, + { + .compatible = "socionext,uniphier-nx1-clock", + .data = uniphier_nx1_sys_clk_data, + }, /* Media I/O clock, SD clock */ { .compatible = "socionext,uniphier-ld4-mio-clock", @@ -165,6 +169,10 @@ static const struct of_device_id uniphier_clk_match[] = { .compatible = "socionext,uniphier-pxs3-sd-clock", .data = uniphier_pro5_sd_clk_data, }, + { + .compatible = "socionext,uniphier-nx1-sd-clock", + .data = uniphier_pro5_sd_clk_data, + }, /* Peripheral clock */ { .compatible = "socionext,uniphier-ld4-peri-clock", @@ -198,6 +206,10 @@ static const struct of_device_id uniphier_clk_match[] = { .compatible = "socionext,uniphier-pxs3-peri-clock", .data = uniphier_pro4_peri_clk_data, }, + { + .compatible = "socionext,uniphier-nx1-peri-clock", + .data = uniphier_pro4_peri_clk_data, + }, { /* sentinel */ } }; diff --git a/drivers/clk/uniphier/clk-uniphier-sys.c b/drivers/clk/uniphier/clk-uniphier-sys.c index 0ec28eb..e8bf85c 100644 --- a/drivers/clk/uniphier/clk-uniphier-sys.c +++ b/drivers/clk/uniphier/clk-uniphier-sys.c @@ -20,6 +20,10 @@ UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 10), \ UNIPHIER_CLK_FACTOR("sd-133m", -1, "spll", 1, 15) +#define UNIPHIER_NX1_SYS_CLK_SD \ + UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 4), \ + UNIPHIER_CLK_FACTOR("sd-133m", -1, "spll", 1, 6) + #define UNIPHIER_LD4_SYS_CLK_NAND(idx) \ UNIPHIER_CLK_FACTOR("nand-50m", -1, "spll", 1, 32), \ UNIPHIER_CLK_GATE("nand", (idx), "nand-50m", 0x2104, 2) @@ -302,3 +306,27 @@ const struct uniphier_clk_data uniphier_pxs3_sys_clk_data[] = { "spll/4", "spll/8", "s2pll/4", "s2pll/8"), { /* sentinel */ } }; + +const struct uniphier_clk_data uniphier_nx1_sys_clk_data[] = { + UNIPHIER_CLK_FACTOR("cpll", -1, "ref", 100, 1), /* ARM: 2500 MHz */ + UNIPHIER_CLK_FACTOR("spll", -1, "ref", 32, 1), /* 800 MHz */ + UNIPHIER_CLK_FACTOR("uart", 0, "spll", 1, 6), + UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 16), + UNIPHIER_NX1_SYS_CLK_SD, + UNIPHIER_CLK_GATE("emmc", 4, NULL, 0x2108, 8), + UNIPHIER_CLK_GATE("ether", 6, NULL, 0x210c, 0), + UNIPHIER_CLK_GATE("usb30-0", 12, NULL, 0x210c, 16), /* =GIO */ + UNIPHIER_CLK_GATE("usb30-1", 13, NULL, 0x210c, 20), /* =GIO1P */ + UNIPHIER_CLK_GATE("usb30-hsphy0", 16, NULL, 0x210c, 24), + UNIPHIER_CLK_GATE("usb30-ssphy0", 17, NULL, 0x210c, 25), + UNIPHIER_CLK_GATE("usb30-ssphy1", 18, NULL, 0x210c, 26), + UNIPHIER_CLK_GATE("pcie", 24, NULL, 0x210c, 8), + UNIPHIER_CLK_GATE("voc", 52, NULL, 0x2110, 0), + UNIPHIER_CLK_GATE("hdmitx", 58, NULL, 0x2110, 8), + /* CPU gears */ + UNIPHIER_CLK_DIV5("cpll", 2, 4, 8, 16, 32), + UNIPHIER_CLK_CPUGEAR("cpu-ca53", 33, 0x8080, 0xf, 5, + "cpll/2", "cpll/4", "cpll/8", "cpll/16", + "cpll/32"), + { /* sentinel */ } +}; diff --git a/drivers/clk/uniphier/clk-uniphier.h b/drivers/clk/uniphier/clk-uniphier.h index 9e30362..c54fb78 100644 --- a/drivers/clk/uniphier/clk-uniphier.h +++ b/drivers/clk/uniphier/clk-uniphier.h @@ -119,6 +119,10 @@ struct uniphier_clk_data { UNIPHIER_CLK_DIV2(parent, div0, div1), \ UNIPHIER_CLK_DIV2(parent, div2, div3) +#define UNIPHIER_CLK_DIV5(parent, div0, div1, div2, div3, div4) \ + UNIPHIER_CLK_DIV4(parent, div0, div1, div2, div3), \ + UNIPHIER_CLK_DIV(parent, div4) + struct clk_hw *uniphier_clk_register_cpugear(struct device *dev, struct regmap *regmap, const char *name, @@ -146,6 +150,7 @@ extern const struct uniphier_clk_data uniphier_pxs2_sys_clk_data[]; extern const struct uniphier_clk_data uniphier_ld11_sys_clk_data[]; extern const struct uniphier_clk_data uniphier_ld20_sys_clk_data[]; extern const struct uniphier_clk_data uniphier_pxs3_sys_clk_data[]; +extern const struct uniphier_clk_data uniphier_nx1_sys_clk_data[]; extern const struct uniphier_clk_data uniphier_ld4_mio_clk_data[]; extern const struct uniphier_clk_data uniphier_pro5_sd_clk_data[]; extern const struct uniphier_clk_data uniphier_ld4_peri_clk_data[]; -- 2.7.4 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH 4/5] dt-bindings: clock: uniphier: Add clock binding for SoC-glue 2021-10-05 2:08 [PATCH 0/5] clk: uniphier: Introduce some clock features and NX1 support Kunihiko Hayashi ` (2 preceding siblings ...) 2021-10-05 2:08 ` [PATCH 3/5] clk: uniphier: Add NX1 clock support Kunihiko Hayashi @ 2021-10-05 2:08 ` Kunihiko Hayashi 2021-10-05 12:26 ` Rob Herring 2021-10-05 2:08 ` [PATCH 5/5] clk: uniphier: Add SoC-glue clock source selector support for Pro4 Kunihiko Hayashi 4 siblings, 1 reply; 8+ messages in thread From: Kunihiko Hayashi @ 2021-10-05 2:08 UTC (permalink / raw) To: Michael Turquette, Stephen Boyd, Rob Herring, Masami Hiramatsu Cc: linux-clk, devicetree, linux-arm-kernel, linux-kernel, Kunihiko Hayashi Update binding document for clocks implemented in SoC-glue. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> --- .../bindings/clock/socionext,uniphier-clock.yaml | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/socionext,uniphier-clock.yaml b/Documentation/devicetree/bindings/clock/socionext,uniphier-clock.yaml index ee8d16a..d1ac311 100644 --- a/Documentation/devicetree/bindings/clock/socionext,uniphier-clock.yaml +++ b/Documentation/devicetree/bindings/clock/socionext,uniphier-clock.yaml @@ -46,6 +46,9 @@ properties: - socionext,uniphier-ld20-peri-clock - socionext,uniphier-pxs3-peri-clock - socionext,uniphier-nx1-peri-clock + - description: SoC-glue clock + enum: + - socionext,uniphier-pro4-sg-clock "#clock-cells": const: 1 @@ -95,3 +98,16 @@ examples: // other nodes ... }; + + - | + soc-glue@5f800000 { + compatible = "socionext,uniphier-sysctrl", "simple-mfd", "syscon"; + reg = <0x5f800000 0x2000>; + + clock { + compatible = "socionext,uniphier-pro4-sg-clock"; + #clock-cells = <1>; + }; + + // other nodes ... + }; -- 2.7.4 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH 4/5] dt-bindings: clock: uniphier: Add clock binding for SoC-glue 2021-10-05 2:08 ` [PATCH 4/5] dt-bindings: clock: uniphier: Add clock binding for SoC-glue Kunihiko Hayashi @ 2021-10-05 12:26 ` Rob Herring 2021-10-05 14:16 ` Kunihiko Hayashi 0 siblings, 1 reply; 8+ messages in thread From: Rob Herring @ 2021-10-05 12:26 UTC (permalink / raw) To: Kunihiko Hayashi Cc: linux-arm-kernel, Stephen Boyd, linux-clk, Masami Hiramatsu, linux-kernel, devicetree, Michael Turquette, Rob Herring On Tue, 05 Oct 2021 11:08:25 +0900, Kunihiko Hayashi wrote: > Update binding document for clocks implemented in SoC-glue. > > Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> > --- > .../bindings/clock/socionext,uniphier-clock.yaml | 16 ++++++++++++++++ > 1 file changed, 16 insertions(+) > My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check' on your patch (DT_CHECKER_FLAGS is new in v5.13): yamllint warnings/errors: ./Documentation/devicetree/bindings/clock/socionext,uniphier-clock.yaml:51:1: [error] syntax error: found character '\t' that cannot start any token (syntax) dtschema/dtc warnings/errors: make[1]: *** Deleting file 'Documentation/devicetree/bindings/clock/socionext,uniphier-clock.example.dts' Traceback (most recent call last): File "/usr/local/bin/dt-extract-example", line 45, in <module> binding = yaml.load(open(args.yamlfile, encoding='utf-8').read()) File "/usr/local/lib/python3.8/dist-packages/ruamel/yaml/main.py", line 434, in load return constructor.get_single_data() File "/usr/local/lib/python3.8/dist-packages/ruamel/yaml/constructor.py", line 120, in get_single_data node = self.composer.get_single_node() File "_ruamel_yaml.pyx", line 706, in _ruamel_yaml.CParser.get_single_node File "_ruamel_yaml.pyx", line 724, in _ruamel_yaml.CParser._compose_document File "_ruamel_yaml.pyx", line 775, in _ruamel_yaml.CParser._compose_node File "_ruamel_yaml.pyx", line 889, in _ruamel_yaml.CParser._compose_mapping_node File "_ruamel_yaml.pyx", line 775, in _ruamel_yaml.CParser._compose_node File "_ruamel_yaml.pyx", line 889, in _ruamel_yaml.CParser._compose_mapping_node File "_ruamel_yaml.pyx", line 775, in _ruamel_yaml.CParser._compose_node File "_ruamel_yaml.pyx", line 889, in _ruamel_yaml.CParser._compose_mapping_node File "_ruamel_yaml.pyx", line 773, in _ruamel_yaml.CParser._compose_node File "_ruamel_yaml.pyx", line 850, in _ruamel_yaml.CParser._compose_sequence_node File "_ruamel_yaml.pyx", line 775, in _ruamel_yaml.CParser._compose_node File "_ruamel_yaml.pyx", line 889, in _ruamel_yaml.CParser._compose_mapping_node File "_ruamel_yaml.pyx", line 731, in _ruamel_yaml.CParser._compose_node File "_ruamel_yaml.pyx", line 904, in _ruamel_yaml.CParser._parse_next_event ruamel.yaml.scanner.ScannerError: while scanning for the next token found character that cannot start any token in "<unicode string>", line 51, column 1 make[1]: *** [Documentation/devicetree/bindings/Makefile:20: Documentation/devicetree/bindings/clock/socionext,uniphier-clock.example.dts] Error 1 make[1]: *** Waiting for unfinished jobs.... ./Documentation/devicetree/bindings/clock/socionext,uniphier-clock.yaml: while scanning for the next token found character that cannot start any token in "<unicode string>", line 51, column 1 /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/clock/socionext,uniphier-clock.yaml: ignoring, error parsing file warning: no schema found in file: ./Documentation/devicetree/bindings/clock/socionext,uniphier-clock.yaml make: *** [Makefile:1441: dt_binding_check] Error 2 doc reference errors (make refcheckdocs): See https://patchwork.ozlabs.org/patch/1536449 This check can fail if there are any dependencies. The base for a patch series is generally the most recent rc1. If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date: pip3 install dtschema --upgrade Please check and re-submit. ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 4/5] dt-bindings: clock: uniphier: Add clock binding for SoC-glue 2021-10-05 12:26 ` Rob Herring @ 2021-10-05 14:16 ` Kunihiko Hayashi 0 siblings, 0 replies; 8+ messages in thread From: Kunihiko Hayashi @ 2021-10-05 14:16 UTC (permalink / raw) To: Rob Herring Cc: linux-arm-kernel, Stephen Boyd, linux-clk, Masami Hiramatsu, linux-kernel, devicetree, Michael Turquette, Rob Herring On 2021/10/05 21:26, Rob Herring wrote: > On Tue, 05 Oct 2021 11:08:25 +0900, Kunihiko Hayashi wrote: >> Update binding document for clocks implemented in SoC-glue. >> >> Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> >> --- >> .../bindings/clock/socionext,uniphier-clock.yaml | 16 > ++++++++++++++++ >> 1 file changed, 16 insertions(+) >> > > My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check' > on your patch (DT_CHECKER_FLAGS is new in v5.13): > > yamllint warnings/errors: > ./Documentation/devicetree/bindings/clock/socionext,uniphier-clock.yaml:51 > :1: [error] syntax error: found character '\t' that cannot start any token > (syntax) I made mistake. I'll fix it in next. Thank you, --- Best Regards Kunihiko Hayashi ^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH 5/5] clk: uniphier: Add SoC-glue clock source selector support for Pro4 2021-10-05 2:08 [PATCH 0/5] clk: uniphier: Introduce some clock features and NX1 support Kunihiko Hayashi ` (3 preceding siblings ...) 2021-10-05 2:08 ` [PATCH 4/5] dt-bindings: clock: uniphier: Add clock binding for SoC-glue Kunihiko Hayashi @ 2021-10-05 2:08 ` Kunihiko Hayashi 4 siblings, 0 replies; 8+ messages in thread From: Kunihiko Hayashi @ 2021-10-05 2:08 UTC (permalink / raw) To: Michael Turquette, Stephen Boyd, Rob Herring, Masami Hiramatsu Cc: linux-clk, devicetree, linux-arm-kernel, linux-kernel, Kunihiko Hayashi Add SoC-glue clock source selector for ahci controller on UniPhier SoCs. Currently this supports Pro4 only. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> --- drivers/clk/uniphier/clk-uniphier-core.c | 5 +++++ drivers/clk/uniphier/clk-uniphier-sys.c | 17 +++++++++++++++++ drivers/clk/uniphier/clk-uniphier.h | 1 + 3 files changed, 23 insertions(+) diff --git a/drivers/clk/uniphier/clk-uniphier-core.c b/drivers/clk/uniphier/clk-uniphier-core.c index 0a947e7..46c66fa 100644 --- a/drivers/clk/uniphier/clk-uniphier-core.c +++ b/drivers/clk/uniphier/clk-uniphier-core.c @@ -210,6 +210,11 @@ static const struct of_device_id uniphier_clk_match[] = { .compatible = "socionext,uniphier-nx1-peri-clock", .data = uniphier_pro4_peri_clk_data, }, + /* SoC-glue clock */ + { + .compatible = "socionext,uniphier-pro4-sg-clock", + .data = uniphier_pro4_sg_clk_data, + }, { /* sentinel */ } }; diff --git a/drivers/clk/uniphier/clk-uniphier-sys.c b/drivers/clk/uniphier/clk-uniphier-sys.c index e8bf85c..0180470 100644 --- a/drivers/clk/uniphier/clk-uniphier-sys.c +++ b/drivers/clk/uniphier/clk-uniphier-sys.c @@ -330,3 +330,20 @@ const struct uniphier_clk_data uniphier_nx1_sys_clk_data[] = { "cpll/32"), { /* sentinel */ } }; + +const struct uniphier_clk_data uniphier_pro4_sg_clk_data[] = { + UNIPHIER_CLK_DIV("gpll", 4), + { + .name = "sata-ref", + .type = UNIPHIER_CLK_TYPE_MUX, + .idx = 0, + .data.mux = { + .parent_names = { "gpll/4", "ref", }, + .num_parents = 2, + .reg = 0x1a28, + .masks = { 0x1, 0x1, }, + .vals = { 0x0, 0x1, }, + }, + }, + { /* sentinel */ } +}; diff --git a/drivers/clk/uniphier/clk-uniphier.h b/drivers/clk/uniphier/clk-uniphier.h index c54fb78..dea0c78 100644 --- a/drivers/clk/uniphier/clk-uniphier.h +++ b/drivers/clk/uniphier/clk-uniphier.h @@ -155,5 +155,6 @@ extern const struct uniphier_clk_data uniphier_ld4_mio_clk_data[]; extern const struct uniphier_clk_data uniphier_pro5_sd_clk_data[]; extern const struct uniphier_clk_data uniphier_ld4_peri_clk_data[]; extern const struct uniphier_clk_data uniphier_pro4_peri_clk_data[]; +extern const struct uniphier_clk_data uniphier_pro4_sg_clk_data[]; #endif /* __CLK_UNIPHIER_H__ */ -- 2.7.4 ^ permalink raw reply related [flat|nested] 8+ messages in thread
end of thread, other threads:[~2021-10-05 14:16 UTC | newest] Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2021-10-05 2:08 [PATCH 0/5] clk: uniphier: Introduce some clock features and NX1 support Kunihiko Hayashi 2021-10-05 2:08 ` [PATCH 1/5] clk: uniphier: Add audio system and video input clock control for PXs3 Kunihiko Hayashi 2021-10-05 2:08 ` [PATCH 2/5] dt-bindings: clock: uniphier: Add NX1 clock binding Kunihiko Hayashi 2021-10-05 2:08 ` [PATCH 3/5] clk: uniphier: Add NX1 clock support Kunihiko Hayashi 2021-10-05 2:08 ` [PATCH 4/5] dt-bindings: clock: uniphier: Add clock binding for SoC-glue Kunihiko Hayashi 2021-10-05 12:26 ` Rob Herring 2021-10-05 14:16 ` Kunihiko Hayashi 2021-10-05 2:08 ` [PATCH 5/5] clk: uniphier: Add SoC-glue clock source selector support for Pro4 Kunihiko Hayashi
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