From: Richard Zhu <hongxing.zhu@nxp.com>
To: l.stach@pengutronix.de, tharvey@gateworks.com, kishon@ti.com,
vkoul@kernel.org, robh@kernel.org, galak@kernel.crashing.org,
shawnguo@kernel.org
Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, kernel@pengutronix.de,
linux-imx@nxp.com, Richard Zhu <hongxing.zhu@nxp.com>
Subject: [PATCH v3 2/9] dt-bindings: phy: add imx8 pcie phy driver support
Date: Tue, 12 Oct 2021 16:41:11 +0800 [thread overview]
Message-ID: <1634028078-2387-3-git-send-email-hongxing.zhu@nxp.com> (raw)
In-Reply-To: <1634028078-2387-1-git-send-email-hongxing.zhu@nxp.com>
Add dt-binding for the standalone i.MX8 PCIe PHY driver.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
---
.../bindings/phy/fsl,imx8-pcie-phy.yaml | 79 +++++++++++++++++++
1 file changed, 79 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml
diff --git a/Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml
new file mode 100644
index 000000000000..7973abf67278
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml
@@ -0,0 +1,79 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/fsl,imx8-pcie-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale i.MX8 SoC series PCIe PHY Device Tree Bindings
+
+maintainers:
+ - Richard Zhu <hongxing.zhu@nxp.com>
+
+properties:
+ "#phy-cells":
+ const: 0
+
+ compatible:
+ enum:
+ - fsl,imx8mm-pcie-phy
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: PHY module clock
+
+ clock-names:
+ items:
+ - const: ref
+
+ resets:
+ items:
+ - description: Phandles to PCIe-related reset lines exposed by SRC
+ IP block.
+
+ reset-names:
+ items:
+ - const: pciephy
+
+ fsl,refclk-pad-mode:
+ description: |
+ Specifies the mode of the refclk pad used. It can be UNUSED(PHY
+ refclock is derived from SoC internal source), INPUT(PHY refclock
+ is provided externally via the refclk pad) or OUTPUT(PHY refclock
+ is derived from SoC internal source and provided on the refclk pad).
+ Refer include/dt-bindings/phy/phy-imx8-pcie.h for the constants
+ to be used.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [ 0, 1, 2 ]
+
+required:
+ - "#phy-cells"
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - fsl,refclk-pad-mode
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/imx8mm-clock.h>
+ #include <dt-bindings/phy/phy-imx8-pcie.h>
+
+ pcie_phy: pcie-phy@32f00000 {
+ compatible = "fsl,imx8mm-pcie-phy";
+ reg = <0x32f00000 0x10000>;
+ clocks = <&clk IMX8MM_CLK_PCIE1_PHY>;
+ clock-names = "ref";
+ assigned-clocks = <&clk IMX8MM_CLK_PCIE1_PHY>;
+ assigned-clock-rates = <100000000>;
+ assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_100M>;
+ resets = <&src IMX8MQ_RESET_PCIEPHY>;
+ reset-names = "pciephy";
+ fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
+ #phy-cells = <0>;
+ };
+...
--
2.25.1
next prev parent reply other threads:[~2021-10-12 9:07 UTC|newest]
Thread overview: 48+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-12 8:41 [PATCH v3 0/9] add the imx8m pcie phy driver and imx8mm pcie support Richard Zhu
2021-10-12 8:41 ` [PATCH v3 1/9] dt-bindings: phy: phy-imx8-pcie: Add binding for the pad modes of imx8 pcie phy Richard Zhu
2021-10-12 8:41 ` Richard Zhu [this message]
2021-10-12 13:18 ` [PATCH v3 2/9] dt-bindings: phy: add imx8 pcie phy driver support Rob Herring
2021-10-12 23:46 ` Richard Zhu
2021-10-12 8:41 ` [PATCH v3 3/9] arm64: dts: imx8mm: add the pcie phy support Richard Zhu
2021-10-15 18:30 ` Lucas Stach
2021-10-22 1:57 ` Richard Zhu
2021-10-12 8:41 ` [PATCH v3 4/9] arm64: dts: imx8mm-evk: " Richard Zhu
2021-10-15 18:32 ` Lucas Stach
2021-10-22 1:58 ` Richard Zhu
2021-10-12 8:41 ` [PATCH v3 5/9] phy: freescale: pcie: initialize the imx8 pcie standalone phy driver Richard Zhu
2021-10-15 18:55 ` Lucas Stach
2021-10-22 4:30 ` Richard Zhu
2021-10-21 16:00 ` Tim Harvey
2021-10-22 0:54 ` Richard Zhu
2021-10-12 8:41 ` [PATCH v3 6/9] dt-bindings: imx6q-pcie: Add PHY phandles and name properties Richard Zhu
2021-10-18 19:18 ` Rob Herring
2021-10-22 2:04 ` Richard Zhu
2021-10-12 8:41 ` [PATCH v3 7/9] arm64: dts: imx8mm: add the pcie support Richard Zhu
2021-10-12 8:41 ` [PATCH v3 8/9] arm64: dts: imx8mm-evk: add the pcie support on imx8mm evk board Richard Zhu
2021-10-15 19:03 ` Lucas Stach
2021-10-22 2:07 ` Richard Zhu
2021-10-12 8:41 ` [PATCH v3 9/9] PCI: imx: add the imx8mm pcie support Richard Zhu
2021-10-13 12:45 ` Matthias Schiffer
2021-10-14 1:20 ` Richard Zhu
2021-10-15 19:00 ` Lucas Stach
2021-10-22 2:06 ` Richard Zhu
2021-10-15 19:58 ` [PATCH v3 0/9] add the imx8m pcie phy driver and " Tim Harvey
2021-10-19 2:10 ` Richard Zhu
2021-10-19 15:52 ` Tim Harvey
2021-10-20 2:10 ` Richard Zhu
2021-10-20 21:22 ` Tim Harvey
2021-10-21 3:32 ` Richard Zhu
2021-10-21 16:25 ` Tim Harvey
2021-10-22 0:43 ` Richard Zhu
2021-10-22 15:59 ` Tim Harvey
2021-10-22 16:55 ` Tim Harvey
2021-10-25 2:12 ` Richard Zhu
2021-10-25 7:23 ` Richard Zhu
2021-10-25 17:14 ` Tim Harvey
2021-10-26 5:41 ` Richard Zhu
2021-10-26 16:06 ` Tim Harvey
2021-10-27 6:18 ` Richard Zhu
2021-10-27 15:40 ` Tim Harvey
2021-10-28 1:51 ` Richard Zhu
2021-10-26 15:56 ` Marcel Ziswiler
2021-10-27 1:39 ` Richard Zhu
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