* [PATCH] perf/x86/msr: Add Sapphire Rapids CPU support
@ 2021-10-06 20:12 kan.liang
2021-10-15 9:32 ` [tip: perf/urgent] " tip-bot2 for Kan Liang
0 siblings, 1 reply; 2+ messages in thread
From: kan.liang @ 2021-10-06 20:12 UTC (permalink / raw)
To: peterz; +Cc: linux-kernel, ak, Kan Liang
From: Kan Liang <kan.liang@linux.intel.com>
SMI_COUNT MSR is supported on Sapphire Rapids CPU.
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
---
arch/x86/events/msr.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/x86/events/msr.c b/arch/x86/events/msr.c
index c853b28..96c775a 100644
--- a/arch/x86/events/msr.c
+++ b/arch/x86/events/msr.c
@@ -68,6 +68,7 @@ static bool test_intel(int idx, void *data)
case INTEL_FAM6_BROADWELL_D:
case INTEL_FAM6_BROADWELL_G:
case INTEL_FAM6_BROADWELL_X:
+ case INTEL_FAM6_SAPPHIRERAPIDS_X:
case INTEL_FAM6_ATOM_SILVERMONT:
case INTEL_FAM6_ATOM_SILVERMONT_D:
--
2.7.4
^ permalink raw reply related [flat|nested] 2+ messages in thread
* [tip: perf/urgent] perf/x86/msr: Add Sapphire Rapids CPU support
2021-10-06 20:12 [PATCH] perf/x86/msr: Add Sapphire Rapids CPU support kan.liang
@ 2021-10-15 9:32 ` tip-bot2 for Kan Liang
0 siblings, 0 replies; 2+ messages in thread
From: tip-bot2 for Kan Liang @ 2021-10-15 9:32 UTC (permalink / raw)
To: linux-tip-commits; +Cc: Kan Liang, Peter Zijlstra (Intel), x86, linux-kernel
The following commit has been merged into the perf/urgent branch of tip:
Commit-ID: 71920ea97d6d1d800ee8b51951dc3fda3f5dc698
Gitweb: https://git.kernel.org/tip/71920ea97d6d1d800ee8b51951dc3fda3f5dc698
Author: Kan Liang <kan.liang@linux.intel.com>
AuthorDate: Wed, 06 Oct 2021 13:12:17 -07:00
Committer: Peter Zijlstra <peterz@infradead.org>
CommitterDate: Fri, 15 Oct 2021 11:25:26 +02:00
perf/x86/msr: Add Sapphire Rapids CPU support
SMI_COUNT MSR is supported on Sapphire Rapids CPU.
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://lkml.kernel.org/r/1633551137-192083-1-git-send-email-kan.liang@linux.intel.com
---
arch/x86/events/msr.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/x86/events/msr.c b/arch/x86/events/msr.c
index c853b28..96c775a 100644
--- a/arch/x86/events/msr.c
+++ b/arch/x86/events/msr.c
@@ -68,6 +68,7 @@ static bool test_intel(int idx, void *data)
case INTEL_FAM6_BROADWELL_D:
case INTEL_FAM6_BROADWELL_G:
case INTEL_FAM6_BROADWELL_X:
+ case INTEL_FAM6_SAPPHIRERAPIDS_X:
case INTEL_FAM6_ATOM_SILVERMONT:
case INTEL_FAM6_ATOM_SILVERMONT_D:
^ permalink raw reply related [flat|nested] 2+ messages in thread
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2021-10-06 20:12 [PATCH] perf/x86/msr: Add Sapphire Rapids CPU support kan.liang
2021-10-15 9:32 ` [tip: perf/urgent] " tip-bot2 for Kan Liang
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