From: cy_huang <u0084500@gmail.com>
To: broonie@kernel.org, perex@perex.cz, tiwai@suse.com
Cc: oder_chiou@realtek.com, lgirdwood@gmail.com,
alsa-devel@alsa-project.org, linux-kernel@vger.kernel.org,
cy_huang@richtek.com, allen_lin@richtek.com
Subject: [PATCH v2 1/3] ASoC: rt9120: Update internal ocp level to the correct value
Date: Wed, 10 Nov 2021 11:45:19 +0800 [thread overview]
Message-ID: <1636515921-31694-2-git-send-email-u0084500@gmail.com> (raw)
In-Reply-To: <1636515921-31694-1-git-send-email-u0084500@gmail.com>
From: ChiYuan Huang <cy_huang@richtek.com>
Update internal ocp level to correct value.
Even the wrong ocp setting can also make the sound output, but the power
cannot match the IC capability.
Signed-off-by: ChiYuan Huang <cy_huang@richtek.com>
---
sound/soc/codecs/rt9120.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/sound/soc/codecs/rt9120.c b/sound/soc/codecs/rt9120.c
index f957498..032c520 100644
--- a/sound/soc/codecs/rt9120.c
+++ b/sound/soc/codecs/rt9120.c
@@ -149,8 +149,7 @@ static int rt9120_codec_probe(struct snd_soc_component *comp)
snd_soc_component_init_regmap(comp, data->regmap);
/* Internal setting */
- snd_soc_component_write(comp, RT9120_REG_INTERNAL1, 0x03);
- snd_soc_component_write(comp, RT9120_REG_INTERNAL0, 0x69);
+ snd_soc_component_write(comp, RT9120_REG_INTERNAL0, 0x04);
return 0;
}
--
2.7.4
next prev parent reply other threads:[~2021-11-10 3:45 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-11-10 3:45 [PATCH v2 0/3] ASoC: rt9120: Fix settings and make compatible with rt9120s cy_huang
2021-11-10 3:45 ` cy_huang [this message]
2021-11-10 3:45 ` [PATCH v2 2/3] ASoC: rt9120: Fix clock auto sync issue when fs is the multiple of 48 cy_huang
2021-11-10 3:45 ` [PATCH v2 3/3] ASoC: rt9120: Add the compatibility with rt9120s cy_huang
2021-11-12 21:27 ` [PATCH v2 0/3] ASoC: rt9120: Fix settings and make compatible " Mark Brown
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