From: cy_huang <u0084500@gmail.com>
To: broonie@kernel.org, perex@perex.cz, tiwai@suse.com
Cc: oder_chiou@realtek.com, lgirdwood@gmail.com,
alsa-devel@alsa-project.org, linux-kernel@vger.kernel.org,
cy_huang@richtek.com, allen_lin@richtek.com
Subject: [PATCH v2 2/3] ASoC: rt9120: Fix clock auto sync issue when fs is the multiple of 48
Date: Wed, 10 Nov 2021 11:45:20 +0800 [thread overview]
Message-ID: <1636515921-31694-3-git-send-email-u0084500@gmail.com> (raw)
In-Reply-To: <1636515921-31694-1-git-send-email-u0084500@gmail.com>
From: ChiYuan Huang <cy_huang@richtek.com>
If fs is divided by 48, to make audio clock sync rate correct, internal
sync function have be disabled.
Signed-off-by: ChiYuan Huang <cy_huang@richtek.com>
---
sound/soc/codecs/rt9120.c | 24 +++++++++++++++++++-----
1 file changed, 19 insertions(+), 5 deletions(-)
diff --git a/sound/soc/codecs/rt9120.c b/sound/soc/codecs/rt9120.c
index 032c520..981aead 100644
--- a/sound/soc/codecs/rt9120.c
+++ b/sound/soc/codecs/rt9120.c
@@ -26,6 +26,7 @@
#define RT9120_REG_INTERNAL0 0x65
#define RT9120_REG_INTERNAL1 0x69
#define RT9120_REG_UVPOPT 0x6C
+#define RT9120_REG_DIGCFG 0xF8
#define RT9120_VID_MASK GENMASK(15, 8)
#define RT9120_SWRST_MASK BIT(7)
@@ -46,6 +47,7 @@
#define RT9120_CFG_WORDLEN_24 24
#define RT9120_CFG_WORDLEN_32 32
#define RT9120_DVDD_UVSEL_MASK GENMASK(5, 4)
+#define RT9120_AUTOSYNC_MASK BIT(6)
#define RT9120_VENDOR_ID 0x4200
#define RT9120_RESET_WAITMS 20
@@ -200,8 +202,8 @@ static int rt9120_hw_params(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_soc_component *comp = dai->component;
- unsigned int param_width, param_slot_width;
- int width;
+ unsigned int param_width, param_slot_width, auto_sync;
+ int width, fs;
switch (width = params_width(param)) {
case 16:
@@ -239,6 +241,16 @@ static int rt9120_hw_params(struct snd_pcm_substream *substream,
snd_soc_component_update_bits(comp, RT9120_REG_I2SWL,
RT9120_AUDWL_MASK, param_slot_width);
+
+ fs = width * params_channels(param);
+ /* If fs is divided by 48, disable auto sync */
+ if (fs % 48 == 0)
+ auto_sync = 0;
+ else
+ auto_sync = RT9120_AUTOSYNC_MASK;
+
+ snd_soc_component_update_bits(comp, RT9120_REG_DIGCFG,
+ RT9120_AUTOSYNC_MASK, auto_sync);
return 0;
}
@@ -280,7 +292,8 @@ static const struct regmap_range rt9120_rd_yes_ranges[] = {
regmap_reg_range(0x3A, 0x40),
regmap_reg_range(0x65, 0x65),
regmap_reg_range(0x69, 0x69),
- regmap_reg_range(0x6C, 0x6C)
+ regmap_reg_range(0x6C, 0x6C),
+ regmap_reg_range(0xF8, 0xF8)
};
static const struct regmap_access_table rt9120_rd_table = {
@@ -298,7 +311,8 @@ static const struct regmap_range rt9120_wr_yes_ranges[] = {
regmap_reg_range(0x40, 0x40),
regmap_reg_range(0x65, 0x65),
regmap_reg_range(0x69, 0x69),
- regmap_reg_range(0x6C, 0x6C)
+ regmap_reg_range(0x6C, 0x6C),
+ regmap_reg_range(0xF8, 0xF8)
};
static const struct regmap_access_table rt9120_wr_table = {
@@ -369,7 +383,7 @@ static int rt9120_reg_write(void *context, unsigned int reg, unsigned int val)
static const struct regmap_config rt9120_regmap_config = {
.reg_bits = 8,
.val_bits = 32,
- .max_register = RT9120_REG_UVPOPT,
+ .max_register = RT9120_REG_DIGCFG,
.reg_read = rt9120_reg_read,
.reg_write = rt9120_reg_write,
--
2.7.4
next prev parent reply other threads:[~2021-11-10 3:45 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-11-10 3:45 [PATCH v2 0/3] ASoC: rt9120: Fix settings and make compatible with rt9120s cy_huang
2021-11-10 3:45 ` [PATCH v2 1/3] ASoC: rt9120: Update internal ocp level to the correct value cy_huang
2021-11-10 3:45 ` cy_huang [this message]
2021-11-10 3:45 ` [PATCH v2 3/3] ASoC: rt9120: Add the compatibility with rt9120s cy_huang
2021-11-12 21:27 ` [PATCH v2 0/3] ASoC: rt9120: Fix settings and make compatible " Mark Brown
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