* [PATCH] soc/tegra: fuse: update nvmem cell list
@ 2021-12-06 11:52 Kartik
2022-02-09 17:35 ` Thierry Reding
0 siblings, 1 reply; 2+ messages in thread
From: Kartik @ 2021-12-06 11:52 UTC (permalink / raw)
To: linux-tegra, linux-kernel, jonathanh, thierry.reding, digetx
Cc: kkartik, smangipudi, pshete
From: kartik <kkartik@nvidia.com>
Update tegra_fuse_cells with below entries:
- gcplex-config-fuse:
Configuration bits for GPU, used to enable/disable write protected
region used for storing GPU firmware.
- pdi0:
Unique per chip public identifier.
- pdi1:
Unique per chip public identifier.
Signed-off-by: Prathamesh Shete <pshete@nvidia.com>
Signed-off-by: kartik <kkartik@nvidia.com>
---
drivers/soc/tegra/fuse/fuse-tegra.c | 20 +++++++++++++++++++-
1 file changed, 19 insertions(+), 1 deletion(-)
diff --git a/drivers/soc/tegra/fuse/fuse-tegra.c b/drivers/soc/tegra/fuse/fuse-tegra.c
index f215181..c65252e 100644
--- a/drivers/soc/tegra/fuse/fuse-tegra.c
+++ b/drivers/soc/tegra/fuse/fuse-tegra.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2013-2021, NVIDIA CORPORATION. All rights reserved.
*/
#include <linux/clk.h>
@@ -161,6 +161,12 @@ static const struct nvmem_cell_info tegra_fuse_cells[] = {
.bit_offset = 0,
.nbits = 32,
}, {
+ .name = "gcplex-config-fuse",
+ .offset = 0x1c8,
+ .bytes = 4,
+ .bit_offset = 0,
+ .nbits = 32,
+ }, {
.name = "tsensor-realignment",
.offset = 0x1fc,
.bytes = 4,
@@ -178,6 +184,18 @@ static const struct nvmem_cell_info tegra_fuse_cells[] = {
.bytes = 4,
.bit_offset = 0,
.nbits = 32,
+ }, {
+ .name = "pdi0",
+ .offset = 0x300,
+ .bytes = 4,
+ .bit_offset = 0,
+ .nbits = 32,
+ }, {
+ .name = "pdi1",
+ .offset = 0x304,
+ .bytes = 4,
+ .bit_offset = 0,
+ .nbits = 32,
},
};
--
2.7.4
^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [PATCH] soc/tegra: fuse: update nvmem cell list
2021-12-06 11:52 [PATCH] soc/tegra: fuse: update nvmem cell list Kartik
@ 2022-02-09 17:35 ` Thierry Reding
0 siblings, 0 replies; 2+ messages in thread
From: Thierry Reding @ 2022-02-09 17:35 UTC (permalink / raw)
To: Kartik; +Cc: linux-tegra, linux-kernel, jonathanh, digetx, smangipudi, pshete
[-- Attachment #1: Type: text/plain, Size: 663 bytes --]
On Mon, Dec 06, 2021 at 05:22:45PM +0530, Kartik wrote:
> From: kartik <kkartik@nvidia.com>
>
> Update tegra_fuse_cells with below entries:
> - gcplex-config-fuse:
> Configuration bits for GPU, used to enable/disable write protected
> region used for storing GPU firmware.
> - pdi0:
> Unique per chip public identifier.
> - pdi1:
> Unique per chip public identifier.
>
> Signed-off-by: Prathamesh Shete <pshete@nvidia.com>
> Signed-off-by: kartik <kkartik@nvidia.com>
> ---
> drivers/soc/tegra/fuse/fuse-tegra.c | 20 +++++++++++++++++++-
> 1 file changed, 19 insertions(+), 1 deletion(-)
Applied, thanks.
Thierry
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2022-02-09 17:35 ` Thierry Reding
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