From: "tip-bot2 for Maciej W. Rozycki" <tip-bot2@linutronix.de>
To: linux-tip-commits@vger.kernel.org
Cc: "Maciej W. Rozycki" <macro@orcam.me.uk>,
Thomas Gleixner <tglx@linutronix.de>,
x86@kernel.org, linux-kernel@vger.kernel.org
Subject: [tip: x86/irq] x86/PCI: Add $IRT PIRQ routing table support
Date: Wed, 02 Feb 2022 20:30:40 -0000 [thread overview]
Message-ID: <164383384095.16921.8293739918583226276.tip-bot2@tip-bot2> (raw)
In-Reply-To: <alpine.DEB.2.21.2201022058050.56863@angie.orcam.me.uk>
The following commit has been merged into the x86/irq branch of tip:
Commit-ID: d1ba93f1f1844e969051e144b4c3b30780fc4812
Gitweb: https://git.kernel.org/tip/d1ba93f1f1844e969051e144b4c3b30780fc4812
Author: Maciej W. Rozycki <macro@orcam.me.uk>
AuthorDate: Thu, 06 Jan 2022 11:24:11
Committer: Thomas Gleixner <tglx@linutronix.de>
CommitterDate: Wed, 02 Feb 2022 21:27:55 +01:00
x86/PCI: Add $IRT PIRQ routing table support
Handle the $IRT PCI IRQ Routing Table format used by AMI for its BCP
(BIOS Configuration Program) external tool meant for tweaking BIOS
structures without the need to rebuild it from sources[1].
The $IRT format has been invented by AMI before Microsoft has come up
with its $PIR format and a $IRT table is therefore there in some systems
that lack a $PIR table, such as the DataExpert EXP8449 mainboard based
on the ALi FinALi 486 chipset (M1489/M1487), which predates DMI 2.0 and
cannot therefore be easily identified at run time.
Unlike with the $PIR format there is no alignment guarantee as to the
placement of the $IRT table, so scan the whole BIOS area bytewise.
Credit to Michal Necasek for helping to chase documentation for the
format.
References:
[1] "What is BCP? - AMI", <https://www.ami.com/what-is-bcp/>
Signed-off-by: Maciej W. Rozycki <macro@orcam.me.uk>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Link: https://lore.kernel.org/r/alpine.DEB.2.21.2201022058050.56863@angie.orcam.me.uk
---
arch/x86/include/asm/pci_x86.h | 8 ++++-
arch/x86/pci/irq.c | 70 +++++++++++++++++++++++++++++++++-
2 files changed, 78 insertions(+)
diff --git a/arch/x86/include/asm/pci_x86.h b/arch/x86/include/asm/pci_x86.h
index 490411d..7be45da 100644
--- a/arch/x86/include/asm/pci_x86.h
+++ b/arch/x86/include/asm/pci_x86.h
@@ -90,6 +90,14 @@ struct irq_routing_table {
struct irq_info slots[0];
} __attribute__((packed));
+struct irt_routing_table {
+ u32 signature; /* IRT_SIGNATURE should be here */
+ u8 size; /* Number of entries provided */
+ u8 used; /* Number of entries actually used */
+ u16 exclusive_irqs; /* IRQs devoted exclusively to PCI usage */
+ struct irq_info slots[0];
+} __packed;
+
extern unsigned int pcibios_irq_mask;
extern raw_spinlock_t pci_config_lock;
diff --git a/arch/x86/pci/irq.c b/arch/x86/pci/irq.c
index 7113688..486ba58 100644
--- a/arch/x86/pci/irq.c
+++ b/arch/x86/pci/irq.c
@@ -25,6 +25,8 @@
#define PIRQ_SIGNATURE (('$' << 0) + ('P' << 8) + ('I' << 16) + ('R' << 24))
#define PIRQ_VERSION 0x0100
+#define IRT_SIGNATURE (('$' << 0) + ('I' << 8) + ('R' << 16) + ('T' << 24))
+
static int broken_hp_bios_irq9;
static int acer_tm360_irqrouting;
@@ -91,7 +93,69 @@ static inline struct irq_routing_table *pirq_check_routing_table(u8 *addr)
return NULL;
}
+/*
+ * Handle the $IRT PCI IRQ Routing Table format used by AMI for its BCP
+ * (BIOS Configuration Program) external tool meant for tweaking BIOS
+ * structures without the need to rebuild it from sources. The $IRT
+ * format has been invented by AMI before Microsoft has come up with its
+ * $PIR format and a $IRT table is therefore there in some systems that
+ * lack a $PIR table.
+ *
+ * It uses the same PCI BIOS 2.1 format for interrupt routing entries
+ * themselves but has a different simpler header prepended instead,
+ * occupying 8 bytes, where a `$IRT' signature is followed by one byte
+ * specifying the total number of interrupt routing entries allocated in
+ * the table, then one byte specifying the actual number of entries used
+ * (which the BCP tool can take advantage of when modifying the table),
+ * and finally a 16-bit word giving the IRQs devoted exclusively to PCI.
+ * Unlike with the $PIR table there is no alignment guarantee.
+ *
+ * Given the similarity of the two formats the $IRT one is trivial to
+ * convert to the $PIR one, which we do here, except that obviously we
+ * have no information as to the router device to use, but we can handle
+ * it by matching PCI device IDs actually seen on the bus against ones
+ * that our individual routers recognise.
+ *
+ * Reportedly there is another $IRT table format where a 16-bit word
+ * follows the header instead that points to interrupt routing entries
+ * in a $PIR table provided elsewhere. In that case this code will not
+ * be reached though as the $PIR table will have been chosen instead.
+ */
+static inline struct irq_routing_table *pirq_convert_irt_table(u8 *addr)
+{
+ struct irt_routing_table *ir;
+ struct irq_routing_table *rt;
+ u16 size;
+ u8 sum;
+ int i;
+
+ ir = (struct irt_routing_table *)addr;
+ if (ir->signature != IRT_SIGNATURE || !ir->used || ir->size < ir->used)
+ return NULL;
+
+ DBG(KERN_DEBUG "PCI: $IRT Interrupt Routing Table found at 0x%lx\n",
+ __pa(ir));
+
+ size = sizeof(*rt) + ir->used * sizeof(rt->slots[0]);
+ rt = kzalloc(size, GFP_KERNEL);
+ if (!rt)
+ return NULL;
+
+ rt->signature = PIRQ_SIGNATURE;
+ rt->version = PIRQ_VERSION;
+ rt->size = size;
+ rt->exclusive_irqs = ir->exclusive_irqs;
+ for (i = 0; i < ir->used; i++)
+ rt->slots[i] = ir->slots[i];
+
+ addr = (u8 *)rt;
+ sum = 0;
+ for (i = 0; i < size; i++)
+ sum += addr[i];
+ rt->checksum = -sum;
+ return rt;
+}
/*
* Search 0xf0000 -- 0xfffff for the PCI IRQ Routing Table.
@@ -113,6 +177,12 @@ static struct irq_routing_table * __init pirq_find_routing_table(void)
if (rt)
return rt;
}
+
+ for (addr = (u8 *)__va(0xf0000); addr < (u8 *)__va(0x100000); addr++) {
+ rt = pirq_convert_irt_table(addr);
+ if (rt)
+ return rt;
+ }
return NULL;
}
next prev parent reply other threads:[~2022-02-02 20:30 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-01-06 11:24 [PATCH v3 0/4] x86/PCI: Improve $PIR and add $IRT PIRQ routing support Maciej W. Rozycki
2022-01-06 11:24 ` [PATCH v3 1/4] x86/PCI: Handle PIRQ routing tables with no router device given Maciej W. Rozycki
2022-02-02 20:30 ` [tip: x86/irq] " tip-bot2 for Maciej W. Rozycki
2022-01-06 11:24 ` [PATCH v3 2/4] x86/PCI: Add $IRT PIRQ routing table support Maciej W. Rozycki
2022-02-02 20:30 ` tip-bot2 for Maciej W. Rozycki [this message]
2022-03-14 22:37 ` Dmitry Osipenko
2022-03-16 18:09 ` Maciej W. Rozycki
2022-03-21 16:50 ` Dmitry Osipenko
2022-01-06 11:24 ` [PATCH v3 3/4] x86/PCI: Fix ALi M1487 (IBC) PIRQ router link value interpretation Maciej W. Rozycki
2022-02-02 20:30 ` [tip: x86/irq] " tip-bot2 for Maciej W. Rozycki
2022-01-06 11:24 ` [PATCH v3 4/4] x86/PCI: Fix coding style in PIRQ table search functions Maciej W. Rozycki
2022-02-02 20:30 ` [tip: x86/irq] " tip-bot2 for Maciej W. Rozycki
2022-02-01 10:50 ` [PING][PATCH v3 0/4] x86/PCI: Improve $PIR and add $IRT PIRQ routing support Maciej W. Rozycki
2022-02-02 10:13 ` [PATCH " Thomas Gleixner
2022-02-03 10:28 ` Maciej W. Rozycki
2022-03-31 7:11 [PATCH v4 3/5] x86/PCI: Add $IRT PIRQ routing table support Maciej W. Rozycki
2022-04-10 10:54 ` [tip: x86/irq] " tip-bot2 for Maciej W. Rozycki
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