* [PATCH v3 0/3] PCI: Introduce UniPhier NX1 PCI endpoint controller support
@ 2022-02-10 8:09 Kunihiko Hayashi
2022-02-10 8:09 ` [PATCH v3 1/3] dt-bindings: PCI: uniphier-ep: Add bindings for NX1 SoC Kunihiko Hayashi
` (3 more replies)
0 siblings, 4 replies; 5+ messages in thread
From: Kunihiko Hayashi @ 2022-02-10 8:09 UTC (permalink / raw)
To: Bjorn Helgaas, Rob Herring, Lorenzo Pieralisi,
Krzysztof Wilczyński, Masami Hiramatsu
Cc: linux-pci, devicetree, linux-arm-kernel, linux-kernel, Kunihiko Hayashi
This series includes the patches to add basic support for the PCI endpoint
controller implemented in NX1 SoC.
This defines SoC-dependent data to distinguish existing functions and flags
for Pro5 and NX1 SoCs.
Changes since v2:
- Add .init(), .wait(), and has_gio to SoC-dependent data instead of
"is_legacy" flag
- Rename uniphier_pcie_init_ep_legacy() with uniphier_pcie_pro5_init_ep()
- Rename uniphier_pcie_init_ep() and uniphier_pcie_wait_ep() with
uniphier_pcie_nx1_init_ep() and uniphier_pcie_nx1_wait_ep()
- Add Reviewed-by: lines
Changes since v1:
- Fix dt-bindings warnings
Kunihiko Hayashi (3):
dt-bindings: PCI: uniphier-ep: Add bindings for NX1 SoC
PCI: uniphier-ep: Add SoC data structure
PCI: uniphier-ep: Add NX1 support
.../bindings/pci/socionext,uniphier-pcie-ep.yaml | 22 +++-
drivers/pci/controller/dwc/pcie-uniphier-ep.c | 142 ++++++++++++++++++---
2 files changed, 138 insertions(+), 26 deletions(-)
--
2.7.4
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH v3 1/3] dt-bindings: PCI: uniphier-ep: Add bindings for NX1 SoC
2022-02-10 8:09 [PATCH v3 0/3] PCI: Introduce UniPhier NX1 PCI endpoint controller support Kunihiko Hayashi
@ 2022-02-10 8:09 ` Kunihiko Hayashi
2022-02-10 8:09 ` [PATCH v3 2/3] PCI: uniphier-ep: Add SoC data structure Kunihiko Hayashi
` (2 subsequent siblings)
3 siblings, 0 replies; 5+ messages in thread
From: Kunihiko Hayashi @ 2022-02-10 8:09 UTC (permalink / raw)
To: Bjorn Helgaas, Rob Herring, Lorenzo Pieralisi,
Krzysztof Wilczyński, Masami Hiramatsu
Cc: linux-pci, devicetree, linux-arm-kernel, linux-kernel, Kunihiko Hayashi
Update PCI endpoint binding document for UniPhier NX1 SoC. Add a compatible
string, clock and reset lines for the SoC to the document.
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
---
.../bindings/pci/socionext,uniphier-pcie-ep.yaml | 22 +++++++++++++++-------
1 file changed, 15 insertions(+), 7 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/socionext,uniphier-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/socionext,uniphier-pcie-ep.yaml
index 179ab0858482..437e61618d06 100644
--- a/Documentation/devicetree/bindings/pci/socionext,uniphier-pcie-ep.yaml
+++ b/Documentation/devicetree/bindings/pci/socionext,uniphier-pcie-ep.yaml
@@ -20,7 +20,9 @@ allOf:
properties:
compatible:
- const: socionext,uniphier-pro5-pcie-ep
+ enum:
+ - socionext,uniphier-pro5-pcie-ep
+ - socionext,uniphier-nx1-pcie-ep
reg:
minItems: 4
@@ -41,20 +43,26 @@ properties:
- const: atu
clocks:
+ minItems: 1
maxItems: 2
clock-names:
- items:
- - const: gio
- - const: link
+ oneOf:
+ - items: # for Pro5
+ - const: gio
+ - const: link
+ - const: link # for NX1
resets:
+ minItems: 1
maxItems: 2
reset-names:
- items:
- - const: gio
- - const: link
+ oneOf:
+ - items: # for Pro5
+ - const: gio
+ - const: link
+ - const: link # for NX1
num-ib-windows:
const: 16
--
2.7.4
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH v3 2/3] PCI: uniphier-ep: Add SoC data structure
2022-02-10 8:09 [PATCH v3 0/3] PCI: Introduce UniPhier NX1 PCI endpoint controller support Kunihiko Hayashi
2022-02-10 8:09 ` [PATCH v3 1/3] dt-bindings: PCI: uniphier-ep: Add bindings for NX1 SoC Kunihiko Hayashi
@ 2022-02-10 8:09 ` Kunihiko Hayashi
2022-02-10 8:09 ` [PATCH v3 3/3] PCI: uniphier-ep: Add NX1 support Kunihiko Hayashi
2022-02-11 16:28 ` [PATCH v3 0/3] PCI: Introduce UniPhier NX1 PCI endpoint controller support Lorenzo Pieralisi
3 siblings, 0 replies; 5+ messages in thread
From: Kunihiko Hayashi @ 2022-02-10 8:09 UTC (permalink / raw)
To: Bjorn Helgaas, Rob Herring, Lorenzo Pieralisi,
Krzysztof Wilczyński, Masami Hiramatsu
Cc: linux-pci, devicetree, linux-arm-kernel, linux-kernel, Kunihiko Hayashi
Define SoC data structure that includes pci_epc_features, SoC-dependent
callback functions and flags to distinguish the behavior of each SoC.
The callback functions define init() to initialize the controller and
wait() to wait until initialization is completed.
Rename uniphier_pcie_init_ep() to uniphier_pcie_pro5_init_ep() for
initializing PCIe controller implemented in Pro5 SoC. And Pro5 SoC
doesn't have wait() function.
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
---
drivers/pci/controller/dwc/pcie-uniphier-ep.c | 61 ++++++++++++++++++---------
1 file changed, 42 insertions(+), 19 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-uniphier-ep.c b/drivers/pci/controller/dwc/pcie-uniphier-ep.c
index 69810c6b0d58..6c035fc45aaa 100644
--- a/drivers/pci/controller/dwc/pcie-uniphier-ep.c
+++ b/drivers/pci/controller/dwc/pcie-uniphier-ep.c
@@ -60,7 +60,14 @@ struct uniphier_pcie_ep_priv {
struct clk *clk, *clk_gio;
struct reset_control *rst, *rst_gio;
struct phy *phy;
- const struct pci_epc_features *features;
+ const struct uniphier_pcie_ep_soc_data *data;
+};
+
+struct uniphier_pcie_ep_soc_data {
+ bool has_gio;
+ void (*init)(struct uniphier_pcie_ep_priv *priv);
+ int (*wait)(struct uniphier_pcie_ep_priv *priv);
+ const struct pci_epc_features features;
};
#define to_uniphier_pcie(x) dev_get_drvdata((x)->dev)
@@ -91,7 +98,7 @@ static void uniphier_pcie_phy_reset(struct uniphier_pcie_ep_priv *priv,
writel(val, priv->base + PCL_RSTCTRL2);
}
-static void uniphier_pcie_init_ep(struct uniphier_pcie_ep_priv *priv)
+static void uniphier_pcie_pro5_init_ep(struct uniphier_pcie_ep_priv *priv)
{
u32 val;
@@ -209,7 +216,7 @@ uniphier_pcie_get_features(struct dw_pcie_ep *ep)
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
struct uniphier_pcie_ep_priv *priv = to_uniphier_pcie(pci);
- return priv->features;
+ return &priv->data->features;
}
static const struct dw_pcie_ep_ops uniphier_pcie_ep_ops = {
@@ -238,7 +245,8 @@ static int uniphier_pcie_ep_enable(struct uniphier_pcie_ep_priv *priv)
if (ret)
goto out_rst_assert;
- uniphier_pcie_init_ep(priv);
+ if (priv->data->init)
+ priv->data->init(priv);
uniphier_pcie_phy_reset(priv, true);
@@ -248,8 +256,16 @@ static int uniphier_pcie_ep_enable(struct uniphier_pcie_ep_priv *priv)
uniphier_pcie_phy_reset(priv, false);
+ if (priv->data->wait) {
+ ret = priv->data->wait(priv);
+ if (ret)
+ goto out_phy_exit;
+ }
+
return 0;
+out_phy_exit:
+ phy_exit(priv->phy);
out_rst_gio_assert:
reset_control_assert(priv->rst_gio);
out_rst_assert:
@@ -277,8 +293,8 @@ static int uniphier_pcie_ep_probe(struct platform_device *pdev)
if (!priv)
return -ENOMEM;
- priv->features = of_device_get_match_data(dev);
- if (WARN_ON(!priv->features))
+ priv->data = of_device_get_match_data(dev);
+ if (WARN_ON(!priv->data))
return -EINVAL;
priv->pci.dev = dev;
@@ -288,13 +304,15 @@ static int uniphier_pcie_ep_probe(struct platform_device *pdev)
if (IS_ERR(priv->base))
return PTR_ERR(priv->base);
- priv->clk_gio = devm_clk_get(dev, "gio");
- if (IS_ERR(priv->clk_gio))
- return PTR_ERR(priv->clk_gio);
+ if (priv->data->has_gio) {
+ priv->clk_gio = devm_clk_get(dev, "gio");
+ if (IS_ERR(priv->clk_gio))
+ return PTR_ERR(priv->clk_gio);
- priv->rst_gio = devm_reset_control_get_shared(dev, "gio");
- if (IS_ERR(priv->rst_gio))
- return PTR_ERR(priv->rst_gio);
+ priv->rst_gio = devm_reset_control_get_shared(dev, "gio");
+ if (IS_ERR(priv->rst_gio))
+ return PTR_ERR(priv->rst_gio);
+ }
priv->clk = devm_clk_get(dev, "link");
if (IS_ERR(priv->clk))
@@ -321,13 +339,18 @@ static int uniphier_pcie_ep_probe(struct platform_device *pdev)
return dw_pcie_ep_init(&priv->pci.ep);
}
-static const struct pci_epc_features uniphier_pro5_data = {
- .linkup_notifier = false,
- .msi_capable = true,
- .msix_capable = false,
- .align = 1 << 16,
- .bar_fixed_64bit = BIT(BAR_0) | BIT(BAR_2) | BIT(BAR_4),
- .reserved_bar = BIT(BAR_4),
+static const struct uniphier_pcie_ep_soc_data uniphier_pro5_data = {
+ .has_gio = true,
+ .init = uniphier_pcie_pro5_init_ep,
+ .wait = NULL,
+ .features = {
+ .linkup_notifier = false,
+ .msi_capable = true,
+ .msix_capable = false,
+ .align = 1 << 16,
+ .bar_fixed_64bit = BIT(BAR_0) | BIT(BAR_2) | BIT(BAR_4),
+ .reserved_bar = BIT(BAR_4),
+ },
};
static const struct of_device_id uniphier_pcie_ep_match[] = {
--
2.7.4
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH v3 3/3] PCI: uniphier-ep: Add NX1 support
2022-02-10 8:09 [PATCH v3 0/3] PCI: Introduce UniPhier NX1 PCI endpoint controller support Kunihiko Hayashi
2022-02-10 8:09 ` [PATCH v3 1/3] dt-bindings: PCI: uniphier-ep: Add bindings for NX1 SoC Kunihiko Hayashi
2022-02-10 8:09 ` [PATCH v3 2/3] PCI: uniphier-ep: Add SoC data structure Kunihiko Hayashi
@ 2022-02-10 8:09 ` Kunihiko Hayashi
2022-02-11 16:28 ` [PATCH v3 0/3] PCI: Introduce UniPhier NX1 PCI endpoint controller support Lorenzo Pieralisi
3 siblings, 0 replies; 5+ messages in thread
From: Kunihiko Hayashi @ 2022-02-10 8:09 UTC (permalink / raw)
To: Bjorn Helgaas, Rob Herring, Lorenzo Pieralisi,
Krzysztof Wilczyński, Masami Hiramatsu
Cc: linux-pci, devicetree, linux-arm-kernel, linux-kernel, Kunihiko Hayashi
Add basic support for UniPhier NX1 SoC as non-legacy SoC. This includes
a compatible string, SoC-dependent data containing init() and wait()
functions for the controller.
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
---
drivers/pci/controller/dwc/pcie-uniphier-ep.c | 81 +++++++++++++++++++++++++++
1 file changed, 81 insertions(+)
diff --git a/drivers/pci/controller/dwc/pcie-uniphier-ep.c b/drivers/pci/controller/dwc/pcie-uniphier-ep.c
index 6c035fc45aaa..4d0a587c0ba5 100644
--- a/drivers/pci/controller/dwc/pcie-uniphier-ep.c
+++ b/drivers/pci/controller/dwc/pcie-uniphier-ep.c
@@ -10,6 +10,7 @@
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/init.h>
+#include <linux/iopoll.h>
#include <linux/of_device.h>
#include <linux/pci.h>
#include <linux/phy/phy.h>
@@ -31,6 +32,17 @@
#define PCL_RSTCTRL2 0x0024
#define PCL_RSTCTRL_PHY_RESET BIT(0)
+#define PCL_PINCTRL0 0x002c
+#define PCL_PERST_PLDN_REGEN BIT(12)
+#define PCL_PERST_NOE_REGEN BIT(11)
+#define PCL_PERST_OUT_REGEN BIT(8)
+#define PCL_PERST_PLDN_REGVAL BIT(4)
+#define PCL_PERST_NOE_REGVAL BIT(3)
+#define PCL_PERST_OUT_REGVAL BIT(0)
+
+#define PCL_PIPEMON 0x0044
+#define PCL_PCLK_ALIVE BIT(15)
+
#define PCL_MODE 0x8000
#define PCL_MODE_REGEN BIT(8)
#define PCL_MODE_REGVAL BIT(0)
@@ -51,6 +63,9 @@
#define PCL_APP_INTX 0x8074
#define PCL_APP_INTX_SYS_INT BIT(0)
+#define PCL_APP_PM0 0x8078
+#define PCL_SYS_AUX_PWR_DET BIT(8)
+
/* assertion time of INTx in usec */
#define PCL_INTX_WIDTH_USEC 30
@@ -123,6 +138,55 @@ static void uniphier_pcie_pro5_init_ep(struct uniphier_pcie_ep_priv *priv)
msleep(100);
}
+static void uniphier_pcie_nx1_init_ep(struct uniphier_pcie_ep_priv *priv)
+{
+ u32 val;
+
+ /* set EP mode */
+ val = readl(priv->base + PCL_MODE);
+ val |= PCL_MODE_REGEN | PCL_MODE_REGVAL;
+ writel(val, priv->base + PCL_MODE);
+
+ /* use auxiliary power detection */
+ val = readl(priv->base + PCL_APP_PM0);
+ val |= PCL_SYS_AUX_PWR_DET;
+ writel(val, priv->base + PCL_APP_PM0);
+
+ /* assert PERST# */
+ val = readl(priv->base + PCL_PINCTRL0);
+ val &= ~(PCL_PERST_NOE_REGVAL | PCL_PERST_OUT_REGVAL
+ | PCL_PERST_PLDN_REGVAL);
+ val |= PCL_PERST_NOE_REGEN | PCL_PERST_OUT_REGEN
+ | PCL_PERST_PLDN_REGEN;
+ writel(val, priv->base + PCL_PINCTRL0);
+
+ uniphier_pcie_ltssm_enable(priv, false);
+
+ usleep_range(100000, 200000);
+
+ /* deassert PERST# */
+ val = readl(priv->base + PCL_PINCTRL0);
+ val |= PCL_PERST_OUT_REGVAL | PCL_PERST_OUT_REGEN;
+ writel(val, priv->base + PCL_PINCTRL0);
+}
+
+static int uniphier_pcie_nx1_wait_ep(struct uniphier_pcie_ep_priv *priv)
+{
+ u32 status;
+ int ret;
+
+ /* wait PIPE clock */
+ ret = readl_poll_timeout(priv->base + PCL_PIPEMON, status,
+ status & PCL_PCLK_ALIVE, 100000, 1000000);
+ if (ret) {
+ dev_err(priv->pci.dev,
+ "Failed to initialize controller in EP mode\n");
+ return ret;
+ }
+
+ return 0;
+}
+
static int uniphier_pcie_start_link(struct dw_pcie *pci)
{
struct uniphier_pcie_ep_priv *priv = to_uniphier_pcie(pci);
@@ -353,11 +417,28 @@ static const struct uniphier_pcie_ep_soc_data uniphier_pro5_data = {
},
};
+static const struct uniphier_pcie_ep_soc_data uniphier_nx1_data = {
+ .has_gio = false,
+ .init = uniphier_pcie_nx1_init_ep,
+ .wait = uniphier_pcie_nx1_wait_ep,
+ .features = {
+ .linkup_notifier = false,
+ .msi_capable = true,
+ .msix_capable = false,
+ .align = 1 << 12,
+ .bar_fixed_64bit = BIT(BAR_0) | BIT(BAR_2) | BIT(BAR_4),
+ },
+};
+
static const struct of_device_id uniphier_pcie_ep_match[] = {
{
.compatible = "socionext,uniphier-pro5-pcie-ep",
.data = &uniphier_pro5_data,
},
+ {
+ .compatible = "socionext,uniphier-nx1-pcie-ep",
+ .data = &uniphier_nx1_data,
+ },
{ /* sentinel */ },
};
--
2.7.4
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH v3 0/3] PCI: Introduce UniPhier NX1 PCI endpoint controller support
2022-02-10 8:09 [PATCH v3 0/3] PCI: Introduce UniPhier NX1 PCI endpoint controller support Kunihiko Hayashi
` (2 preceding siblings ...)
2022-02-10 8:09 ` [PATCH v3 3/3] PCI: uniphier-ep: Add NX1 support Kunihiko Hayashi
@ 2022-02-11 16:28 ` Lorenzo Pieralisi
3 siblings, 0 replies; 5+ messages in thread
From: Lorenzo Pieralisi @ 2022-02-11 16:28 UTC (permalink / raw)
To: Bjorn Helgaas, Krzysztof Wilczyński, Kunihiko Hayashi,
Masami Hiramatsu, Rob Herring
Cc: Lorenzo Pieralisi, linux-kernel, devicetree, linux-arm-kernel, linux-pci
On Thu, 10 Feb 2022 17:09:53 +0900, Kunihiko Hayashi wrote:
> This series includes the patches to add basic support for the PCI endpoint
> controller implemented in NX1 SoC.
>
> This defines SoC-dependent data to distinguish existing functions and flags
> for Pro5 and NX1 SoCs.
>
> Changes since v2:
> - Add .init(), .wait(), and has_gio to SoC-dependent data instead of
> "is_legacy" flag
> - Rename uniphier_pcie_init_ep_legacy() with uniphier_pcie_pro5_init_ep()
> - Rename uniphier_pcie_init_ep() and uniphier_pcie_wait_ep() with
> uniphier_pcie_nx1_init_ep() and uniphier_pcie_nx1_wait_ep()
> - Add Reviewed-by: lines
>
> [...]
Applied to pci/uniphier, thanks!
[1/3] dt-bindings: PCI: uniphier-ep: Add bindings for NX1 SoC
https://git.kernel.org/lpieralisi/pci/c/f28b24042b
[2/3] PCI: uniphier-ep: Add SoC data structure
https://git.kernel.org/lpieralisi/pci/c/d41584ae86
[3/3] PCI: uniphier-ep: Add NX1 support
https://git.kernel.org/lpieralisi/pci/c/892fdf15b8
Thanks,
Lorenzo
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2022-02-11 16:28 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-02-10 8:09 [PATCH v3 0/3] PCI: Introduce UniPhier NX1 PCI endpoint controller support Kunihiko Hayashi
2022-02-10 8:09 ` [PATCH v3 1/3] dt-bindings: PCI: uniphier-ep: Add bindings for NX1 SoC Kunihiko Hayashi
2022-02-10 8:09 ` [PATCH v3 2/3] PCI: uniphier-ep: Add SoC data structure Kunihiko Hayashi
2022-02-10 8:09 ` [PATCH v3 3/3] PCI: uniphier-ep: Add NX1 support Kunihiko Hayashi
2022-02-11 16:28 ` [PATCH v3 0/3] PCI: Introduce UniPhier NX1 PCI endpoint controller support Lorenzo Pieralisi
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).