* [PATCH V2 1/2] perf/x86/intel/pt: Add a capability and config bit for event tracing
2022-01-26 10:48 [PATCH V2 0/2] perf/x86/intel/pt: Add support for event tracing and TNT disabling Adrian Hunter
@ 2022-01-26 10:48 ` Adrian Hunter
2022-02-16 14:57 ` [tip: perf/core] " tip-bot2 for Alexander Shishkin
2022-01-26 10:48 ` [PATCH V2 2/2] perf/x86/intel/pt: Add a capability and config bit for disabling TNTs Adrian Hunter
` (3 subsequent siblings)
4 siblings, 1 reply; 11+ messages in thread
From: Adrian Hunter @ 2022-01-26 10:48 UTC (permalink / raw)
To: Peter Zijlstra
Cc: Alexander Shishkin, Andi Kleen, Arnaldo Carvalho de Melo,
Jiri Olsa, linux-kernel, Ingo Molnar, Borislav Petkov,
Dave Hansen, x86, H Peter Anvin
From: Alexander Shishkin <alexander.shishkin@linux.intel.com>
As of Intel SDM (https://www.intel.com/sdm) version 076, there is a new
Intel PT feature called Event Trace which is enabled config bit 31.
Event Trace exposes details about asynchronous events such as interrupts
and VM-Entry/Exit.
Add a capability and config bit for Event Trace.
Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Reviewed-by: Adrian Hunter <adrian.hunter@intel.com>
Signed-off-by: Adrian Hunter <adrian.hunter@intel.com>
---
arch/x86/events/intel/pt.c | 8 ++++++++
arch/x86/include/asm/intel_pt.h | 1 +
arch/x86/include/asm/msr-index.h | 1 +
3 files changed, 10 insertions(+)
diff --git a/arch/x86/events/intel/pt.c b/arch/x86/events/intel/pt.c
index 7f406c14715f..02727b9b3c8a 100644
--- a/arch/x86/events/intel/pt.c
+++ b/arch/x86/events/intel/pt.c
@@ -57,6 +57,7 @@ static struct pt_cap_desc {
PT_CAP(mtc, 0, CPUID_EBX, BIT(3)),
PT_CAP(ptwrite, 0, CPUID_EBX, BIT(4)),
PT_CAP(power_event_trace, 0, CPUID_EBX, BIT(5)),
+ PT_CAP(event_trace, 0, CPUID_EBX, BIT(7)),
PT_CAP(topa_output, 0, CPUID_ECX, BIT(0)),
PT_CAP(topa_multiple_entries, 0, CPUID_ECX, BIT(1)),
PT_CAP(single_range_output, 0, CPUID_ECX, BIT(2)),
@@ -108,6 +109,7 @@ PMU_FORMAT_ATTR(tsc, "config:10" );
PMU_FORMAT_ATTR(noretcomp, "config:11" );
PMU_FORMAT_ATTR(ptw, "config:12" );
PMU_FORMAT_ATTR(branch, "config:13" );
+PMU_FORMAT_ATTR(event, "config:31" );
PMU_FORMAT_ATTR(mtc_period, "config:14-17" );
PMU_FORMAT_ATTR(cyc_thresh, "config:19-22" );
PMU_FORMAT_ATTR(psb_period, "config:24-27" );
@@ -116,6 +118,7 @@ static struct attribute *pt_formats_attr[] = {
&format_attr_pt.attr,
&format_attr_cyc.attr,
&format_attr_pwr_evt.attr,
+ &format_attr_event.attr,
&format_attr_fup_on_ptw.attr,
&format_attr_mtc.attr,
&format_attr_tsc.attr,
@@ -296,6 +299,7 @@ static int __init pt_pmu_hw_init(void)
RTIT_CTL_CYC_PSB | \
RTIT_CTL_MTC | \
RTIT_CTL_PWR_EVT_EN | \
+ RTIT_CTL_EVENT_EN | \
RTIT_CTL_FUP_ON_PTW | \
RTIT_CTL_PTW_EN)
@@ -350,6 +354,10 @@ static bool pt_event_valid(struct perf_event *event)
!intel_pt_validate_hw_cap(PT_CAP_power_event_trace))
return false;
+ if (config & RTIT_CTL_EVENT_EN &&
+ !intel_pt_validate_hw_cap(PT_CAP_event_trace))
+ return false;
+
if (config & RTIT_CTL_PTW) {
if (!intel_pt_validate_hw_cap(PT_CAP_ptwrite))
return false;
diff --git a/arch/x86/include/asm/intel_pt.h b/arch/x86/include/asm/intel_pt.h
index ebe8d2ea44fe..d1ef9cb58847 100644
--- a/arch/x86/include/asm/intel_pt.h
+++ b/arch/x86/include/asm/intel_pt.h
@@ -13,6 +13,7 @@ enum pt_capabilities {
PT_CAP_mtc,
PT_CAP_ptwrite,
PT_CAP_power_event_trace,
+ PT_CAP_event_trace,
PT_CAP_topa_output,
PT_CAP_topa_multiple_entries,
PT_CAP_single_range_output,
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index 3faf0f97edb1..79b392d893e3 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -205,6 +205,7 @@
#define RTIT_CTL_DISRETC BIT(11)
#define RTIT_CTL_PTW_EN BIT(12)
#define RTIT_CTL_BRANCH_EN BIT(13)
+#define RTIT_CTL_EVENT_EN BIT(31)
#define RTIT_CTL_MTC_RANGE_OFFSET 14
#define RTIT_CTL_MTC_RANGE (0x0full << RTIT_CTL_MTC_RANGE_OFFSET)
#define RTIT_CTL_CYC_THRESH_OFFSET 19
--
2.25.1
^ permalink raw reply related [flat|nested] 11+ messages in thread* [tip: perf/core] perf/x86/intel/pt: Add a capability and config bit for event tracing
2022-01-26 10:48 ` [PATCH V2 1/2] perf/x86/intel/pt: Add a capability and config bit for event tracing Adrian Hunter
@ 2022-02-16 14:57 ` tip-bot2 for Alexander Shishkin
0 siblings, 0 replies; 11+ messages in thread
From: tip-bot2 for Alexander Shishkin @ 2022-02-16 14:57 UTC (permalink / raw)
To: linux-tip-commits
Cc: Alexander Shishkin, Adrian Hunter, Peter Zijlstra (Intel),
x86, linux-kernel
The following commit has been merged into the perf/core branch of tip:
Commit-ID: 28c24ded649cf068ca518f2a3d78f5e7e06d41d8
Gitweb: https://git.kernel.org/tip/28c24ded649cf068ca518f2a3d78f5e7e06d41d8
Author: Alexander Shishkin <alexander.shishkin@linux.intel.com>
AuthorDate: Wed, 26 Jan 2022 12:48:14 +02:00
Committer: Peter Zijlstra <peterz@infradead.org>
CommitterDate: Tue, 15 Feb 2022 17:47:11 +01:00
perf/x86/intel/pt: Add a capability and config bit for event tracing
As of Intel SDM (https://www.intel.com/sdm) version 076, there is a new
Intel PT feature called Event Trace which is enabled config bit 31.
Event Trace exposes details about asynchronous events such as interrupts
and VM-Entry/Exit.
Add a capability and config bit for Event Trace.
Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Signed-off-by: Adrian Hunter <adrian.hunter@intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Reviewed-by: Adrian Hunter <adrian.hunter@intel.com>
Link: https://lore.kernel.org/r/20220126104815.2807416-2-adrian.hunter@intel.com
---
arch/x86/events/intel/pt.c | 8 ++++++++
arch/x86/include/asm/intel_pt.h | 1 +
arch/x86/include/asm/msr-index.h | 1 +
3 files changed, 10 insertions(+)
diff --git a/arch/x86/events/intel/pt.c b/arch/x86/events/intel/pt.c
index f061dc2..f339c88 100644
--- a/arch/x86/events/intel/pt.c
+++ b/arch/x86/events/intel/pt.c
@@ -59,6 +59,7 @@ static struct pt_cap_desc {
PT_CAP(mtc, 0, CPUID_EBX, BIT(3)),
PT_CAP(ptwrite, 0, CPUID_EBX, BIT(4)),
PT_CAP(power_event_trace, 0, CPUID_EBX, BIT(5)),
+ PT_CAP(event_trace, 0, CPUID_EBX, BIT(7)),
PT_CAP(topa_output, 0, CPUID_ECX, BIT(0)),
PT_CAP(topa_multiple_entries, 0, CPUID_ECX, BIT(1)),
PT_CAP(single_range_output, 0, CPUID_ECX, BIT(2)),
@@ -110,6 +111,7 @@ PMU_FORMAT_ATTR(tsc, "config:10" );
PMU_FORMAT_ATTR(noretcomp, "config:11" );
PMU_FORMAT_ATTR(ptw, "config:12" );
PMU_FORMAT_ATTR(branch, "config:13" );
+PMU_FORMAT_ATTR(event, "config:31" );
PMU_FORMAT_ATTR(mtc_period, "config:14-17" );
PMU_FORMAT_ATTR(cyc_thresh, "config:19-22" );
PMU_FORMAT_ATTR(psb_period, "config:24-27" );
@@ -118,6 +120,7 @@ static struct attribute *pt_formats_attr[] = {
&format_attr_pt.attr,
&format_attr_cyc.attr,
&format_attr_pwr_evt.attr,
+ &format_attr_event.attr,
&format_attr_fup_on_ptw.attr,
&format_attr_mtc.attr,
&format_attr_tsc.attr,
@@ -298,6 +301,7 @@ fail:
RTIT_CTL_CYC_PSB | \
RTIT_CTL_MTC | \
RTIT_CTL_PWR_EVT_EN | \
+ RTIT_CTL_EVENT_EN | \
RTIT_CTL_FUP_ON_PTW | \
RTIT_CTL_PTW_EN)
@@ -352,6 +356,10 @@ static bool pt_event_valid(struct perf_event *event)
!intel_pt_validate_hw_cap(PT_CAP_power_event_trace))
return false;
+ if (config & RTIT_CTL_EVENT_EN &&
+ !intel_pt_validate_hw_cap(PT_CAP_event_trace))
+ return false;
+
if (config & RTIT_CTL_PTW) {
if (!intel_pt_validate_hw_cap(PT_CAP_ptwrite))
return false;
diff --git a/arch/x86/include/asm/intel_pt.h b/arch/x86/include/asm/intel_pt.h
index ebe8d2e..d1ef9cb 100644
--- a/arch/x86/include/asm/intel_pt.h
+++ b/arch/x86/include/asm/intel_pt.h
@@ -13,6 +13,7 @@ enum pt_capabilities {
PT_CAP_mtc,
PT_CAP_ptwrite,
PT_CAP_power_event_trace,
+ PT_CAP_event_trace,
PT_CAP_topa_output,
PT_CAP_topa_multiple_entries,
PT_CAP_single_range_output,
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index 3faf0f9..79b392d 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -205,6 +205,7 @@
#define RTIT_CTL_DISRETC BIT(11)
#define RTIT_CTL_PTW_EN BIT(12)
#define RTIT_CTL_BRANCH_EN BIT(13)
+#define RTIT_CTL_EVENT_EN BIT(31)
#define RTIT_CTL_MTC_RANGE_OFFSET 14
#define RTIT_CTL_MTC_RANGE (0x0full << RTIT_CTL_MTC_RANGE_OFFSET)
#define RTIT_CTL_CYC_THRESH_OFFSET 19
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH V2 2/2] perf/x86/intel/pt: Add a capability and config bit for disabling TNTs
2022-01-26 10:48 [PATCH V2 0/2] perf/x86/intel/pt: Add support for event tracing and TNT disabling Adrian Hunter
2022-01-26 10:48 ` [PATCH V2 1/2] perf/x86/intel/pt: Add a capability and config bit for event tracing Adrian Hunter
@ 2022-01-26 10:48 ` Adrian Hunter
2022-02-16 14:57 ` [tip: perf/core] " tip-bot2 for Alexander Shishkin
2022-02-08 6:28 ` [PATCH V2 0/2] perf/x86/intel/pt: Add support for event tracing and TNT disabling Adrian Hunter
` (2 subsequent siblings)
4 siblings, 1 reply; 11+ messages in thread
From: Adrian Hunter @ 2022-01-26 10:48 UTC (permalink / raw)
To: Peter Zijlstra
Cc: Alexander Shishkin, Andi Kleen, Arnaldo Carvalho de Melo,
Jiri Olsa, linux-kernel, Ingo Molnar, Borislav Petkov,
Dave Hansen, x86, H Peter Anvin
From: Alexander Shishkin <alexander.shishkin@linux.intel.com>
As of Intel SDM (https://www.intel.com/sdm) version 076, there is a new
Intel PT feature called TNT-Disable which is enabled config bit 55.
TNT-Disable disables TNT packets to reduce the tracing overhead, but with
the result that exact control flow information is lost.
Add a capability and config bit for TNT-Disable.
Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Reviewed-by: Adrian Hunter <adrian.hunter@intel.com>
Signed-off-by: Adrian Hunter <adrian.hunter@intel.com>
---
arch/x86/events/intel/pt.c | 8 ++++++++
arch/x86/include/asm/intel_pt.h | 1 +
arch/x86/include/asm/msr-index.h | 1 +
3 files changed, 10 insertions(+)
diff --git a/arch/x86/events/intel/pt.c b/arch/x86/events/intel/pt.c
index 02727b9b3c8a..ae396fdfabab 100644
--- a/arch/x86/events/intel/pt.c
+++ b/arch/x86/events/intel/pt.c
@@ -58,6 +58,7 @@ static struct pt_cap_desc {
PT_CAP(ptwrite, 0, CPUID_EBX, BIT(4)),
PT_CAP(power_event_trace, 0, CPUID_EBX, BIT(5)),
PT_CAP(event_trace, 0, CPUID_EBX, BIT(7)),
+ PT_CAP(tnt_disable, 0, CPUID_EBX, BIT(8)),
PT_CAP(topa_output, 0, CPUID_ECX, BIT(0)),
PT_CAP(topa_multiple_entries, 0, CPUID_ECX, BIT(1)),
PT_CAP(single_range_output, 0, CPUID_ECX, BIT(2)),
@@ -110,6 +111,7 @@ PMU_FORMAT_ATTR(noretcomp, "config:11" );
PMU_FORMAT_ATTR(ptw, "config:12" );
PMU_FORMAT_ATTR(branch, "config:13" );
PMU_FORMAT_ATTR(event, "config:31" );
+PMU_FORMAT_ATTR(notnt, "config:55" );
PMU_FORMAT_ATTR(mtc_period, "config:14-17" );
PMU_FORMAT_ATTR(cyc_thresh, "config:19-22" );
PMU_FORMAT_ATTR(psb_period, "config:24-27" );
@@ -119,6 +121,7 @@ static struct attribute *pt_formats_attr[] = {
&format_attr_cyc.attr,
&format_attr_pwr_evt.attr,
&format_attr_event.attr,
+ &format_attr_notnt.attr,
&format_attr_fup_on_ptw.attr,
&format_attr_mtc.attr,
&format_attr_tsc.attr,
@@ -300,6 +303,7 @@ static int __init pt_pmu_hw_init(void)
RTIT_CTL_MTC | \
RTIT_CTL_PWR_EVT_EN | \
RTIT_CTL_EVENT_EN | \
+ RTIT_CTL_NOTNT | \
RTIT_CTL_FUP_ON_PTW | \
RTIT_CTL_PTW_EN)
@@ -358,6 +362,10 @@ static bool pt_event_valid(struct perf_event *event)
!intel_pt_validate_hw_cap(PT_CAP_event_trace))
return false;
+ if (config & RTIT_CTL_NOTNT &&
+ !intel_pt_validate_hw_cap(PT_CAP_tnt_disable))
+ return false;
+
if (config & RTIT_CTL_PTW) {
if (!intel_pt_validate_hw_cap(PT_CAP_ptwrite))
return false;
diff --git a/arch/x86/include/asm/intel_pt.h b/arch/x86/include/asm/intel_pt.h
index d1ef9cb58847..c796e9bc98b6 100644
--- a/arch/x86/include/asm/intel_pt.h
+++ b/arch/x86/include/asm/intel_pt.h
@@ -14,6 +14,7 @@ enum pt_capabilities {
PT_CAP_ptwrite,
PT_CAP_power_event_trace,
PT_CAP_event_trace,
+ PT_CAP_tnt_disable,
PT_CAP_topa_output,
PT_CAP_topa_multiple_entries,
PT_CAP_single_range_output,
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index 79b392d893e3..efd34cfa1720 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -206,6 +206,7 @@
#define RTIT_CTL_PTW_EN BIT(12)
#define RTIT_CTL_BRANCH_EN BIT(13)
#define RTIT_CTL_EVENT_EN BIT(31)
+#define RTIT_CTL_NOTNT BIT_ULL(55)
#define RTIT_CTL_MTC_RANGE_OFFSET 14
#define RTIT_CTL_MTC_RANGE (0x0full << RTIT_CTL_MTC_RANGE_OFFSET)
#define RTIT_CTL_CYC_THRESH_OFFSET 19
--
2.25.1
^ permalink raw reply related [flat|nested] 11+ messages in thread* [tip: perf/core] perf/x86/intel/pt: Add a capability and config bit for disabling TNTs
2022-01-26 10:48 ` [PATCH V2 2/2] perf/x86/intel/pt: Add a capability and config bit for disabling TNTs Adrian Hunter
@ 2022-02-16 14:57 ` tip-bot2 for Alexander Shishkin
0 siblings, 0 replies; 11+ messages in thread
From: tip-bot2 for Alexander Shishkin @ 2022-02-16 14:57 UTC (permalink / raw)
To: linux-tip-commits
Cc: Alexander Shishkin, Adrian Hunter, Peter Zijlstra (Intel),
x86, linux-kernel
The following commit has been merged into the perf/core branch of tip:
Commit-ID: 161a9a33702a2e65a4118dacb449505ac8ce3122
Gitweb: https://git.kernel.org/tip/161a9a33702a2e65a4118dacb449505ac8ce3122
Author: Alexander Shishkin <alexander.shishkin@linux.intel.com>
AuthorDate: Wed, 26 Jan 2022 12:48:15 +02:00
Committer: Peter Zijlstra <peterz@infradead.org>
CommitterDate: Tue, 15 Feb 2022 17:47:11 +01:00
perf/x86/intel/pt: Add a capability and config bit for disabling TNTs
As of Intel SDM (https://www.intel.com/sdm) version 076, there is a new
Intel PT feature called TNT-Disable which is enabled config bit 55.
TNT-Disable disables Taken-Not-Taken packets to reduce the tracing
overhead, but with the result that exact control flow information is
lost.
Add a capability and config bit for TNT-Disable.
Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Signed-off-by: Adrian Hunter <adrian.hunter@intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Reviewed-by: Adrian Hunter <adrian.hunter@intel.com>
Link: https://lore.kernel.org/r/20220126104815.2807416-3-adrian.hunter@intel.com
---
arch/x86/events/intel/pt.c | 8 ++++++++
arch/x86/include/asm/intel_pt.h | 1 +
arch/x86/include/asm/msr-index.h | 1 +
3 files changed, 10 insertions(+)
diff --git a/arch/x86/events/intel/pt.c b/arch/x86/events/intel/pt.c
index f339c88..aa66c0c 100644
--- a/arch/x86/events/intel/pt.c
+++ b/arch/x86/events/intel/pt.c
@@ -60,6 +60,7 @@ static struct pt_cap_desc {
PT_CAP(ptwrite, 0, CPUID_EBX, BIT(4)),
PT_CAP(power_event_trace, 0, CPUID_EBX, BIT(5)),
PT_CAP(event_trace, 0, CPUID_EBX, BIT(7)),
+ PT_CAP(tnt_disable, 0, CPUID_EBX, BIT(8)),
PT_CAP(topa_output, 0, CPUID_ECX, BIT(0)),
PT_CAP(topa_multiple_entries, 0, CPUID_ECX, BIT(1)),
PT_CAP(single_range_output, 0, CPUID_ECX, BIT(2)),
@@ -112,6 +113,7 @@ PMU_FORMAT_ATTR(noretcomp, "config:11" );
PMU_FORMAT_ATTR(ptw, "config:12" );
PMU_FORMAT_ATTR(branch, "config:13" );
PMU_FORMAT_ATTR(event, "config:31" );
+PMU_FORMAT_ATTR(notnt, "config:55" );
PMU_FORMAT_ATTR(mtc_period, "config:14-17" );
PMU_FORMAT_ATTR(cyc_thresh, "config:19-22" );
PMU_FORMAT_ATTR(psb_period, "config:24-27" );
@@ -121,6 +123,7 @@ static struct attribute *pt_formats_attr[] = {
&format_attr_cyc.attr,
&format_attr_pwr_evt.attr,
&format_attr_event.attr,
+ &format_attr_notnt.attr,
&format_attr_fup_on_ptw.attr,
&format_attr_mtc.attr,
&format_attr_tsc.attr,
@@ -302,6 +305,7 @@ fail:
RTIT_CTL_MTC | \
RTIT_CTL_PWR_EVT_EN | \
RTIT_CTL_EVENT_EN | \
+ RTIT_CTL_NOTNT | \
RTIT_CTL_FUP_ON_PTW | \
RTIT_CTL_PTW_EN)
@@ -360,6 +364,10 @@ static bool pt_event_valid(struct perf_event *event)
!intel_pt_validate_hw_cap(PT_CAP_event_trace))
return false;
+ if (config & RTIT_CTL_NOTNT &&
+ !intel_pt_validate_hw_cap(PT_CAP_tnt_disable))
+ return false;
+
if (config & RTIT_CTL_PTW) {
if (!intel_pt_validate_hw_cap(PT_CAP_ptwrite))
return false;
diff --git a/arch/x86/include/asm/intel_pt.h b/arch/x86/include/asm/intel_pt.h
index d1ef9cb..c796e9b 100644
--- a/arch/x86/include/asm/intel_pt.h
+++ b/arch/x86/include/asm/intel_pt.h
@@ -14,6 +14,7 @@ enum pt_capabilities {
PT_CAP_ptwrite,
PT_CAP_power_event_trace,
PT_CAP_event_trace,
+ PT_CAP_tnt_disable,
PT_CAP_topa_output,
PT_CAP_topa_multiple_entries,
PT_CAP_single_range_output,
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index 79b392d..efd34cf 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -206,6 +206,7 @@
#define RTIT_CTL_PTW_EN BIT(12)
#define RTIT_CTL_BRANCH_EN BIT(13)
#define RTIT_CTL_EVENT_EN BIT(31)
+#define RTIT_CTL_NOTNT BIT_ULL(55)
#define RTIT_CTL_MTC_RANGE_OFFSET 14
#define RTIT_CTL_MTC_RANGE (0x0full << RTIT_CTL_MTC_RANGE_OFFSET)
#define RTIT_CTL_CYC_THRESH_OFFSET 19
^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [PATCH V2 0/2] perf/x86/intel/pt: Add support for event tracing and TNT disabling
2022-01-26 10:48 [PATCH V2 0/2] perf/x86/intel/pt: Add support for event tracing and TNT disabling Adrian Hunter
2022-01-26 10:48 ` [PATCH V2 1/2] perf/x86/intel/pt: Add a capability and config bit for event tracing Adrian Hunter
2022-01-26 10:48 ` [PATCH V2 2/2] perf/x86/intel/pt: Add a capability and config bit for disabling TNTs Adrian Hunter
@ 2022-02-08 6:28 ` Adrian Hunter
2022-02-15 14:18 ` Adrian Hunter
2022-02-15 15:35 ` Peter Zijlstra
2022-02-15 15:41 ` Peter Zijlstra
4 siblings, 1 reply; 11+ messages in thread
From: Adrian Hunter @ 2022-02-08 6:28 UTC (permalink / raw)
To: Peter Zijlstra
Cc: Alexander Shishkin, Andi Kleen, Arnaldo Carvalho de Melo,
Jiri Olsa, linux-kernel, Ingo Molnar, Borislav Petkov,
Dave Hansen, x86, H Peter Anvin
On 26/01/2022 12:48, Adrian Hunter wrote:
> Hi
>
> As of Intel SDM (https://www.intel.com/sdm) version 076, there are 2 new
> Intel PT features called Event Trace and TNT-Disable.
>
> Event Trace exposes details about asynchronous events such as interrupts
> and VM-Entry/Exit.
>
> TNT-Disable disables TNT packets to reduce the tracing overhead, but with
> the result that exact control flow information is lost.
>
> Tools patches are being sent in a separate patch set, but can be found
> here:
>
> https://github.com/ahunter6/linux/tree/event-trace
>
>
> Changes in V2:
>
> Add my SOB
Ping
>
>
> Alexander Shishkin (2):
> perf/x86/intel/pt: Add a capability and config bit for event tracing
> perf/x86/intel/pt: Add a capability and config bit for disabling TNTs
>
> arch/x86/events/intel/pt.c | 16 ++++++++++++++++
> arch/x86/include/asm/intel_pt.h | 2 ++
> arch/x86/include/asm/msr-index.h | 2 ++
> 3 files changed, 20 insertions(+)
>
>
> Regards
> Adrian
>
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH V2 0/2] perf/x86/intel/pt: Add support for event tracing and TNT disabling
2022-02-08 6:28 ` [PATCH V2 0/2] perf/x86/intel/pt: Add support for event tracing and TNT disabling Adrian Hunter
@ 2022-02-15 14:18 ` Adrian Hunter
0 siblings, 0 replies; 11+ messages in thread
From: Adrian Hunter @ 2022-02-15 14:18 UTC (permalink / raw)
To: Peter Zijlstra
Cc: Alexander Shishkin, Andi Kleen, Arnaldo Carvalho de Melo,
Jiri Olsa, linux-kernel, Ingo Molnar, Borislav Petkov,
Dave Hansen, x86, H Peter Anvin
On 08/02/2022 08:28, Adrian Hunter wrote:
> On 26/01/2022 12:48, Adrian Hunter wrote:
>> Hi
>>
>> As of Intel SDM (https://www.intel.com/sdm) version 076, there are 2 new
>> Intel PT features called Event Trace and TNT-Disable.
>>
>> Event Trace exposes details about asynchronous events such as interrupts
>> and VM-Entry/Exit.
>>
>> TNT-Disable disables TNT packets to reduce the tracing overhead, but with
>> the result that exact control flow information is lost.
>>
>> Tools patches are being sent in a separate patch set, but can be found
>> here:
>>
>> https://github.com/ahunter6/linux/tree/event-trace
>>
>>
>> Changes in V2:
>>
>> Add my SOB
>
> Ping
Any comments on these patches?
>
>
>>
>>
>> Alexander Shishkin (2):
>> perf/x86/intel/pt: Add a capability and config bit for event tracing
>> perf/x86/intel/pt: Add a capability and config bit for disabling TNTs
>>
>> arch/x86/events/intel/pt.c | 16 ++++++++++++++++
>> arch/x86/include/asm/intel_pt.h | 2 ++
>> arch/x86/include/asm/msr-index.h | 2 ++
>> 3 files changed, 20 insertions(+)
>>
>>
>> Regards
>> Adrian
>>
>
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH V2 0/2] perf/x86/intel/pt: Add support for event tracing and TNT disabling
2022-01-26 10:48 [PATCH V2 0/2] perf/x86/intel/pt: Add support for event tracing and TNT disabling Adrian Hunter
` (2 preceding siblings ...)
2022-02-08 6:28 ` [PATCH V2 0/2] perf/x86/intel/pt: Add support for event tracing and TNT disabling Adrian Hunter
@ 2022-02-15 15:35 ` Peter Zijlstra
2022-02-15 15:40 ` Adrian Hunter
2022-02-15 15:41 ` Peter Zijlstra
4 siblings, 1 reply; 11+ messages in thread
From: Peter Zijlstra @ 2022-02-15 15:35 UTC (permalink / raw)
To: Adrian Hunter
Cc: Alexander Shishkin, Andi Kleen, Arnaldo Carvalho de Melo,
Jiri Olsa, linux-kernel, Ingo Molnar, Borislav Petkov,
Dave Hansen, x86, H Peter Anvin
On Wed, Jan 26, 2022 at 12:48:13PM +0200, Adrian Hunter wrote:
> Hi
>
> As of Intel SDM (https://www.intel.com/sdm) version 076, there are 2 new
> Intel PT features called Event Trace and TNT-Disable.
>
> Event Trace exposes details about asynchronous events such as interrupts
> and VM-Entry/Exit.
>
> TNT-Disable disables TNT packets to reduce the tracing overhead, but with
> the result that exact control flow information is lost.
What's a TNT?
^ permalink raw reply [flat|nested] 11+ messages in thread* Re: [PATCH V2 0/2] perf/x86/intel/pt: Add support for event tracing and TNT disabling
2022-02-15 15:35 ` Peter Zijlstra
@ 2022-02-15 15:40 ` Adrian Hunter
2022-02-15 15:51 ` Peter Zijlstra
0 siblings, 1 reply; 11+ messages in thread
From: Adrian Hunter @ 2022-02-15 15:40 UTC (permalink / raw)
To: Peter Zijlstra
Cc: Alexander Shishkin, Andi Kleen, Arnaldo Carvalho de Melo,
Jiri Olsa, linux-kernel, Ingo Molnar, Borislav Petkov,
Dave Hansen, x86, H Peter Anvin
On 15/02/2022 17:35, Peter Zijlstra wrote:
> On Wed, Jan 26, 2022 at 12:48:13PM +0200, Adrian Hunter wrote:
>> Hi
>>
>> As of Intel SDM (https://www.intel.com/sdm) version 076, there are 2 new
>> Intel PT features called Event Trace and TNT-Disable.
>>
>> Event Trace exposes details about asynchronous events such as interrupts
>> and VM-Entry/Exit.
>>
>> TNT-Disable disables TNT packets to reduce the tracing overhead, but with
>> the result that exact control flow information is lost.
>
> What's a TNT?
The TNT packet indicates whether conditional branches were taken
or not taken.
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH V2 0/2] perf/x86/intel/pt: Add support for event tracing and TNT disabling
2022-02-15 15:40 ` Adrian Hunter
@ 2022-02-15 15:51 ` Peter Zijlstra
0 siblings, 0 replies; 11+ messages in thread
From: Peter Zijlstra @ 2022-02-15 15:51 UTC (permalink / raw)
To: Adrian Hunter
Cc: Alexander Shishkin, Andi Kleen, Arnaldo Carvalho de Melo,
Jiri Olsa, linux-kernel, Ingo Molnar, Borislav Petkov,
Dave Hansen, x86, H Peter Anvin
On Tue, Feb 15, 2022 at 05:40:45PM +0200, Adrian Hunter wrote:
> On 15/02/2022 17:35, Peter Zijlstra wrote:
> > On Wed, Jan 26, 2022 at 12:48:13PM +0200, Adrian Hunter wrote:
> >> Hi
> >>
> >> As of Intel SDM (https://www.intel.com/sdm) version 076, there are 2 new
> >> Intel PT features called Event Trace and TNT-Disable.
> >>
> >> Event Trace exposes details about asynchronous events such as interrupts
> >> and VM-Entry/Exit.
> >>
> >> TNT-Disable disables TNT packets to reduce the tracing overhead, but with
> >> the result that exact control flow information is lost.
> >
> > What's a TNT?
>
> The TNT packet indicates whether conditional branches were taken
> or not taken.
Thanks, updated that Changelog.
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH V2 0/2] perf/x86/intel/pt: Add support for event tracing and TNT disabling
2022-01-26 10:48 [PATCH V2 0/2] perf/x86/intel/pt: Add support for event tracing and TNT disabling Adrian Hunter
` (3 preceding siblings ...)
2022-02-15 15:35 ` Peter Zijlstra
@ 2022-02-15 15:41 ` Peter Zijlstra
4 siblings, 0 replies; 11+ messages in thread
From: Peter Zijlstra @ 2022-02-15 15:41 UTC (permalink / raw)
To: Adrian Hunter
Cc: Alexander Shishkin, Andi Kleen, Arnaldo Carvalho de Melo,
Jiri Olsa, linux-kernel, Ingo Molnar, Borislav Petkov,
Dave Hansen, x86, H Peter Anvin
On Wed, Jan 26, 2022 at 12:48:13PM +0200, Adrian Hunter wrote:
> Alexander Shishkin (2):
> perf/x86/intel/pt: Add a capability and config bit for event tracing
> perf/x86/intel/pt: Add a capability and config bit for disabling TNTs
>
> arch/x86/events/intel/pt.c | 16 ++++++++++++++++
> arch/x86/include/asm/intel_pt.h | 2 ++
> arch/x86/include/asm/msr-index.h | 2 ++
> 3 files changed, 20 insertions(+)
patches look Ok otherwise, I'll queue then in perf/core
^ permalink raw reply [flat|nested] 11+ messages in thread