From: Rohit Agarwal <quic_rohiagar@quicinc.com>
To: will@kernel.org, robin.murphy@arm.com, joro@8bytes.org,
robh+dt@kernel.org, krzk+dt@kernel.org, ulf.hansson@linaro.org,
agross@kernel.org, bjorn.andersson@linaro.org
Cc: linux-arm-kernel@lists.infradead.org,
iommu@lists.linux-foundation.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org,
linux-arm-msm@vger.kernel.org,
Rohit Agarwal <quic_rohiagar@quicinc.com>
Subject: [PATCH 5/7] ARM: dts: qcom: sdx65: Enable ARM SMMU
Date: Mon, 11 Apr 2022 12:25:41 +0530 [thread overview]
Message-ID: <1649660143-22400-6-git-send-email-quic_rohiagar@quicinc.com> (raw)
In-Reply-To: <1649660143-22400-1-git-send-email-quic_rohiagar@quicinc.com>
Add a node for the ARM SMMU found in the SDX65.
Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
---
arch/arm/boot/dts/qcom-sdx65.dtsi | 40 +++++++++++++++++++++++++++++++++++++++
1 file changed, 40 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi
index 632ac78..2481769 100644
--- a/arch/arm/boot/dts/qcom-sdx65.dtsi
+++ b/arch/arm/boot/dts/qcom-sdx65.dtsi
@@ -181,6 +181,46 @@
status = "disabled";
};
+ apps_smmu: iommu@15000000 {
+ compatible = "qcom,sdx65-smmu-500", "arm,mmu-500";
+ reg = <0x15000000 0x40000>;
+ #iommu-cells = <2>;
+ #global-interrupts = <1>;
+ interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
pdc: interrupt-controller@b210000 {
compatible = "qcom,sdx65-pdc", "qcom,pdc";
reg = <0xb210000 0x10000>;
--
2.7.4
next prev parent reply other threads:[~2022-04-11 6:56 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-04-11 6:55 [PATCH 0/7] SDX65 devicetree updates Rohit Agarwal
2022-04-11 6:55 ` [PATCH 1/7] ARM: dts: qcom: sdx65: Add reserved memory nodes Rohit Agarwal
2022-04-11 7:30 ` Manivannan Sadhasivam
2022-04-11 6:55 ` [PATCH 2/7] dt-bindings: mmc: sdhci-msm: Document the SDX65 compatible Rohit Agarwal
2022-04-11 6:55 ` [PATCH 3/7] ARM: dts: qcom: sdx65: Add support for SDHCI controller Rohit Agarwal
2022-04-11 7:31 ` Manivannan Sadhasivam
2022-04-11 6:55 ` [PATCH 4/7] dt-bindings: arm-smmu: Add binding for SDX65 SMMU Rohit Agarwal
2022-04-11 6:55 ` Rohit Agarwal [this message]
2022-04-11 7:32 ` [PATCH 5/7] ARM: dts: qcom: sdx65: Enable ARM SMMU Manivannan Sadhasivam
2022-04-11 6:55 ` [PATCH 6/7] ARM: dts: qcom: sdx65: Add support for TCSR Mutex Rohit Agarwal
2022-04-11 7:33 ` Manivannan Sadhasivam
2022-04-11 6:55 ` [PATCH 7/7] ARM: dts: qcom: sdx65: Add Shared memory manager support Rohit Agarwal
2022-04-11 7:27 ` [PATCH 0/7] SDX65 devicetree updates Manivannan Sadhasivam
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