* [PATCH 0/3] Add 128-bit support mailbox for Tegra234 chips
@ 2022-04-14 7:35 Kartik
2022-04-14 7:35 ` [PATCH 1/3] mailbox: tegra-hsp: Add tegra_hsp_sm_ops Kartik
` (3 more replies)
0 siblings, 4 replies; 9+ messages in thread
From: Kartik @ 2022-04-14 7:35 UTC (permalink / raw)
To: jassisinghbrar, robh+dt, krzk+dt, thierry.reding, jonathanh,
linux-kernel, devicetree, linux-tegra, kkartik
This series of patches adds support for 128-bit shared mailbox found
on Tegra234 chips. It also introduce tegra_hsp_sm_ops to abstract
send & receive APIs for 32-bit and 128-bit shared mailboxes.
Kartik (3):
mailbox: tegra-hsp: Add tegra_hsp_sm_ops
dt-bindings: tegra186-hsp: add type for shared mailboxes
mailbox: tegra-hsp: Add 128-bit shared mailbox support
.../bindings/mailbox/nvidia,tegra186-hsp.yaml | 9 ++
drivers/mailbox/tegra-hsp.c | 149 ++++++++++++++----
include/dt-bindings/mailbox/tegra186-hsp.h | 5 +
3 files changed, 134 insertions(+), 29 deletions(-)
--
2.17.1
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH 1/3] mailbox: tegra-hsp: Add tegra_hsp_sm_ops
2022-04-14 7:35 [PATCH 0/3] Add 128-bit support mailbox for Tegra234 chips Kartik
@ 2022-04-14 7:35 ` Kartik
2022-04-14 7:35 ` [PATCH 2/3] dt-bindings: tegra186-hsp: add type for shared mailboxes Kartik
` (2 subsequent siblings)
3 siblings, 0 replies; 9+ messages in thread
From: Kartik @ 2022-04-14 7:35 UTC (permalink / raw)
To: jassisinghbrar, robh+dt, krzk+dt, thierry.reding, jonathanh,
linux-kernel, devicetree, linux-tegra, kkartik
This patch introduces tegra_hsp_sm_ops to abstract send & receive
API's for shared mailboxes.
Signed-off-by: Kartik <kkartik@nvidia.com>
---
drivers/mailbox/tegra-hsp.c | 74 +++++++++++++++++++++++--------------
1 file changed, 47 insertions(+), 27 deletions(-)
diff --git a/drivers/mailbox/tegra-hsp.c b/drivers/mailbox/tegra-hsp.c
index 78f7265039c6..af61ae43ab09 100644
--- a/drivers/mailbox/tegra-hsp.c
+++ b/drivers/mailbox/tegra-hsp.c
@@ -67,8 +67,14 @@ struct tegra_hsp_doorbell {
unsigned int index;
};
+struct tegra_hsp_sm_ops {
+ void (*send)(struct tegra_hsp_channel *channel, void *data);
+ void (*recv)(struct tegra_hsp_channel *channel);
+};
+
struct tegra_hsp_mailbox {
struct tegra_hsp_channel channel;
+ const struct tegra_hsp_sm_ops *ops;
unsigned int index;
bool producer;
};
@@ -208,8 +214,7 @@ static irqreturn_t tegra_hsp_shared_irq(int irq, void *data)
{
struct tegra_hsp *hsp = data;
unsigned long bit, mask;
- u32 status, value;
- void *msg;
+ u32 status;
status = tegra_hsp_readl(hsp, HSP_INT_IR) & hsp->mask;
@@ -245,25 +250,8 @@ static irqreturn_t tegra_hsp_shared_irq(int irq, void *data)
for_each_set_bit(bit, &mask, hsp->num_sm) {
struct tegra_hsp_mailbox *mb = &hsp->mailboxes[bit];
- if (!mb->producer) {
- value = tegra_hsp_channel_readl(&mb->channel,
- HSP_SM_SHRD_MBOX);
- value &= ~HSP_SM_SHRD_MBOX_FULL;
- msg = (void *)(unsigned long)value;
- mbox_chan_received_data(mb->channel.chan, msg);
-
- /*
- * Need to clear all bits here since some producers,
- * such as TCU, depend on fields in the register
- * getting cleared by the consumer.
- *
- * The mailbox API doesn't give the consumers a way
- * of doing that explicitly, so we have to make sure
- * we cover all possible cases.
- */
- tegra_hsp_channel_writel(&mb->channel, 0x0,
- HSP_SM_SHRD_MBOX);
- }
+ if (!mb->producer)
+ mb->ops->recv(&mb->channel);
}
return IRQ_HANDLED;
@@ -372,21 +360,52 @@ static const struct mbox_chan_ops tegra_hsp_db_ops = {
.shutdown = tegra_hsp_doorbell_shutdown,
};
+static void tegra_hsp_sm_send32(struct tegra_hsp_channel *channel, void *data)
+{
+ u32 value;
+
+ /* copy data and mark mailbox full */
+ value = (u32)(unsigned long)data;
+ value |= HSP_SM_SHRD_MBOX_FULL;
+
+ tegra_hsp_channel_writel(channel, value, HSP_SM_SHRD_MBOX);
+}
+
+static void tegra_hsp_sm_recv32(struct tegra_hsp_channel *channel)
+{
+ u32 value;
+ void *msg;
+
+ value = tegra_hsp_channel_readl(channel, HSP_SM_SHRD_MBOX);
+ value &= ~HSP_SM_SHRD_MBOX_FULL;
+ msg = (void *)(unsigned long)value;
+ mbox_chan_received_data(channel->chan, msg);
+
+ /*
+ * Need to clear all bits here since some producers, such as TCU, depend
+ * on fields in the register getting cleared by the consumer.
+ *
+ * The mailbox API doesn't give the consumers a way of doing that
+ * explicitly, so we have to make sure we cover all possible cases.
+ */
+ tegra_hsp_channel_writel(channel, 0x0, HSP_SM_SHRD_MBOX);
+}
+
+static const struct tegra_hsp_sm_ops tegra_hsp_sm_32bit_ops = {
+ .send = tegra_hsp_sm_send32,
+ .recv = tegra_hsp_sm_recv32,
+};
+
static int tegra_hsp_mailbox_send_data(struct mbox_chan *chan, void *data)
{
struct tegra_hsp_mailbox *mb = chan->con_priv;
struct tegra_hsp *hsp = mb->channel.hsp;
unsigned long flags;
- u32 value;
if (WARN_ON(!mb->producer))
return -EPERM;
- /* copy data and mark mailbox full */
- value = (u32)(unsigned long)data;
- value |= HSP_SM_SHRD_MBOX_FULL;
-
- tegra_hsp_channel_writel(&mb->channel, value, HSP_SM_SHRD_MBOX);
+ mb->ops->send(&mb->channel, data);
/* enable EMPTY interrupt for the shared mailbox */
spin_lock_irqsave(&hsp->lock, flags);
@@ -557,6 +576,7 @@ static struct mbox_chan *tegra_hsp_sm_xlate(struct mbox_controller *mbox,
return ERR_PTR(-ENODEV);
mb = &hsp->mailboxes[index];
+ mb->ops = &tegra_hsp_sm_32bit_ops;
if ((args->args[1] & TEGRA_HSP_SM_FLAG_TX) == 0)
mb->producer = false;
--
2.17.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 2/3] dt-bindings: tegra186-hsp: add type for shared mailboxes
2022-04-14 7:35 [PATCH 0/3] Add 128-bit support mailbox for Tegra234 chips Kartik
2022-04-14 7:35 ` [PATCH 1/3] mailbox: tegra-hsp: Add tegra_hsp_sm_ops Kartik
@ 2022-04-14 7:35 ` Kartik
2022-04-14 13:53 ` Rob Herring
2022-04-20 19:55 ` Rob Herring
2022-04-14 7:35 ` [PATCH 3/3] mailbox: tegra-hsp: Add 128-bit shared mailbox support Kartik
2022-06-29 18:56 ` [PATCH 0/3] Add 128-bit support mailbox for Tegra234 chips Kartik
3 siblings, 2 replies; 9+ messages in thread
From: Kartik @ 2022-04-14 7:35 UTC (permalink / raw)
To: jassisinghbrar, robh+dt, krzk+dt, thierry.reding, jonathanh,
linux-kernel, devicetree, linux-tegra, kkartik
Tegra234 supports sending/receiving 32-bit and 128-bit data over
a shared mailbox. Based on the data size to be used, clients need
to specify the type of shared mailbox in the device tree.
Add a macro for 128-bit shared mailbox. Mailbox clients can use this
macro as a flag in device tree to enable 128-bit data support for a
shared mailbox.
Signed-off-by: Kartik <kkartik@nvidia.com>
---
.../devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml | 9 +++++++++
include/dt-bindings/mailbox/tegra186-hsp.h | 5 +++++
2 files changed, 14 insertions(+)
diff --git a/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml b/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml
index 9f7a7296b57f..a3e87516d637 100644
--- a/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml
+++ b/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml
@@ -26,6 +26,15 @@ description: |
second cell is used to identify the mailbox that the client is going
to use.
+ For shared mailboxes, the first cell composed of two fields:
+ - bits 15..8:
+ A bit mask of flags that further specifies the type of shared
+ mailbox to be used (based on the data size). If no flag is
+ specified then, 32-bit shared mailbox is used.
+ - bits 7..0:
+ Defines the type of the mailbox to be used. This field should be
+ TEGRA_HSP_MBOX_TYPE_SM for shared mailboxes.
+
For doorbells, the second cell specifies the index of the doorbell to
use.
diff --git a/include/dt-bindings/mailbox/tegra186-hsp.h b/include/dt-bindings/mailbox/tegra186-hsp.h
index 3bdec7a84d35..b9ccae2aa9e2 100644
--- a/include/dt-bindings/mailbox/tegra186-hsp.h
+++ b/include/dt-bindings/mailbox/tegra186-hsp.h
@@ -15,6 +15,11 @@
#define TEGRA_HSP_MBOX_TYPE_SS 0x2
#define TEGRA_HSP_MBOX_TYPE_AS 0x3
+/*
+ * These define the types of shared mailbox supported based on data size.
+ */
+#define TEGRA_HSP_MBOX_TYPE_SM_128BIT (1 << 8)
+
/*
* These defines represent the bit associated with the given master ID in the
* doorbell registers.
--
2.17.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 3/3] mailbox: tegra-hsp: Add 128-bit shared mailbox support
2022-04-14 7:35 [PATCH 0/3] Add 128-bit support mailbox for Tegra234 chips Kartik
2022-04-14 7:35 ` [PATCH 1/3] mailbox: tegra-hsp: Add tegra_hsp_sm_ops Kartik
2022-04-14 7:35 ` [PATCH 2/3] dt-bindings: tegra186-hsp: add type for shared mailboxes Kartik
@ 2022-04-14 7:35 ` Kartik
2022-06-29 18:56 ` [PATCH 0/3] Add 128-bit support mailbox for Tegra234 chips Kartik
3 siblings, 0 replies; 9+ messages in thread
From: Kartik @ 2022-04-14 7:35 UTC (permalink / raw)
To: jassisinghbrar, robh+dt, krzk+dt, thierry.reding, jonathanh,
linux-kernel, devicetree, linux-tegra, kkartik
Add support for 128-bit shared mailboxes found on Tegra234 chips.
Signed-off-by: Kartik <kkartik@nvidia.com>
---
drivers/mailbox/tegra-hsp.c | 77 +++++++++++++++++++++++++++++++++++--
1 file changed, 74 insertions(+), 3 deletions(-)
diff --git a/drivers/mailbox/tegra-hsp.c b/drivers/mailbox/tegra-hsp.c
index af61ae43ab09..f58448b10d90 100644
--- a/drivers/mailbox/tegra-hsp.c
+++ b/drivers/mailbox/tegra-hsp.c
@@ -46,10 +46,18 @@
#define HSP_SM_SHRD_MBOX_FULL_INT_IE 0x04
#define HSP_SM_SHRD_MBOX_EMPTY_INT_IE 0x08
+#define HSP_SHRD_MBOX_TYPE1_TAG 0x40
+#define HSP_SHRD_MBOX_TYPE1_DATA0 0x48
+#define HSP_SHRD_MBOX_TYPE1_DATA1 0x4c
+#define HSP_SHRD_MBOX_TYPE1_DATA2 0x50
+#define HSP_SHRD_MBOX_TYPE1_DATA3 0x54
+
#define HSP_DB_CCPLEX 1
#define HSP_DB_BPMP 3
#define HSP_DB_MAX 7
+#define HSP_MBOX_TYPE_MASK 0xff
+
struct tegra_hsp_channel;
struct tegra_hsp;
@@ -88,6 +96,7 @@ struct tegra_hsp_db_map {
struct tegra_hsp_soc {
const struct tegra_hsp_db_map *map;
bool has_per_mb_ie;
+ bool has_128_bit_mb;
};
struct tegra_hsp {
@@ -396,6 +405,51 @@ static const struct tegra_hsp_sm_ops tegra_hsp_sm_32bit_ops = {
.recv = tegra_hsp_sm_recv32,
};
+static void tegra_hsp_sm_send128(struct tegra_hsp_channel *channel, void *data)
+{
+ u32 value[4];
+
+ memcpy(value, data, sizeof(value));
+
+ /* Copy data */
+ tegra_hsp_channel_writel(channel, value[0], HSP_SHRD_MBOX_TYPE1_DATA0);
+ tegra_hsp_channel_writel(channel, value[1], HSP_SHRD_MBOX_TYPE1_DATA1);
+ tegra_hsp_channel_writel(channel, value[2], HSP_SHRD_MBOX_TYPE1_DATA2);
+ tegra_hsp_channel_writel(channel, value[3], HSP_SHRD_MBOX_TYPE1_DATA3);
+
+ /* Update tag to mark mailbox full */
+ tegra_hsp_channel_writel(channel, HSP_SM_SHRD_MBOX_FULL,
+ HSP_SHRD_MBOX_TYPE1_TAG);
+}
+
+static void tegra_hsp_sm_recv128(struct tegra_hsp_channel *channel)
+{
+ u32 value[4];
+ void *msg;
+
+ value[0] = tegra_hsp_channel_readl(channel, HSP_SHRD_MBOX_TYPE1_DATA0);
+ value[1] = tegra_hsp_channel_readl(channel, HSP_SHRD_MBOX_TYPE1_DATA1);
+ value[2] = tegra_hsp_channel_readl(channel, HSP_SHRD_MBOX_TYPE1_DATA2);
+ value[3] = tegra_hsp_channel_readl(channel, HSP_SHRD_MBOX_TYPE1_DATA3);
+
+ msg = (void *)(unsigned long)value;
+ mbox_chan_received_data(channel->chan, msg);
+
+ /*
+ * Clear data registers and tag.
+ */
+ tegra_hsp_channel_writel(channel, 0x0, HSP_SHRD_MBOX_TYPE1_DATA0);
+ tegra_hsp_channel_writel(channel, 0x0, HSP_SHRD_MBOX_TYPE1_DATA1);
+ tegra_hsp_channel_writel(channel, 0x0, HSP_SHRD_MBOX_TYPE1_DATA2);
+ tegra_hsp_channel_writel(channel, 0x0, HSP_SHRD_MBOX_TYPE1_DATA3);
+ tegra_hsp_channel_writel(channel, 0x0, HSP_SHRD_MBOX_TYPE1_TAG);
+}
+
+static const struct tegra_hsp_sm_ops tegra_hsp_sm_128bit_ops = {
+ .send = tegra_hsp_sm_send128,
+ .recv = tegra_hsp_sm_recv128,
+};
+
static int tegra_hsp_mailbox_send_data(struct mbox_chan *chan, void *data)
{
struct tegra_hsp_mailbox *mb = chan->con_priv;
@@ -571,12 +625,20 @@ static struct mbox_chan *tegra_hsp_sm_xlate(struct mbox_controller *mbox,
index = args->args[1] & TEGRA_HSP_SM_MASK;
- if (type != TEGRA_HSP_MBOX_TYPE_SM || !hsp->shared_irqs ||
- index >= hsp->num_sm)
+ if ((type & HSP_MBOX_TYPE_MASK) != TEGRA_HSP_MBOX_TYPE_SM ||
+ !hsp->shared_irqs || index >= hsp->num_sm)
return ERR_PTR(-ENODEV);
mb = &hsp->mailboxes[index];
- mb->ops = &tegra_hsp_sm_32bit_ops;
+
+ if (type & TEGRA_HSP_MBOX_TYPE_SM_128BIT) {
+ if (!hsp->soc->has_128_bit_mb)
+ return ERR_PTR(-ENODEV);
+
+ mb->ops = &tegra_hsp_sm_128bit_ops;
+ } else {
+ mb->ops = &tegra_hsp_sm_32bit_ops;
+ }
if ((args->args[1] & TEGRA_HSP_SM_FLAG_TX) == 0)
mb->producer = false;
@@ -853,16 +915,25 @@ static const struct tegra_hsp_db_map tegra186_hsp_db_map[] = {
static const struct tegra_hsp_soc tegra186_hsp_soc = {
.map = tegra186_hsp_db_map,
.has_per_mb_ie = false,
+ .has_128_bit_mb = false,
};
static const struct tegra_hsp_soc tegra194_hsp_soc = {
.map = tegra186_hsp_db_map,
.has_per_mb_ie = true,
+ .has_128_bit_mb = false,
+};
+
+static const struct tegra_hsp_soc tegra234_hsp_soc = {
+ .map = tegra186_hsp_db_map,
+ .has_per_mb_ie = false,
+ .has_128_bit_mb = true,
};
static const struct of_device_id tegra_hsp_match[] = {
{ .compatible = "nvidia,tegra186-hsp", .data = &tegra186_hsp_soc },
{ .compatible = "nvidia,tegra194-hsp", .data = &tegra194_hsp_soc },
+ { .compatible = "nvidia,tegra234-hsp", .data = &tegra234_hsp_soc },
{ }
};
--
2.17.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH 2/3] dt-bindings: tegra186-hsp: add type for shared mailboxes
2022-04-14 7:35 ` [PATCH 2/3] dt-bindings: tegra186-hsp: add type for shared mailboxes Kartik
@ 2022-04-14 13:53 ` Rob Herring
2022-04-18 11:01 ` Kartik
2022-04-20 19:55 ` Rob Herring
1 sibling, 1 reply; 9+ messages in thread
From: Rob Herring @ 2022-04-14 13:53 UTC (permalink / raw)
To: Kartik
Cc: jassisinghbrar, krzk+dt, thierry.reding, jonathanh, linux-kernel,
devicetree, linux-tegra
On Thu, Apr 14, 2022 at 01:05:56PM +0530, Kartik wrote:
> Tegra234 supports sending/receiving 32-bit and 128-bit data over
> a shared mailbox. Based on the data size to be used, clients need
> to specify the type of shared mailbox in the device tree.
>
> Add a macro for 128-bit shared mailbox. Mailbox clients can use this
> macro as a flag in device tree to enable 128-bit data support for a
> shared mailbox.
>
> Signed-off-by: Kartik <kkartik@nvidia.com>
Need a full name here.
> ---
> .../devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml | 9 +++++++++
> include/dt-bindings/mailbox/tegra186-hsp.h | 5 +++++
> 2 files changed, 14 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml b/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml
> index 9f7a7296b57f..a3e87516d637 100644
> --- a/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml
> +++ b/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml
> @@ -26,6 +26,15 @@ description: |
> second cell is used to identify the mailbox that the client is going
> to use.
>
> + For shared mailboxes, the first cell composed of two fields:
> + - bits 15..8:
> + A bit mask of flags that further specifies the type of shared
> + mailbox to be used (based on the data size). If no flag is
> + specified then, 32-bit shared mailbox is used.
> + - bits 7..0:
> + Defines the type of the mailbox to be used. This field should be
> + TEGRA_HSP_MBOX_TYPE_SM for shared mailboxes.
> +
> For doorbells, the second cell specifies the index of the doorbell to
> use.
>
> diff --git a/include/dt-bindings/mailbox/tegra186-hsp.h b/include/dt-bindings/mailbox/tegra186-hsp.h
> index 3bdec7a84d35..b9ccae2aa9e2 100644
> --- a/include/dt-bindings/mailbox/tegra186-hsp.h
> +++ b/include/dt-bindings/mailbox/tegra186-hsp.h
> @@ -15,6 +15,11 @@
> #define TEGRA_HSP_MBOX_TYPE_SS 0x2
> #define TEGRA_HSP_MBOX_TYPE_AS 0x3
>
> +/*
> + * These define the types of shared mailbox supported based on data size.
> + */
> +#define TEGRA_HSP_MBOX_TYPE_SM_128BIT (1 << 8)
> +
> /*
> * These defines represent the bit associated with the given master ID in the
> * doorbell registers.
> --
> 2.17.1
>
>
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 2/3] dt-bindings: tegra186-hsp: add type for shared mailboxes
2022-04-14 13:53 ` Rob Herring
@ 2022-04-18 11:01 ` Kartik
0 siblings, 0 replies; 9+ messages in thread
From: Kartik @ 2022-04-18 11:01 UTC (permalink / raw)
To: robh
Cc: devicetree, jassisinghbrar, jonathanh, kkartik, krzk+dt,
linux-kernel, linux-tegra, thierry.reding
On 14/04/2022 13:53, Rob Herring wrote:
>> Tegra234 supports sending/receiving 32-bit and 128-bit data over
>> a shared mailbox. Based on the data size to be used, clients need
>> to specify the type of shared mailbox in the device tree.
>>
>> Add a macro for 128-bit shared mailbox. Mailbox clients can use this
>> macro as a flag in device tree to enable 128-bit data support for a
>> shared mailbox.
>>
>> Signed-off-by: Kartik <kkartik@nvidia.com>
>
>Need a full name here.
This is my legal name as per the government ID's.
>
>> ---
>> .../devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml | 9 +++++++++
>> include/dt-bindings/mailbox/tegra186-hsp.h | 5 +++++
>> 2 files changed, 14 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml b/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml
>> index 9f7a7296b57f..a3e87516d637 100644
>> --- a/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml
>> +++ b/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml
>> @@ -26,6 +26,15 @@ description: |
>> second cell is used to identify the mailbox that the client is going
>> to use.
>>
>> + For shared mailboxes, the first cell composed of two fields:
>> + - bits 15..8:
>> + A bit mask of flags that further specifies the type of shared
>> + mailbox to be used (based on the data size). If no flag is
>> + specified then, 32-bit shared mailbox is used.
>> + - bits 7..0:
>> + Defines the type of the mailbox to be used. This field should be
>> + TEGRA_HSP_MBOX_TYPE_SM for shared mailboxes.
>> +
>> For doorbells, the second cell specifies the index of the doorbell to
>> use.
>>
>> diff --git a/include/dt-bindings/mailbox/tegra186-hsp.h b/include/dt-bindings/mailbox/tegra186-hsp.h
>> index 3bdec7a84d35..b9ccae2aa9e2 100644
>> --- a/include/dt-bindings/mailbox/tegra186-hsp.h
>> +++ b/include/dt-bindings/mailbox/tegra186-hsp.h
>> @@ -15,6 +15,11 @@
>> #define TEGRA_HSP_MBOX_TYPE_SS 0x2
>> #define TEGRA_HSP_MBOX_TYPE_AS 0x3
>>
>> +/*
>> + * These define the types of shared mailbox supported based on data size.
>> + */
>> +#define TEGRA_HSP_MBOX_TYPE_SM_128BIT (1 << 8)
>> +
>> /*
>> * These defines represent the bit associated with the given master ID in the
>> * doorbell registers.
>> --
>> 2.17.1
>>
>>
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 2/3] dt-bindings: tegra186-hsp: add type for shared mailboxes
2022-04-14 7:35 ` [PATCH 2/3] dt-bindings: tegra186-hsp: add type for shared mailboxes Kartik
2022-04-14 13:53 ` Rob Herring
@ 2022-04-20 19:55 ` Rob Herring
1 sibling, 0 replies; 9+ messages in thread
From: Rob Herring @ 2022-04-20 19:55 UTC (permalink / raw)
To: Kartik
Cc: jassisinghbrar, krzk+dt, thierry.reding, jonathanh, linux-kernel,
devicetree, linux-tegra
On Thu, Apr 14, 2022 at 01:05:56PM +0530, Kartik wrote:
> Tegra234 supports sending/receiving 32-bit and 128-bit data over
> a shared mailbox. Based on the data size to be used, clients need
> to specify the type of shared mailbox in the device tree.
>
> Add a macro for 128-bit shared mailbox. Mailbox clients can use this
> macro as a flag in device tree to enable 128-bit data support for a
> shared mailbox.
>
> Signed-off-by: Kartik <kkartik@nvidia.com>
> ---
> .../devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml | 9 +++++++++
> include/dt-bindings/mailbox/tegra186-hsp.h | 5 +++++
> 2 files changed, 14 insertions(+)
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 0/3] Add 128-bit support mailbox for Tegra234 chips
2022-04-14 7:35 [PATCH 0/3] Add 128-bit support mailbox for Tegra234 chips Kartik
` (2 preceding siblings ...)
2022-04-14 7:35 ` [PATCH 3/3] mailbox: tegra-hsp: Add 128-bit shared mailbox support Kartik
@ 2022-06-29 18:56 ` Kartik
2022-06-30 9:06 ` Thierry Reding
3 siblings, 1 reply; 9+ messages in thread
From: Kartik @ 2022-06-29 18:56 UTC (permalink / raw)
To: jassisinghbrar
Cc: devicetree, jonathanh, krzk+dt, linux-kernel, linux-tegra,
robh+dt, thierry.reding, kkartik
On 14/04/2022 13:05 +530, Kartik Wrote:
> This series of patches adds support for 128-bit shared mailbox found
> on Tegra234 chips. It also introduce tegra_hsp_sm_ops to abstract
> send & receive APIs for 32-bit and 128-bit shared mailboxes.
>
> Kartik (3):
> mailbox: tegra-hsp: Add tegra_hsp_sm_ops
> dt-bindings: tegra186-hsp: add type for shared mailboxes
> mailbox: tegra-hsp: Add 128-bit shared mailbox support
>
> .../bindings/mailbox/nvidia,tegra186-hsp.yaml | 9 ++
> drivers/mailbox/tegra-hsp.c | 149 ++++++++++++++----
> include/dt-bindings/mailbox/tegra186-hsp.h | 5 +
> 3 files changed, 134 insertions(+), 29 deletions(-)
Hi Jassi,
Any comments on this from the mailbox side?
Regards,
Kartik
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 0/3] Add 128-bit support mailbox for Tegra234 chips
2022-06-29 18:56 ` [PATCH 0/3] Add 128-bit support mailbox for Tegra234 chips Kartik
@ 2022-06-30 9:06 ` Thierry Reding
0 siblings, 0 replies; 9+ messages in thread
From: Thierry Reding @ 2022-06-30 9:06 UTC (permalink / raw)
To: Kartik
Cc: jassisinghbrar, devicetree, jonathanh, krzk+dt, linux-kernel,
linux-tegra, robh+dt
[-- Attachment #1: Type: text/plain, Size: 937 bytes --]
On Thu, Jun 30, 2022 at 12:26:27AM +0530, Kartik wrote:
> On 14/04/2022 13:05 +530, Kartik Wrote:
> > This series of patches adds support for 128-bit shared mailbox found
> > on Tegra234 chips. It also introduce tegra_hsp_sm_ops to abstract
> > send & receive APIs for 32-bit and 128-bit shared mailboxes.
> >
> > Kartik (3):
> > mailbox: tegra-hsp: Add tegra_hsp_sm_ops
> > dt-bindings: tegra186-hsp: add type for shared mailboxes
> > mailbox: tegra-hsp: Add 128-bit shared mailbox support
> >
> > .../bindings/mailbox/nvidia,tegra186-hsp.yaml | 9 ++
> > drivers/mailbox/tegra-hsp.c | 149 ++++++++++++++----
> > include/dt-bindings/mailbox/tegra186-hsp.h | 5 +
> > 3 files changed, 134 insertions(+), 29 deletions(-)
>
> Hi Jassi,
>
> Any comments on this from the mailbox side?
I noticed that Jassi pulled this in for v5.19-rc1, so I think this is
all good now.
Thierry
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^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2022-06-30 9:06 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-04-14 7:35 [PATCH 0/3] Add 128-bit support mailbox for Tegra234 chips Kartik
2022-04-14 7:35 ` [PATCH 1/3] mailbox: tegra-hsp: Add tegra_hsp_sm_ops Kartik
2022-04-14 7:35 ` [PATCH 2/3] dt-bindings: tegra186-hsp: add type for shared mailboxes Kartik
2022-04-14 13:53 ` Rob Herring
2022-04-18 11:01 ` Kartik
2022-04-20 19:55 ` Rob Herring
2022-04-14 7:35 ` [PATCH 3/3] mailbox: tegra-hsp: Add 128-bit shared mailbox support Kartik
2022-06-29 18:56 ` [PATCH 0/3] Add 128-bit support mailbox for Tegra234 chips Kartik
2022-06-30 9:06 ` Thierry Reding
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