From: Richard Zhu <hongxing.zhu@nxp.com>
To: l.stach@pengutronix.de, bhelgaas@google.com, robh+dt@kernel.org,
lorenzo.pieralisi@arm.com, shawnguo@kernel.org, kishon@ti.com,
kw@linux.com, frank.li@nxp.com
Cc: hongxing.zhu@nxp.com, linux-pci@vger.kernel.org,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, kernel@pengutronix.de,
linux-imx@nxp.com
Subject: [PATCH v5 14/14] PCI: imx6: Add i.MX8MP PCIe EP support
Date: Mon, 16 Jan 2023 13:41:24 +0800 [thread overview]
Message-ID: <1673847684-31893-15-git-send-email-hongxing.zhu@nxp.com> (raw)
In-Reply-To: <1673847684-31893-1-git-send-email-hongxing.zhu@nxp.com>
Add the i.MX8MP PCIe EP support.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
---
drivers/pci/controller/dwc/pci-imx6.c | 19 ++++++++++++++++++-
1 file changed, 18 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
index eab332eb4c36..55a0405b921d 100644
--- a/drivers/pci/controller/dwc/pci-imx6.c
+++ b/drivers/pci/controller/dwc/pci-imx6.c
@@ -54,6 +54,7 @@ enum imx6_pcie_variants {
IMX8MP,
IMX8MQ_EP,
IMX8MM_EP,
+ IMX8MP_EP,
};
#define IMX6_PCIE_FLAG_IMX6_PHY BIT(0)
@@ -158,7 +159,8 @@ static unsigned int imx6_pcie_grp_offset(const struct imx6_pcie *imx6_pcie)
imx6_pcie->drvdata->variant != IMX8MQ_EP &&
imx6_pcie->drvdata->variant != IMX8MM &&
imx6_pcie->drvdata->variant != IMX8MM_EP &&
- imx6_pcie->drvdata->variant != IMX8MP);
+ imx6_pcie->drvdata->variant != IMX8MP &&
+ imx6_pcie->drvdata->variant != IMX8MP_EP);
return imx6_pcie->controller_id == 1 ? IOMUXC_GPR16 : IOMUXC_GPR14;
}
@@ -323,6 +325,7 @@ static void imx6_pcie_init_phy(struct imx6_pcie *imx6_pcie)
case IMX8MM:
case IMX8MM_EP:
case IMX8MP:
+ case IMX8MP_EP:
/*
* The PHY initialization had been done in the PHY
* driver, break here directly.
@@ -584,6 +587,7 @@ static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie)
case IMX8MQ:
case IMX8MQ_EP:
case IMX8MP:
+ case IMX8MP_EP:
ret = clk_prepare_enable(imx6_pcie->pcie_aux);
if (ret) {
dev_err(dev, "unable to enable pcie_aux clock\n");
@@ -631,6 +635,7 @@ static void imx6_pcie_disable_ref_clk(struct imx6_pcie *imx6_pcie)
case IMX8MQ:
case IMX8MQ_EP:
case IMX8MP:
+ case IMX8MP_EP:
clk_disable_unprepare(imx6_pcie->pcie_aux);
break;
default:
@@ -701,6 +706,7 @@ static void imx6_pcie_assert_core_reset(struct imx6_pcie *imx6_pcie)
case IMX8MM:
case IMX8MM_EP:
case IMX8MP:
+ case IMX8MP_EP:
reset_control_assert(imx6_pcie->apps_reset);
break;
case IMX6SX:
@@ -779,6 +785,7 @@ static int imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie)
case IMX8MM:
case IMX8MM_EP:
case IMX8MP:
+ case IMX8MP_EP:
break;
}
@@ -831,6 +838,7 @@ static void imx6_pcie_ltssm_enable(struct device *dev)
case IMX8MM:
case IMX8MM_EP:
case IMX8MP:
+ case IMX8MP_EP:
reset_control_deassert(imx6_pcie->apps_reset);
break;
}
@@ -853,6 +861,7 @@ static void imx6_pcie_ltssm_disable(struct device *dev)
case IMX8MM:
case IMX8MM_EP:
case IMX8MP:
+ case IMX8MP_EP:
reset_control_assert(imx6_pcie->apps_reset);
break;
}
@@ -1105,6 +1114,7 @@ static int imx6_add_pcie_ep(struct imx6_pcie *imx6_pcie,
switch (imx6_pcie->drvdata->variant) {
case IMX8MQ_EP:
case IMX8MM_EP:
+ case IMX8MP_EP:
pcie_dbi2_offset = SZ_1M;
break;
default:
@@ -1319,6 +1329,7 @@ static int imx6_pcie_probe(struct platform_device *pdev)
case IMX8MM:
case IMX8MM_EP:
case IMX8MP:
+ case IMX8MP_EP:
imx6_pcie->pcie_aux = devm_clk_get(dev, "pcie_aux");
if (IS_ERR(imx6_pcie->pcie_aux))
return dev_err_probe(dev, PTR_ERR(imx6_pcie->pcie_aux),
@@ -1488,6 +1499,11 @@ static const struct imx6_pcie_drvdata drvdata[] = {
.mode = DW_PCIE_EP_TYPE,
.gpr = "fsl,imx8mm-iomuxc-gpr",
},
+ [IMX8MP_EP] = {
+ .variant = IMX8MP_EP,
+ .mode = DW_PCIE_EP_TYPE,
+ .gpr = "fsl,imx8mp-iomuxc-gpr",
+ },
};
static const struct of_device_id imx6_pcie_of_match[] = {
@@ -1500,6 +1516,7 @@ static const struct of_device_id imx6_pcie_of_match[] = {
{ .compatible = "fsl,imx8mp-pcie", .data = &drvdata[IMX8MP], },
{ .compatible = "fsl,imx8mq-pcie-ep", .data = &drvdata[IMX8MQ_EP], },
{ .compatible = "fsl,imx8mm-pcie-ep", .data = &drvdata[IMX8MM_EP], },
+ { .compatible = "fsl,imx8mp-pcie-ep", .data = &drvdata[IMX8MP_EP], },
{},
};
--
2.25.1
next prev parent reply other threads:[~2023-01-16 6:07 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-01-16 5:41 [PATCH v5 0/14] Add i.MX PCIe EP mode support Richard Zhu
2023-01-16 5:41 ` [PATCH v5 01/14] dt-bindings: imx6q-pcie: Add i.MX8MM PCIe EP mode compatible string Richard Zhu
2023-01-16 5:41 ` [PATCH v5 02/14] dt-bindings: imx6q-pcie: Add i.MX8MQ " Richard Zhu
2023-01-16 5:41 ` [PATCH v5 03/14] dt-bindings: imx6q-pcie: Add i.MX8MP " Richard Zhu
2023-01-16 5:41 ` [PATCH v5 04/14] arm64: dts: Add i.MX8MM PCIe EP support Richard Zhu
2023-01-26 6:47 ` Shawn Guo
2023-01-26 8:37 ` Shawn Guo
2023-01-16 5:41 ` [PATCH v5 05/14] arm64: dts: Add i.MX8MM PCIe EP support on EVK board Richard Zhu
2023-01-16 5:41 ` [PATCH v5 06/14] arm64: dts: Add i.MX8MQ PCIe EP support Richard Zhu
2023-01-16 5:41 ` [PATCH v5 07/14] arm64: dts: Add i.MX8MQ PCIe EP support on EVK board Richard Zhu
2023-01-16 5:41 ` [PATCH v5 08/14] arm64: dts: Add i.MX8MP PCIe EP support Richard Zhu
2023-01-16 5:41 ` [PATCH v5 09/14] arm64: dts: Add i.MX8MP PCIe EP support on EVK board Richard Zhu
2023-01-16 5:41 ` [PATCH v5 10/14] misc: pci_endpoint_test: Add i.MX8 PCIe EP device support Richard Zhu
2023-01-16 5:41 ` [PATCH v5 11/14] PCI: imx6: Add i.MX PCIe EP mode support Richard Zhu
2023-01-16 5:41 ` [PATCH v5 12/14] PCI: imx6: Add i.MX8MQ PCIe EP support Richard Zhu
2023-01-16 5:41 ` [PATCH v5 13/14] PCI: imx6: Add i.MX8MM " Richard Zhu
2023-01-16 5:41 ` Richard Zhu [this message]
2023-01-16 9:45 ` (subset) [PATCH v5 0/14] Add i.MX PCIe EP mode support Lorenzo Pieralisi
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