From: "tip-bot2 for Kim Phillips" <tip-bot2@linutronix.de>
To: linux-tip-commits@vger.kernel.org
Cc: Kim Phillips <kim.phillips@amd.com>,
"Borislav Petkov (AMD)" <bp@alien8.de>,
Sean Christopherson <seanjc@google.com>,
x86@kernel.org, linux-kernel@vger.kernel.org
Subject: [tip: x86/cpu] x86/cpu, kvm: Move X86_FEATURE_LFENCE_RDTSC to its native leaf
Date: Thu, 26 Jan 2023 10:12:26 -0000 [thread overview]
Message-ID: <167472794699.4906.12879995558166444038.tip-bot2@tip-bot2> (raw)
In-Reply-To: <20230124163319.2277355-5-kim.phillips@amd.com>
The following commit has been merged into the x86/cpu branch of tip:
Commit-ID: 84168ae786f8a15a7eb0f79d34f20b8d261ce2f5
Gitweb: https://git.kernel.org/tip/84168ae786f8a15a7eb0f79d34f20b8d261ce2f5
Author: Kim Phillips <kim.phillips@amd.com>
AuthorDate: Tue, 24 Jan 2023 10:33:15 -06:00
Committer: Borislav Petkov (AMD) <bp@alien8.de>
CommitterDate: Wed, 25 Jan 2023 13:06:13 +01:00
x86/cpu, kvm: Move X86_FEATURE_LFENCE_RDTSC to its native leaf
The LFENCE always serializing feature bit was defined as scattered
LFENCE_RDTSC and its native leaf bit position open-coded for KVM. Add
it to its newly added CPUID leaf 0x80000021 EAX proper. With
LFENCE_RDTSC in its proper place, the kernel's set_cpu_cap() will
effectively synthesize the feature for KVM going forward.
Also, DE_CFG[1] doesn't need to be set on such CPUs anymore.
[ bp: Massage and merge diff from Sean. ]
Signed-off-by: Kim Phillips <kim.phillips@amd.com>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Acked-by: Sean Christopherson <seanjc@google.com>
Link: https://lore.kernel.org/r/20230124163319.2277355-5-kim.phillips@amd.com
---
arch/x86/include/asm/cpufeatures.h | 3 ++-
arch/x86/kernel/cpu/amd.c | 2 +-
arch/x86/kvm/cpuid.c | 16 +++++++++++++---
3 files changed, 16 insertions(+), 5 deletions(-)
diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
index 1b2d40a..901128e 100644
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -97,7 +97,7 @@
#define X86_FEATURE_SYSENTER32 ( 3*32+15) /* "" sysenter in IA32 userspace */
#define X86_FEATURE_REP_GOOD ( 3*32+16) /* REP microcode works well */
#define X86_FEATURE_AMD_LBR_V2 ( 3*32+17) /* AMD Last Branch Record Extension Version 2 */
-#define X86_FEATURE_LFENCE_RDTSC ( 3*32+18) /* "" LFENCE synchronizes RDTSC */
+/* FREE, was #define X86_FEATURE_LFENCE_RDTSC ( 3*32+18) "" LFENCE synchronizes RDTSC */
#define X86_FEATURE_ACC_POWER ( 3*32+19) /* AMD Accumulated Power Mechanism */
#define X86_FEATURE_NOPL ( 3*32+20) /* The NOPL (0F 1F) instructions */
#define X86_FEATURE_ALWAYS ( 3*32+21) /* "" Always-present feature */
@@ -429,6 +429,7 @@
/* AMD-defined Extended Feature 2 EAX, CPUID level 0x80000021 (EAX), word 20 */
#define X86_FEATURE_NO_NESTED_DATA_BP (20*32+ 0) /* "" No Nested Data Breakpoints */
+#define X86_FEATURE_LFENCE_RDTSC (20*32+ 2) /* "" LFENCE always serializing / synchronizes RDTSC */
/*
* BUG word(s)
diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index f769d6d..208c2ce 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -956,7 +956,7 @@ static void init_amd(struct cpuinfo_x86 *c)
init_amd_cacheinfo(c);
- if (cpu_has(c, X86_FEATURE_XMM2)) {
+ if (!cpu_has(c, X86_FEATURE_LFENCE_RDTSC) && cpu_has(c, X86_FEATURE_XMM2)) {
/*
* Use LFENCE for execution serialization. On families which
* don't have that MSR, LFENCE is already serializing.
diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c
index aa3a6dc..12455dc 100644
--- a/arch/x86/kvm/cpuid.c
+++ b/arch/x86/kvm/cpuid.c
@@ -742,12 +742,22 @@ void kvm_set_cpu_caps(void)
F(SME_COHERENT));
kvm_cpu_cap_mask(CPUID_8000_0021_EAX,
- F(NO_NESTED_DATA_BP) |
- BIT(2) /* LFENCE Always serializing */ | 0 /* SmmPgCfgLock */ |
+ F(NO_NESTED_DATA_BP) | F(LFENCE_RDTSC) | 0 /* SmmPgCfgLock */ |
BIT(6) /* NULL_SEL_CLR_BASE */ | 0 /* PrefetchCtlMsr */
);
+
+ /*
+ * Synthesize "LFENCE is serializing" into the AMD-defined entry in
+ * KVM's supported CPUID if the feature is reported as supported by the
+ * kernel. LFENCE_RDTSC was a Linux-defined synthetic feature long
+ * before AMD joined the bandwagon, e.g. LFENCE is serializing on most
+ * CPUs that support SSE2. On CPUs that don't support AMD's leaf,
+ * kvm_cpu_cap_mask() will unfortunately drop the flag due to ANDing
+ * the mask with the raw host CPUID, and reporting support in AMD's
+ * leaf can make it easier for userspace to detect the feature.
+ */
if (cpu_feature_enabled(X86_FEATURE_LFENCE_RDTSC))
- kvm_cpu_caps[CPUID_8000_0021_EAX] |= BIT(2) /* LFENCE Always serializing */;
+ kvm_cpu_cap_set(X86_FEATURE_LFENCE_RDTSC);
if (!static_cpu_has_bug(X86_BUG_NULL_SEG))
kvm_cpu_caps[CPUID_8000_0021_EAX] |= BIT(6) /* NULL_SEL_CLR_BASE */;
kvm_cpu_caps[CPUID_8000_0021_EAX] |= BIT(9) /* NO_SMM_CTL_MSR */;
next prev parent reply other threads:[~2023-01-26 10:12 UTC|newest]
Thread overview: 47+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-01-24 16:33 [PATCH v9 0/8] x86/cpu, kvm: Support AMD Automatic IBRS Kim Phillips
2023-01-24 16:33 ` [PATCH v9 1/8] x86/cpu, kvm: Add support for CPUID_80000021_EAX Kim Phillips
2023-01-26 10:12 ` [tip: x86/cpu] " tip-bot2 for Kim Phillips
2023-01-24 16:33 ` [PATCH v9 2/8] KVM: x86: Move open-coded cpuid leaf 0x80000021 EAX bit propagation code Kim Phillips
2023-01-26 10:12 ` [tip: x86/cpu] KVM: x86: Move open-coded CPUID " tip-bot2 for Kim Phillips
2023-01-24 16:33 ` [PATCH v9 3/8] x86/cpu, kvm: Add the NO_NESTED_DATA_BP feature Kim Phillips
2023-01-26 10:12 ` [tip: x86/cpu] " tip-bot2 for Kim Phillips
2023-01-24 16:33 ` [PATCH v9 4/8] x86/cpu, kvm: Move X86_FEATURE_LFENCE_RDTSC to its native leaf Kim Phillips
2023-01-24 21:32 ` Sean Christopherson
2023-01-25 12:09 ` Borislav Petkov
2023-01-26 10:12 ` tip-bot2 for Kim Phillips [this message]
2023-01-24 16:33 ` [PATCH v9 5/8] x86/cpu, kvm: Add the Null Selector Clears Base feature Kim Phillips
2023-01-26 10:12 ` [tip: x86/cpu] " tip-bot2 for Kim Phillips
2023-01-24 16:33 ` [PATCH v9 6/8] x86/cpu, kvm: Add the SMM_CTL MSR not present feature Kim Phillips
2023-01-26 10:12 ` [tip: x86/cpu] " tip-bot2 for Kim Phillips
2023-01-24 16:33 ` [PATCH v9 7/8] x86/cpu: Support AMD Automatic IBRS Kim Phillips
2023-01-26 10:12 ` [tip: x86/cpu] " tip-bot2 for Kim Phillips
2023-02-24 18:52 ` [PATCH v9 7/8] " Josh Poimboeuf
2023-02-24 21:08 ` Borislav Petkov
2023-02-24 21:35 ` Josh Poimboeuf
2023-02-24 21:59 ` Borislav Petkov
2023-02-24 22:03 ` Luck, Tony
2023-02-24 22:12 ` Borislav Petkov
2023-02-24 23:30 ` pawan.kumar.gupta
2023-03-10 10:23 ` [tip: x86/misc] MAINTAINERS: Add x86 hardware vulnerabilities section tip-bot2 for Josh Poimboeuf
2023-02-24 22:51 ` [PATCH v9 7/8] x86/cpu: Support AMD Automatic IBRS Borislav Petkov
2023-02-24 23:23 ` Borislav Petkov
2023-02-25 0:09 ` Josh Poimboeuf
2023-02-25 0:20 ` [PATCH] x86/CPU/AMD: Make sure EFER[AIBRSE] is set Borislav Petkov
2023-02-25 0:52 ` Pawan Gupta
2023-02-25 1:32 ` Josh Poimboeuf
2023-02-25 12:21 ` Borislav Petkov
2023-02-25 17:28 ` Josh Poimboeuf
2023-02-25 22:56 ` Borislav Petkov
2023-02-25 23:43 ` Josh Poimboeuf
2023-02-26 11:18 ` Borislav Petkov
2023-02-26 17:27 ` Josh Poimboeuf
2023-02-26 18:44 ` Borislav Petkov
2023-02-27 15:25 ` Dave Hansen
2023-02-27 15:40 ` Borislav Petkov
2023-02-27 16:39 ` Dave Hansen
2023-03-10 16:22 ` [PATCH -v2] " Borislav Petkov
2023-03-13 15:42 ` Dave Hansen
2023-03-16 11:04 ` [tip: x86/cpu] " tip-bot2 for Borislav Petkov (AMD)
2023-01-24 16:33 ` [PATCH v9 8/8] KVM: x86: Propagate the AMD Automatic IBRS feature to the guest Kim Phillips
2023-01-26 10:12 ` [tip: x86/cpu] " tip-bot2 for Kim Phillips
2023-01-24 21:37 ` [PATCH v9 0/8] x86/cpu, kvm: Support AMD Automatic IBRS Sean Christopherson
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