[PATCH v3 0/2] riscv: allow case-insensitive ISA string parsing

* [PATCH v3 0/2] riscv: allow case-insensitive ISA string parsing
@ 2023-05-01 16:10 Yangyu Chen
  2023-05-01 16:17 ` [PATCH v3 1/2] " Yangyu Chen
                   ` (3 more replies)
  0 siblings, 4 replies; 5+ messages in thread
From: Yangyu Chen @ 2023-05-01 16:10 UTC (permalink / raw)
  To: Conor Dooley, Paul Walmsley, Palmer Dabbelt, Albert Ou,
	Rob Herring, Krzysztof Kozlowski
  Cc: linux-riscv, linux-kernel, Andrew Jones, Wende Tan, Soha Jin,
	Hongren Zheng, Yangyu Chen

This patchset allows case-insensitive ISA string parsing, which is
needed in the ACPI environment. As the RISC-V Hart Capabilities Table
(RHCT) description in UEFI Forum ECR[1] shows the format of the ISA
string is defined in the RISC-V unprivileged specification[2]. However,
the RISC-V unprivileged specification defines the ISA naming strings are
case-insensitive while the current ISA string parser in the kernel only
accepts lowercase letters. In this case, the kernel should allow
case-insensitive ISA string parsing. Moreover, this reason has been
discussed in Conor's patch[3]. And I have also checked the current ISA
string parsing in the recent ACPI support patch[4] will also call
`riscv_fill_hwcap` function as DT we use now.

The original motivation for my patch v1[5] is that some SoC generators
will provide generated DT with illegal ISA string in dt-binding such as
rocket-chip, which will even cause kernel panic in some cases as I
mentioned in v1[5]. Now, the rocket-chip has been fixed in PR #3333[6].
However, when using some specific version of rocket-chip with
illegal ISA string in DT, this patchset will also work for parsing
uppercase letters correctly in DT, thus will have better compatibility.

In summary, this patch not only works for case-insensitive ISA string
parsing to meet the requirements in ECR[1] but also can be a workaround
for some specific versions of rocket-chip.

[1] https://drive.google.com/file/d/1nP3nFiH4jkPMp6COOxP6123DCZKR-tia/view
[2] https://github.com/riscv/riscv-isa-manual/blob/main/src/naming.adoc
[3] https://lore.kernel.org/all/20230426-getting-tactile-e6cee2cdf870@spud/
[4] https://lore.kernel.org/linux-riscv/20230404182037.863533-14-sunilvl@ventanamicro.com/
[5] https://lore.kernel.org/all/tencent_1647475C9618C390BEC601BE2CC1206D0C07@qq.com/
[6] https://github.com/chipsalliance/rocket-chip/pull/3333

Changes since v2:
* Fixed misaligned '\' in `riscv_fill_hwcap`
* Move case 'S' after 's' to make the workaround only works for QEMU 
    in `riscv_fill_hwcap`

Changes since v1:
* Remove convert all isa string to lowercase letters in `print_isa`
* Remove warp parser pointer dereference with tolower in switch, use
    uppercase letter case instead in `riscv_fill_hwcap`
* Remove allow uppercase letters in dt-bindings
* Add Conor Dooley's patch which drops invalid comment about riscv,isa
    lower-case reasoning

Conor Dooley (1):
  dt-bindings: riscv: drop invalid comment about riscv,isa lower-case
    reasoning

Yangyu Chen (1):
  riscv: allow case-insensitive ISA string parsing

 .../devicetree/bindings/riscv/cpus.yaml       |  2 +-
 arch/riscv/kernel/cpu.c                       |  3 +-
 arch/riscv/kernel/cpufeature.c                | 35 +++++++++----------
 3 files changed, 20 insertions(+), 20 deletions(-)

-- 
2.40.1

^ permalink raw reply	[flat|nested] 5+ messages in thread