* [PATCH 0/2] Update parts of PLL_TEST_CTL(_U) if required
@ 2023-06-01 9:39 Konrad Dybcio
2023-06-01 9:39 ` [PATCH 1/2] clk: qcom: clk-alpha-pll: Add a way to update some bits of test_ctl(_hi) Konrad Dybcio
` (3 more replies)
0 siblings, 4 replies; 5+ messages in thread
From: Konrad Dybcio @ 2023-06-01 9:39 UTC (permalink / raw)
To: Bjorn Andersson, Andy Gross, Michael Turquette, Stephen Boyd,
Iskren Chernev
Cc: Marijn Suijten, linux-arm-msm, linux-clk, linux-kernel, Konrad Dybcio
Some recent-ish clock drivers touching on the "standard" Alpha PLLs
have been specifying the values that should be written into the CTL
registers as mask-value combos, but that wasn't always reflected
properly (or at all). This series tries to fix that without affecitng
the drivers that actually provide the full register values.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
Konrad Dybcio (2):
clk: qcom: clk-alpha-pll: Add a way to update some bits of test_ctl(_hi)
clk: qcom: gcc-sm6115: Add missing PLL config properties
drivers/clk/qcom/clk-alpha-pll.c | 19 +++++++++++++++----
drivers/clk/qcom/clk-alpha-pll.h | 2 ++
drivers/clk/qcom/gcc-sm6115.c | 8 ++++++++
3 files changed, 25 insertions(+), 4 deletions(-)
---
base-commit: 571d71e886a5edc89b4ea6d0fe6f445282938320
change-id: 20230601-topic-alpha_ctl-ab0dc0ad3654
Best regards,
--
Konrad Dybcio <konrad.dybcio@linaro.org>
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH 1/2] clk: qcom: clk-alpha-pll: Add a way to update some bits of test_ctl(_hi)
2023-06-01 9:39 [PATCH 0/2] Update parts of PLL_TEST_CTL(_U) if required Konrad Dybcio
@ 2023-06-01 9:39 ` Konrad Dybcio
2023-06-01 9:39 ` [PATCH 2/2] clk: qcom: gcc-sm6115: Add missing PLL config properties Konrad Dybcio
` (2 subsequent siblings)
3 siblings, 0 replies; 5+ messages in thread
From: Konrad Dybcio @ 2023-06-01 9:39 UTC (permalink / raw)
To: Bjorn Andersson, Andy Gross, Michael Turquette, Stephen Boyd,
Iskren Chernev
Cc: Marijn Suijten, linux-arm-msm, linux-clk, linux-kernel, Konrad Dybcio
The "vanilla" Alpha PLL configs are sometimes provided with an intention
to only update certain bits of th register.
Do so if a mask is found.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
drivers/clk/qcom/clk-alpha-pll.c | 19 +++++++++++++++----
drivers/clk/qcom/clk-alpha-pll.h | 2 ++
2 files changed, 17 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c
index f81c7c561352..e4ef645f65d1 100644
--- a/drivers/clk/qcom/clk-alpha-pll.c
+++ b/drivers/clk/qcom/clk-alpha-pll.c
@@ -384,10 +384,21 @@ void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val);
- clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll),
- config->test_ctl_val);
- clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll),
- config->test_ctl_hi_val);
+ if (config->test_ctl_mask)
+ regmap_update_bits(regmap, PLL_TEST_CTL(pll),
+ config->test_ctl_mask,
+ config->test_ctl_val);
+ else
+ clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll),
+ config->test_ctl_val);
+
+ if (config->test_ctl_hi_mask)
+ regmap_update_bits(regmap, PLL_TEST_CTL_U(pll),
+ config->test_ctl_hi_mask,
+ config->test_ctl_hi_val);
+ else
+ clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll),
+ config->test_ctl_hi_val);
if (pll->flags & SUPPORTS_FSM_MODE)
qcom_pll_set_fsm_mode(regmap, PLL_MODE(pll), 6, 0);
diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-pll.h
index 6ff0d08eb938..e4bd863027ab 100644
--- a/drivers/clk/qcom/clk-alpha-pll.h
+++ b/drivers/clk/qcom/clk-alpha-pll.h
@@ -123,7 +123,9 @@ struct alpha_pll_config {
u32 user_ctl_hi_val;
u32 user_ctl_hi1_val;
u32 test_ctl_val;
+ u32 test_ctl_mask;
u32 test_ctl_hi_val;
+ u32 test_ctl_hi_mask;
u32 test_ctl_hi1_val;
u32 test_ctl_hi2_val;
u32 main_output_mask;
--
2.40.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH 2/2] clk: qcom: gcc-sm6115: Add missing PLL config properties
2023-06-01 9:39 [PATCH 0/2] Update parts of PLL_TEST_CTL(_U) if required Konrad Dybcio
2023-06-01 9:39 ` [PATCH 1/2] clk: qcom: clk-alpha-pll: Add a way to update some bits of test_ctl(_hi) Konrad Dybcio
@ 2023-06-01 9:39 ` Konrad Dybcio
2023-06-02 11:08 ` [PATCH 0/2] Update parts of PLL_TEST_CTL(_U) if required Iskren Chernev
2023-06-13 23:48 ` Bjorn Andersson
3 siblings, 0 replies; 5+ messages in thread
From: Konrad Dybcio @ 2023-06-01 9:39 UTC (permalink / raw)
To: Bjorn Andersson, Andy Gross, Michael Turquette, Stephen Boyd,
Iskren Chernev
Cc: Marijn Suijten, linux-arm-msm, linux-clk, linux-kernel, Konrad Dybcio
When the driver was ported upstream, PLL ctl register values were omitted.
Add them to ensure the PLLs are fully configured like we expect them to.
Fixes: cbe63bfdc54f ("clk: qcom: Add Global Clock controller (GCC) driver for SM6115")
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
drivers/clk/qcom/gcc-sm6115.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/clk/qcom/gcc-sm6115.c b/drivers/clk/qcom/gcc-sm6115.c
index 5f09aefa7fb9..033e308ff865 100644
--- a/drivers/clk/qcom/gcc-sm6115.c
+++ b/drivers/clk/qcom/gcc-sm6115.c
@@ -119,6 +119,8 @@ static const struct alpha_pll_config gpll10_config = {
.vco_mask = GENMASK(21, 20),
.main_output_mask = BIT(0),
.config_ctl_val = 0x4001055b,
+ .test_ctl_hi1_val = 0x1,
+ .test_ctl_hi_mask = 0x1,
};
static struct clk_alpha_pll gpll10 = {
@@ -170,6 +172,8 @@ static const struct alpha_pll_config gpll11_config = {
.vco_val = 0x2 << 20,
.vco_mask = GENMASK(21, 20),
.config_ctl_val = 0x4001055b,
+ .test_ctl_hi1_val = 0x1,
+ .test_ctl_hi_mask = 0x1,
};
static struct clk_alpha_pll gpll11 = {
@@ -362,6 +366,8 @@ static const struct alpha_pll_config gpll8_config = {
.post_div_val = 0x1 << 8,
.post_div_mask = GENMASK(11, 8),
.config_ctl_val = 0x4001055b,
+ .test_ctl_hi1_val = 0x1,
+ .test_ctl_hi_mask = 0x1,
};
static struct clk_alpha_pll gpll8 = {
@@ -413,6 +419,8 @@ static const struct alpha_pll_config gpll9_config = {
.post_div_mask = GENMASK(9, 8),
.main_output_mask = BIT(0),
.config_ctl_val = 0x00004289,
+ .test_ctl_mask = GENMASK(31, 0),
+ .test_ctl_val = 0x08000000,
};
static struct clk_alpha_pll gpll9 = {
--
2.40.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH 0/2] Update parts of PLL_TEST_CTL(_U) if required
2023-06-01 9:39 [PATCH 0/2] Update parts of PLL_TEST_CTL(_U) if required Konrad Dybcio
2023-06-01 9:39 ` [PATCH 1/2] clk: qcom: clk-alpha-pll: Add a way to update some bits of test_ctl(_hi) Konrad Dybcio
2023-06-01 9:39 ` [PATCH 2/2] clk: qcom: gcc-sm6115: Add missing PLL config properties Konrad Dybcio
@ 2023-06-02 11:08 ` Iskren Chernev
2023-06-13 23:48 ` Bjorn Andersson
3 siblings, 0 replies; 5+ messages in thread
From: Iskren Chernev @ 2023-06-02 11:08 UTC (permalink / raw)
To: Konrad Dybcio, Bjorn Andersson, Andy Gross, Michael Turquette,
Stephen Boyd
Cc: Marijn Suijten, linux-arm-msm, linux-clk, linux-kernel
On June 1, 2023 12:39:06 PM GMT+03:00, Konrad Dybcio <konrad.dybcio@linaro.org> wrote:
>Some recent-ish clock drivers touching on the "standard" Alpha PLLs
>have been specifying the values that should be written into the CTL
>registers as mask-value combos, but that wasn't always reflected
>properly (or at all).
Yeah, that would be me. I didn't feel confident enough to add the mask parameter, but it seems very reasonable.
> This series tries to fix that without affecitng
>the drivers that actually provide the full register values.
>
>Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Iskren Chernev <me@iskren.info>
>---
>Konrad Dybcio (2):
> clk: qcom: clk-alpha-pll: Add a way to update some bits of test_ctl(_hi)
> clk: qcom: gcc-sm6115: Add missing PLL config properties
>
> drivers/clk/qcom/clk-alpha-pll.c | 19 +++++++++++++++----
> drivers/clk/qcom/clk-alpha-pll.h | 2 ++
> drivers/clk/qcom/gcc-sm6115.c | 8 ++++++++
> 3 files changed, 25 insertions(+), 4 deletions(-)
>---
>base-commit: 571d71e886a5edc89b4ea6d0fe6f445282938320
>change-id: 20230601-topic-alpha_ctl-ab0dc0ad3654
>
>Best regards,
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH 0/2] Update parts of PLL_TEST_CTL(_U) if required
2023-06-01 9:39 [PATCH 0/2] Update parts of PLL_TEST_CTL(_U) if required Konrad Dybcio
` (2 preceding siblings ...)
2023-06-02 11:08 ` [PATCH 0/2] Update parts of PLL_TEST_CTL(_U) if required Iskren Chernev
@ 2023-06-13 23:48 ` Bjorn Andersson
3 siblings, 0 replies; 5+ messages in thread
From: Bjorn Andersson @ 2023-06-13 23:48 UTC (permalink / raw)
To: Michael Turquette, Andy Gross, Iskren Chernev, Stephen Boyd,
Konrad Dybcio
Cc: linux-arm-msm, Marijn Suijten, linux-clk, linux-kernel
On Thu, 01 Jun 2023 11:39:06 +0200, Konrad Dybcio wrote:
> Some recent-ish clock drivers touching on the "standard" Alpha PLLs
> have been specifying the values that should be written into the CTL
> registers as mask-value combos, but that wasn't always reflected
> properly (or at all). This series tries to fix that without affecitng
> the drivers that actually provide the full register values.
>
>
> [...]
Applied, thanks!
[1/2] clk: qcom: clk-alpha-pll: Add a way to update some bits of test_ctl(_hi)
commit: 501624339466a7896bb8a1f048cf8dcfd54b174e
[2/2] clk: qcom: gcc-sm6115: Add missing PLL config properties
commit: e88c533d8a2a0fe84bb54cff1569bd079ad3512c
Best regards,
--
Bjorn Andersson <andersson@kernel.org>
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2023-06-13 23:49 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-06-01 9:39 [PATCH 0/2] Update parts of PLL_TEST_CTL(_U) if required Konrad Dybcio
2023-06-01 9:39 ` [PATCH 1/2] clk: qcom: clk-alpha-pll: Add a way to update some bits of test_ctl(_hi) Konrad Dybcio
2023-06-01 9:39 ` [PATCH 2/2] clk: qcom: gcc-sm6115: Add missing PLL config properties Konrad Dybcio
2023-06-02 11:08 ` [PATCH 0/2] Update parts of PLL_TEST_CTL(_U) if required Iskren Chernev
2023-06-13 23:48 ` Bjorn Andersson
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).