[PATCH 0/4] X Elite fixups

[PATCH 0/4] X Elite fixups

[Konrad Dybcio]

Just a couple of "usual" fixups that slipped through introduction
reviews..

p1-2 for icc
p3-4 for qcom

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
Konrad Dybcio (4):
      interconnect: qcom: x1e80100: Remove bogus per-RSC BCMs and nodes
      dt-bindings: interconnect: Remove bogus interconnect nodes
      arm64: dts: qcom: x1e80100: Add missing system-wide PSCI power domain
      arm64: dts: qcom: x1e80100: Flush RSC sleep & wake votes

 arch/arm64/boot/dts/qcom/x1e80100.dtsi             |   9 +
 drivers/interconnect/qcom/x1e80100.c               | 315 ---------------------
 .../dt-bindings/interconnect/qcom,x1e80100-rpmh.h  |  24 --
 3 files changed, 9 insertions(+), 339 deletions(-)
---
base-commit: ab0b3e6ef50d305278b1971891cf1d82ab050b35
change-id: 20240102-topic-x1e_fixes-a62d8f5a1b75

Best regards,
-- 
Konrad Dybcio <konrad.dybcio@linaro.org>

[PATCH 1/4] interconnect: qcom: x1e80100: Remove bogus per-RSC BCMs and nodes

[Konrad Dybcio]

The downstream kernel has infrastructure for passing votes from different
interconnect nodes onto different RPMh RSCs. This neither implemented, not
is going to be implemented upstream (in favor of a different solution
using ICC tags through the same node).

Unfortunately, as it happens, meaningless (in the upstream context) parts
of the vendor driver were copied, ending up causing havoc - since all
"per-RSC" (in quotes because they all point to the main APPS one) BCMs
defined within the driver overwrite the value in RPMh on every
aggregation.

To both avoid keeping bogus code around and possibly introducing
impossible-to-track-down bugs (busses shutting down for no reason), get
rid of the duplicated BCMs and their associated ICC nodes.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
 drivers/interconnect/qcom/x1e80100.c | 315 -----------------------------------
 1 file changed, 315 deletions(-)

diff --git a/drivers/interconnect/qcom/x1e80100.c b/drivers/interconnect/qcom/x1e80100.c
index d19501d913b3..5b2de9c3a1d6 100644
--- a/drivers/interconnect/qcom/x1e80100.c
+++ b/drivers/interconnect/qcom/x1e80100.c
@@ -670,150 +670,6 @@ static struct qcom_icc_node xm_usb4_2 = {
 	.links = { X1E80100_SLAVE_AGGRE_USB_SOUTH },
 };
 
-static struct qcom_icc_node qnm_mnoc_hf_disp = {
-	.name = "qnm_mnoc_hf_disp",
-	.id = X1E80100_MASTER_MNOC_HF_MEM_NOC_DISP,
-	.channels = 2,
-	.buswidth = 32,
-	.num_links = 1,
-	.links = { X1E80100_SLAVE_LLCC_DISP },
-};
-
-static struct qcom_icc_node qnm_pcie_disp = {
-	.name = "qnm_pcie_disp",
-	.id = X1E80100_MASTER_ANOC_PCIE_GEM_NOC_DISP,
-	.channels = 1,
-	.buswidth = 64,
-	.num_links = 1,
-	.links = { X1E80100_SLAVE_LLCC_DISP },
-};
-
-static struct qcom_icc_node llcc_mc_disp = {
-	.name = "llcc_mc_disp",
-	.id = X1E80100_MASTER_LLCC_DISP,
-	.channels = 8,
-	.buswidth = 4,
-	.num_links = 1,
-	.links = { X1E80100_SLAVE_EBI1_DISP },
-};
-
-static struct qcom_icc_node qnm_mdp_disp = {
-	.name = "qnm_mdp_disp",
-	.id = X1E80100_MASTER_MDP_DISP,
-	.channels = 2,
-	.buswidth = 32,
-	.num_links = 1,
-	.links = { X1E80100_SLAVE_MNOC_HF_MEM_NOC_DISP },
-};
-
-static struct qcom_icc_node qnm_pcie_pcie = {
-	.name = "qnm_pcie_pcie",
-	.id = X1E80100_MASTER_ANOC_PCIE_GEM_NOC_PCIE,
-	.channels = 1,
-	.buswidth = 64,
-	.num_links = 1,
-	.links = { X1E80100_SLAVE_LLCC_PCIE },
-};
-
-static struct qcom_icc_node llcc_mc_pcie = {
-	.name = "llcc_mc_pcie",
-	.id = X1E80100_MASTER_LLCC_PCIE,
-	.channels = 8,
-	.buswidth = 4,
-	.num_links = 1,
-	.links = { X1E80100_SLAVE_EBI1_PCIE },
-};
-
-static struct qcom_icc_node qnm_pcie_north_gem_noc_pcie = {
-	.name = "qnm_pcie_north_gem_noc_pcie",
-	.id = X1E80100_MASTER_PCIE_NORTH_PCIE,
-	.channels = 1,
-	.buswidth = 64,
-	.num_links = 1,
-	.links = { X1E80100_SLAVE_ANOC_PCIE_GEM_NOC_PCIE },
-};
-
-static struct qcom_icc_node qnm_pcie_south_gem_noc_pcie = {
-	.name = "qnm_pcie_south_gem_noc_pcie",
-	.id = X1E80100_MASTER_PCIE_SOUTH_PCIE,
-	.channels = 1,
-	.buswidth = 64,
-	.num_links = 1,
-	.links = { X1E80100_SLAVE_ANOC_PCIE_GEM_NOC_PCIE },
-};
-
-static struct qcom_icc_node xm_pcie_3_pcie = {
-	.name = "xm_pcie_3_pcie",
-	.id = X1E80100_MASTER_PCIE_3_PCIE,
-	.channels = 1,
-	.buswidth = 64,
-	.num_links = 1,
-	.links = { X1E80100_SLAVE_PCIE_NORTH_PCIE },
-};
-
-static struct qcom_icc_node xm_pcie_4_pcie = {
-	.name = "xm_pcie_4_pcie",
-	.id = X1E80100_MASTER_PCIE_4_PCIE,
-	.channels = 1,
-	.buswidth = 8,
-	.num_links = 1,
-	.links = { X1E80100_SLAVE_PCIE_NORTH_PCIE },
-};
-
-static struct qcom_icc_node xm_pcie_5_pcie = {
-	.name = "xm_pcie_5_pcie",
-	.id = X1E80100_MASTER_PCIE_5_PCIE,
-	.channels = 1,
-	.buswidth = 8,
-	.num_links = 1,
-	.links = { X1E80100_SLAVE_PCIE_NORTH_PCIE },
-};
-
-static struct qcom_icc_node xm_pcie_0_pcie = {
-	.name = "xm_pcie_0_pcie",
-	.id = X1E80100_MASTER_PCIE_0_PCIE,
-	.channels = 1,
-	.buswidth = 16,
-	.num_links = 1,
-	.links = { X1E80100_SLAVE_PCIE_SOUTH_PCIE },
-};
-
-static struct qcom_icc_node xm_pcie_1_pcie = {
-	.name = "xm_pcie_1_pcie",
-	.id = X1E80100_MASTER_PCIE_1_PCIE,
-	.channels = 1,
-	.buswidth = 16,
-	.num_links = 1,
-	.links = { X1E80100_SLAVE_PCIE_SOUTH_PCIE },
-};
-
-static struct qcom_icc_node xm_pcie_2_pcie = {
-	.name = "xm_pcie_2_pcie",
-	.id = X1E80100_MASTER_PCIE_2_PCIE,
-	.channels = 1,
-	.buswidth = 16,
-	.num_links = 1,
-	.links = { X1E80100_SLAVE_PCIE_SOUTH_PCIE },
-};
-
-static struct qcom_icc_node xm_pcie_6a_pcie = {
-	.name = "xm_pcie_6a_pcie",
-	.id = X1E80100_MASTER_PCIE_6A_PCIE,
-	.channels = 1,
-	.buswidth = 32,
-	.num_links = 1,
-	.links = { X1E80100_SLAVE_PCIE_SOUTH_PCIE },
-};
-
-static struct qcom_icc_node xm_pcie_6b_pcie = {
-	.name = "xm_pcie_6b_pcie",
-	.id = X1E80100_MASTER_PCIE_6B_PCIE,
-	.channels = 1,
-	.buswidth = 16,
-	.num_links = 1,
-	.links = { X1E80100_SLAVE_PCIE_SOUTH_PCIE },
-};
-
 static struct qcom_icc_node qns_a1noc_snoc = {
 	.name = "qns_a1noc_snoc",
 	.id = X1E80100_SLAVE_A1NOC_SNOC,
@@ -1514,76 +1370,6 @@ static struct qcom_icc_node qns_aggre_usb_south_snoc = {
 	.links = { X1E80100_MASTER_AGGRE_USB_SOUTH },
 };
 
-static struct qcom_icc_node qns_llcc_disp = {
-	.name = "qns_llcc_disp",
-	.id = X1E80100_SLAVE_LLCC_DISP,
-	.channels = 8,
-	.buswidth = 16,
-	.num_links = 1,
-	.links = { X1E80100_MASTER_LLCC_DISP },
-};
-
-static struct qcom_icc_node ebi_disp = {
-	.name = "ebi_disp",
-	.id = X1E80100_SLAVE_EBI1_DISP,
-	.channels = 8,
-	.buswidth = 4,
-	.num_links = 0,
-};
-
-static struct qcom_icc_node qns_mem_noc_hf_disp = {
-	.name = "qns_mem_noc_hf_disp",
-	.id = X1E80100_SLAVE_MNOC_HF_MEM_NOC_DISP,
-	.channels = 2,
-	.buswidth = 32,
-	.num_links = 1,
-	.links = { X1E80100_MASTER_MNOC_HF_MEM_NOC_DISP },
-};
-
-static struct qcom_icc_node qns_llcc_pcie = {
-	.name = "qns_llcc_pcie",
-	.id = X1E80100_SLAVE_LLCC_PCIE,
-	.channels = 8,
-	.buswidth = 16,
-	.num_links = 1,
-	.links = { X1E80100_MASTER_LLCC_PCIE },
-};
-
-static struct qcom_icc_node ebi_pcie = {
-	.name = "ebi_pcie",
-	.id = X1E80100_SLAVE_EBI1_PCIE,
-	.channels = 8,
-	.buswidth = 4,
-	.num_links = 0,
-};
-
-static struct qcom_icc_node qns_pcie_mem_noc_pcie = {
-	.name = "qns_pcie_mem_noc_pcie",
-	.id = X1E80100_SLAVE_ANOC_PCIE_GEM_NOC_PCIE,
-	.channels = 1,
-	.buswidth = 64,
-	.num_links = 1,
-	.links = { X1E80100_MASTER_ANOC_PCIE_GEM_NOC_PCIE },
-};
-
-static struct qcom_icc_node qns_pcie_north_gem_noc_pcie = {
-	.name = "qns_pcie_north_gem_noc_pcie",
-	.id = X1E80100_SLAVE_PCIE_NORTH_PCIE,
-	.channels = 1,
-	.buswidth = 64,
-	.num_links = 1,
-	.links = { X1E80100_MASTER_PCIE_NORTH_PCIE },
-};
-
-static struct qcom_icc_node qns_pcie_south_gem_noc_pcie = {
-	.name = "qns_pcie_south_gem_noc_pcie",
-	.id = X1E80100_SLAVE_PCIE_SOUTH_PCIE,
-	.channels = 1,
-	.buswidth = 64,
-	.num_links = 1,
-	.links = { X1E80100_MASTER_PCIE_SOUTH_PCIE },
-};
-
 static struct qcom_icc_bcm bcm_acv = {
 	.name = "ACV",
 	.num_nodes = 1,
@@ -1755,72 +1541,6 @@ static struct qcom_icc_bcm bcm_sn4 = {
 	.nodes = { &qnm_usb_anoc },
 };
 
-static struct qcom_icc_bcm bcm_acv_disp = {
-	.name = "ACV",
-	.num_nodes = 1,
-	.nodes = { &ebi_disp },
-};
-
-static struct qcom_icc_bcm bcm_mc0_disp = {
-	.name = "MC0",
-	.num_nodes = 1,
-	.nodes = { &ebi_disp },
-};
-
-static struct qcom_icc_bcm bcm_mm0_disp = {
-	.name = "MM0",
-	.num_nodes = 1,
-	.nodes = { &qns_mem_noc_hf_disp },
-};
-
-static struct qcom_icc_bcm bcm_mm1_disp = {
-	.name = "MM1",
-	.num_nodes = 1,
-	.nodes = { &qnm_mdp_disp },
-};
-
-static struct qcom_icc_bcm bcm_sh0_disp = {
-	.name = "SH0",
-	.num_nodes = 1,
-	.nodes = { &qns_llcc_disp },
-};
-
-static struct qcom_icc_bcm bcm_sh1_disp = {
-	.name = "SH1",
-	.num_nodes = 2,
-	.nodes = { &qnm_mnoc_hf_disp, &qnm_pcie_disp },
-};
-
-static struct qcom_icc_bcm bcm_acv_pcie = {
-	.name = "ACV",
-	.num_nodes = 1,
-	.nodes = { &ebi_pcie },
-};
-
-static struct qcom_icc_bcm bcm_mc0_pcie = {
-	.name = "MC0",
-	.num_nodes = 1,
-	.nodes = { &ebi_pcie },
-};
-
-static struct qcom_icc_bcm bcm_pc0_pcie = {
-	.name = "PC0",
-	.num_nodes = 1,
-	.nodes = { &qns_pcie_mem_noc_pcie },
-};
-
-static struct qcom_icc_bcm bcm_sh0_pcie = {
-	.name = "SH0",
-	.num_nodes = 1,
-	.nodes = { &qns_llcc_pcie },
-};
-
-static struct qcom_icc_bcm bcm_sh1_pcie = {
-	.name = "SH1",
-	.num_nodes = 1,
-	.nodes = { &qnm_pcie_pcie },
-};
-
 static struct qcom_icc_bcm *aggre1_noc_bcms[] = {
 };
 
@@ -1982,10 +1702,6 @@ static const struct qcom_icc_desc x1e80100_cnoc_main = {
 static struct qcom_icc_bcm * const gem_noc_bcms[] = {
 	&bcm_sh0,
 	&bcm_sh1,
-	&bcm_sh0_disp,
-	&bcm_sh1_disp,
-	&bcm_sh0_pcie,
-	&bcm_sh1_pcie,
 };
 
 static struct qcom_icc_node * const gem_noc_nodes[] = {
@@ -2004,11 +1720,6 @@ static struct qcom_icc_node * const gem_noc_nodes[] = {
 	[SLAVE_GEM_NOC_CNOC] = &qns_gem_noc_cnoc,
 	[SLAVE_LLCC] = &qns_llcc,
 	[SLAVE_MEM_NOC_PCIE_SNOC] = &qns_pcie,
-	[MASTER_MNOC_HF_MEM_NOC_DISP] = &qnm_mnoc_hf_disp,
-	[MASTER_ANOC_PCIE_GEM_NOC_DISP] = &qnm_pcie_disp,
-	[SLAVE_LLCC_DISP] = &qns_llcc_disp,
-	[MASTER_ANOC_PCIE_GEM_NOC_PCIE] = &qnm_pcie_pcie,
-	[SLAVE_LLCC_PCIE] = &qns_llcc_pcie,
 };
 
 static const struct qcom_icc_desc x1e80100_gem_noc = {
@@ -2067,19 +1778,11 @@ static const struct qcom_icc_desc x1e80100_lpass_lpicx_noc = {
 static struct qcom_icc_bcm * const mc_virt_bcms[] = {
 	&bcm_acv,
 	&bcm_mc0,
-	&bcm_acv_disp,
-	&bcm_mc0_disp,
-	&bcm_acv_pcie,
-	&bcm_mc0_pcie,
 };
 
 static struct qcom_icc_node * const mc_virt_nodes[] = {
 	[MASTER_LLCC] = &llcc_mc,
 	[SLAVE_EBI1] = &ebi,
-	[MASTER_LLCC_DISP] = &llcc_mc_disp,
-	[SLAVE_EBI1_DISP] = &ebi_disp,
-	[MASTER_LLCC_PCIE] = &llcc_mc_pcie,
-	[SLAVE_EBI1_PCIE] = &ebi_pcie,
 };
 
 static const struct qcom_icc_desc x1e80100_mc_virt = {
@@ -2092,8 +1795,6 @@ static const struct qcom_icc_desc x1e80100_mc_virt = {
 static struct qcom_icc_bcm * const mmss_noc_bcms[] = {
 	&bcm_mm0,
 	&bcm_mm1,
-	&bcm_mm0_disp,
-	&bcm_mm1_disp,
 };
 
 static struct qcom_icc_node * const mmss_noc_nodes[] = {
@@ -2110,8 +1811,6 @@ static struct qcom_icc_node * const mmss_noc_nodes[] = {
 	[SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf,
 	[SLAVE_MNOC_SF_MEM_NOC] = &qns_mem_noc_sf,
 	[SLAVE_SERVICE_MNOC] = &srvc_mnoc,
-	[MASTER_MDP_DISP] = &qnm_mdp_disp,
-	[SLAVE_MNOC_HF_MEM_NOC_DISP] = &qns_mem_noc_hf_disp,
 };
 
 static const struct qcom_icc_desc x1e80100_mmss_noc = {
@@ -2139,16 +1838,12 @@ static const struct qcom_icc_desc x1e80100_nsp_noc = {
 
 static struct qcom_icc_bcm * const pcie_center_anoc_bcms[] = {
 	&bcm_pc0,
-	&bcm_pc0_pcie,
 };
 
 static struct qcom_icc_node * const pcie_center_anoc_nodes[] = {
 	[MASTER_PCIE_NORTH] = &qnm_pcie_north_gem_noc,
 	[MASTER_PCIE_SOUTH] = &qnm_pcie_south_gem_noc,
 	[SLAVE_ANOC_PCIE_GEM_NOC] = &qns_pcie_mem_noc,
-	[MASTER_PCIE_NORTH_PCIE] = &qnm_pcie_north_gem_noc_pcie,
-	[MASTER_PCIE_SOUTH_PCIE] = &qnm_pcie_south_gem_noc_pcie,
-	[SLAVE_ANOC_PCIE_GEM_NOC_PCIE] = &qns_pcie_mem_noc_pcie,
 };
 
 static const struct qcom_icc_desc x1e80100_pcie_center_anoc = {
@@ -2166,10 +1861,6 @@ static struct qcom_icc_node * const pcie_north_anoc_nodes[] = {
 	[MASTER_PCIE_4] = &xm_pcie_4,
 	[MASTER_PCIE_5] = &xm_pcie_5,
 	[SLAVE_PCIE_NORTH] = &qns_pcie_north_gem_noc,
-	[MASTER_PCIE_3_PCIE] = &xm_pcie_3_pcie,
-	[MASTER_PCIE_4_PCIE] = &xm_pcie_4_pcie,
-	[MASTER_PCIE_5_PCIE] = &xm_pcie_5_pcie,
-	[SLAVE_PCIE_NORTH_PCIE] = &qns_pcie_north_gem_noc_pcie,
 };
 
 static const struct qcom_icc_desc x1e80100_pcie_north_anoc = {
@@ -2189,12 +1880,6 @@ static struct qcom_icc_node * const pcie_south_anoc_nodes[] = {
 	[MASTER_PCIE_6A] = &xm_pcie_6a,
 	[MASTER_PCIE_6B] = &xm_pcie_6b,
 	[SLAVE_PCIE_SOUTH] = &qns_pcie_south_gem_noc,
-	[MASTER_PCIE_0_PCIE] = &xm_pcie_0_pcie,
-	[MASTER_PCIE_1_PCIE] = &xm_pcie_1_pcie,
-	[MASTER_PCIE_2_PCIE] = &xm_pcie_2_pcie,
-	[MASTER_PCIE_6A_PCIE] = &xm_pcie_6a_pcie,
-	[MASTER_PCIE_6B_PCIE] = &xm_pcie_6b_pcie,
-	[SLAVE_PCIE_SOUTH_PCIE] = &qns_pcie_south_gem_noc_pcie,
 };
 
 static const struct qcom_icc_desc x1e80100_pcie_south_anoc = {

-- 
2.43.0

[PATCH 2/4] dt-bindings: interconnect: Remove bogus interconnect nodes

[Konrad Dybcio]

The downstream kernel has infrastructure for passing votes from different
interconnect nodes onto different RPMh RSCs. This neither implemented, not
is going to be implemented upstream (in favor of a different solution
using ICC tags through the same node).

Unfortunately, as it happens, meaningless (in the upstream context) parts
of the vendor driver were copied, ending up causing havoc - since all
"per-RSC" (in quotes because they all point to the main APPS one) BCMs
defined within the driver overwrite the value in RPMh on every
aggregation.

To both avoid keeping bogus code around and possibly introducing
impossible-to-track-down bugs (busses shutting down for no reason), get
rid of the duplicated ICC node definitions.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
 .../dt-bindings/interconnect/qcom,x1e80100-rpmh.h  | 24 ----------------------
 1 file changed, 24 deletions(-)

diff --git a/include/dt-bindings/interconnect/qcom,x1e80100-rpmh.h b/include/dt-bindings/interconnect/qcom,x1e80100-rpmh.h
index a38c3472698a..7d9710881149 100644
--- a/include/dt-bindings/interconnect/qcom,x1e80100-rpmh.h
+++ b/include/dt-bindings/interconnect/qcom,x1e80100-rpmh.h
@@ -112,11 +112,6 @@
 #define SLAVE_GEM_NOC_CNOC			12
 #define SLAVE_LLCC				13
 #define SLAVE_MEM_NOC_PCIE_SNOC			14
-#define MASTER_MNOC_HF_MEM_NOC_DISP		15
-#define MASTER_ANOC_PCIE_GEM_NOC_DISP		16
-#define SLAVE_LLCC_DISP				17
-#define MASTER_ANOC_PCIE_GEM_NOC_PCIE		18
-#define SLAVE_LLCC_PCIE				19
 
 #define MASTER_LPIAON_NOC			0
 #define SLAVE_LPASS_GEM_NOC			1
@@ -129,10 +124,6 @@
 
 #define MASTER_LLCC				0
 #define SLAVE_EBI1				1
-#define MASTER_LLCC_DISP			2
-#define SLAVE_EBI1_DISP				3
-#define MASTER_LLCC_PCIE			4
-#define SLAVE_EBI1_PCIE				5
 
 #define MASTER_AV1_ENC				0
 #define MASTER_CAMNOC_HF			1
@@ -147,8 +138,6 @@
 #define SLAVE_MNOC_HF_MEM_NOC			10
 #define SLAVE_MNOC_SF_MEM_NOC			11
 #define SLAVE_SERVICE_MNOC			12
-#define MASTER_MDP_DISP				13
-#define SLAVE_MNOC_HF_MEM_NOC_DISP		14
 
 #define MASTER_CDSP_PROC			0
 #define SLAVE_CDSP_MEM_NOC			1
@@ -156,18 +145,11 @@
 #define MASTER_PCIE_NORTH			0
 #define MASTER_PCIE_SOUTH			1
 #define SLAVE_ANOC_PCIE_GEM_NOC			2
-#define MASTER_PCIE_NORTH_PCIE			3
-#define MASTER_PCIE_SOUTH_PCIE			4
-#define SLAVE_ANOC_PCIE_GEM_NOC_PCIE		5
 
 #define MASTER_PCIE_3				0
 #define MASTER_PCIE_4				1
 #define MASTER_PCIE_5				2
 #define SLAVE_PCIE_NORTH			3
-#define MASTER_PCIE_3_PCIE			4
-#define MASTER_PCIE_4_PCIE			5
-#define MASTER_PCIE_5_PCIE			6
-#define SLAVE_PCIE_NORTH_PCIE			7
 
 #define MASTER_PCIE_0				0
 #define MASTER_PCIE_1				1
@@ -175,12 +157,6 @@
 #define MASTER_PCIE_6A				3
 #define MASTER_PCIE_6B				4
 #define SLAVE_PCIE_SOUTH			5
-#define MASTER_PCIE_0_PCIE			6
-#define MASTER_PCIE_1_PCIE			7
-#define MASTER_PCIE_2_PCIE			8
-#define MASTER_PCIE_6A_PCIE			9
-#define MASTER_PCIE_6B_PCIE			10
-#define SLAVE_PCIE_SOUTH_PCIE			11
 
 #define MASTER_A1NOC_SNOC			0
 #define MASTER_A2NOC_SNOC			1

-- 
2.43.0

[PATCH 3/4] arm64: dts: qcom: x1e80100: Add missing system-wide PSCI power domain

[Konrad Dybcio]

Previous Qualcomm SoCs over the past couple years have used the Arm DSU
architecture, which basically unified the meaning of the "cluster" and
"system". This is however clearly not the case on X1E, as can be seen
by three separate cluster power domains.

Add the lacking system-level power domain. For now it's going to be
always-on, as no system-wide idle states are defined at the moment.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
 arch/arm64/boot/dts/qcom/x1e80100.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
index 6f75fc342ceb..fc164b9b3ef1 100644
--- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
+++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
@@ -395,16 +395,24 @@ CPU_PD11: power-domain-cpu11 {
 		CLUSTER_PD0: power-domain-cpu-cluster0 {
 			#power-domain-cells = <0>;
 			domain-idle-states = <&CLUSTER_CL4>, <&CLUSTER_CL5>;
+			power-domains = <&SYSTEM_PD>;
 		};
 
 		CLUSTER_PD1: power-domain-cpu-cluster1 {
 			#power-domain-cells = <0>;
 			domain-idle-states = <&CLUSTER_CL4>, <&CLUSTER_CL5>;
+			power-domains = <&SYSTEM_PD>;
 		};
 
 		CLUSTER_PD2: power-domain-cpu-cluster2 {
 			#power-domain-cells = <0>;
 			domain-idle-states = <&CLUSTER_CL4>, <&CLUSTER_CL5>;
+			power-domains = <&SYSTEM_PD>;
+		};
+
+		SYSTEM_PD: power-domain-system {
+			#power-domain-cells = <0>;
+			/* TODO: system-wide idle states */
 		};
 	};
 

-- 
2.43.0

[PATCH 4/4] arm64: dts: qcom: x1e80100: Flush RSC sleep & wake votes

[Konrad Dybcio]

The RPMh driver will cache sleep and wake votes until the cluster
power-domain is about to enter idle, to avoid unnecessary writes. So
associate the apps_rsc with the cluster pd, so that it can be notified
about this event.

Without this, only AMC votes are being committed.

Fixes: af16b00578a7 ("arm64: dts: qcom: Add base X1E80100 dtsi and the QCP dts")
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
 arch/arm64/boot/dts/qcom/x1e80100.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
index fc164b9b3ef1..2a14e8e39b3b 100644
--- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
+++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
@@ -3334,6 +3334,7 @@ apps_rsc: rsc@17500000 {
 					  <WAKE_TCS      2>, <CONTROL_TCS   0>;
 
 			label = "apps_rsc";
+			power-domains = <&SYSTEM_PD>;
 
 			apps_bcm_voter: bcm-voter {
 				compatible = "qcom,bcm-voter";

-- 
2.43.0

Re: [PATCH 2/4] dt-bindings: interconnect: Remove bogus interconnect nodes

[Krzysztof Kozlowski]

On 02/01/2024 19:29, Konrad Dybcio wrote:
> The downstream kernel has infrastructure for passing votes from different
> interconnect nodes onto different RPMh RSCs. This neither implemented, not
> is going to be implemented upstream (in favor of a different solution
> using ICC tags through the same node).
> 
> Unfortunately, as it happens, meaningless (in the upstream context) parts
> of the vendor driver were copied, ending up causing havoc - since all
> "per-RSC" (in quotes because they all point to the main APPS one) BCMs
> defined within the driver overwrite the value in RPMh on every
> aggregation.
> 
> To both avoid keeping bogus code around and possibly introducing
> impossible-to-track-down bugs (busses shutting down for no reason), get
> rid of the duplicated ICC node definitions.
> 
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof

Re: [PATCH 3/4] arm64: dts: qcom: x1e80100: Add missing system-wide PSCI power domain

[Abel Vesa]

On 24-01-02 19:29:49, Konrad Dybcio wrote:
> Previous Qualcomm SoCs over the past couple years have used the Arm DSU
> architecture, which basically unified the meaning of the "cluster" and
> "system". This is however clearly not the case on X1E, as can be seen
> by three separate cluster power domains.
> 
> Add the lacking system-level power domain. For now it's going to be
> always-on, as no system-wide idle states are defined at the moment.
> 
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>

Reviewed-by: Abel Vesa <abel.vesa@linaro.org>

> ---
>  arch/arm64/boot/dts/qcom/x1e80100.dtsi | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
> index 6f75fc342ceb..fc164b9b3ef1 100644
> --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
> +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
> @@ -395,16 +395,24 @@ CPU_PD11: power-domain-cpu11 {
>  		CLUSTER_PD0: power-domain-cpu-cluster0 {
>  			#power-domain-cells = <0>;
>  			domain-idle-states = <&CLUSTER_CL4>, <&CLUSTER_CL5>;
> +			power-domains = <&SYSTEM_PD>;
>  		};
>  
>  		CLUSTER_PD1: power-domain-cpu-cluster1 {
>  			#power-domain-cells = <0>;
>  			domain-idle-states = <&CLUSTER_CL4>, <&CLUSTER_CL5>;
> +			power-domains = <&SYSTEM_PD>;
>  		};
>  
>  		CLUSTER_PD2: power-domain-cpu-cluster2 {
>  			#power-domain-cells = <0>;
>  			domain-idle-states = <&CLUSTER_CL4>, <&CLUSTER_CL5>;
> +			power-domains = <&SYSTEM_PD>;
> +		};
> +
> +		SYSTEM_PD: power-domain-system {
> +			#power-domain-cells = <0>;
> +			/* TODO: system-wide idle states */
>  		};
>  	};
>  
> 
> -- 
> 2.43.0
> 

Re: [PATCH 4/4] arm64: dts: qcom: x1e80100: Flush RSC sleep & wake votes

[Abel Vesa]

On 24-01-02 19:29:50, Konrad Dybcio wrote:
> The RPMh driver will cache sleep and wake votes until the cluster
> power-domain is about to enter idle, to avoid unnecessary writes. So
> associate the apps_rsc with the cluster pd, so that it can be notified
> about this event.
> 
> Without this, only AMC votes are being committed.
> 
> Fixes: af16b00578a7 ("arm64: dts: qcom: Add base X1E80100 dtsi and the QCP dts")
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>

Reviewed-by: Abel Vesa <abel.vesa@linaro.org>

> ---
>  arch/arm64/boot/dts/qcom/x1e80100.dtsi | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
> index fc164b9b3ef1..2a14e8e39b3b 100644
> --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
> +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
> @@ -3334,6 +3334,7 @@ apps_rsc: rsc@17500000 {
>  					  <WAKE_TCS      2>, <CONTROL_TCS   0>;
>  
>  			label = "apps_rsc";
> +			power-domains = <&SYSTEM_PD>;
>  
>  			apps_bcm_voter: bcm-voter {
>  				compatible = "qcom,bcm-voter";
> 
> -- 
> 2.43.0
> 

Re: [PATCH 1/4] interconnect: qcom: x1e80100: Remove bogus per-RSC BCMs and nodes

[Rajendra Nayak]

On 1/2/2024 11:59 PM, Konrad Dybcio wrote:
> The downstream kernel has infrastructure for passing votes from different
> interconnect nodes onto different RPMh RSCs. This neither implemented, not
> is going to be implemented upstream (in favor of a different solution
> using ICC tags through the same node).
> 
> Unfortunately, as it happens, meaningless (in the upstream context) parts
> of the vendor driver were copied, ending up causing havoc - since all
> "per-RSC" (in quotes because they all point to the main APPS one) BCMs
> defined within the driver overwrite the value in RPMh on every
> aggregation.
> 
> To both avoid keeping bogus code around and possibly introducing
> impossible-to-track-down bugs (busses shutting down for no reason), get
> rid of the duplicated BCMs and their associated ICC nodes.

Thanks Konrad for catching this, I do see these nodes in other Qualcomm 
SoCs upstream (atleast sm8350/sm8450 and sm8550), perhaps they need to 
be cleaned up as well?

Reviewed-by: Rajendra Nayak <quic_rjendra@quicinc.com>

> 
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> ---
>   drivers/interconnect/qcom/x1e80100.c | 315 -----------------------------------
>   1 file changed, 315 deletions(-)
> 
> diff --git a/drivers/interconnect/qcom/x1e80100.c b/drivers/interconnect/qcom/x1e80100.c
> index d19501d913b3..5b2de9c3a1d6 100644
> --- a/drivers/interconnect/qcom/x1e80100.c
> +++ b/drivers/interconnect/qcom/x1e80100.c
> @@ -670,150 +670,6 @@ static struct qcom_icc_node xm_usb4_2 = {
>   	.links = { X1E80100_SLAVE_AGGRE_USB_SOUTH },
>   };
>   
> -static struct qcom_icc_node qnm_mnoc_hf_disp = {
> -	.name = "qnm_mnoc_hf_disp",
> -	.id = X1E80100_MASTER_MNOC_HF_MEM_NOC_DISP,
> -	.channels = 2,
> -	.buswidth = 32,
> -	.num_links = 1,
> -	.links = { X1E80100_SLAVE_LLCC_DISP },
> -};
> -
> -static struct qcom_icc_node qnm_pcie_disp = {
> -	.name = "qnm_pcie_disp",
> -	.id = X1E80100_MASTER_ANOC_PCIE_GEM_NOC_DISP,
> -	.channels = 1,
> -	.buswidth = 64,
> -	.num_links = 1,
> -	.links = { X1E80100_SLAVE_LLCC_DISP },
> -};
> -
> -static struct qcom_icc_node llcc_mc_disp = {
> -	.name = "llcc_mc_disp",
> -	.id = X1E80100_MASTER_LLCC_DISP,
> -	.channels = 8,
> -	.buswidth = 4,
> -	.num_links = 1,
> -	.links = { X1E80100_SLAVE_EBI1_DISP },
> -};
> -
> -static struct qcom_icc_node qnm_mdp_disp = {
> -	.name = "qnm_mdp_disp",
> -	.id = X1E80100_MASTER_MDP_DISP,
> -	.channels = 2,
> -	.buswidth = 32,
> -	.num_links = 1,
> -	.links = { X1E80100_SLAVE_MNOC_HF_MEM_NOC_DISP },
> -};
> -
> -static struct qcom_icc_node qnm_pcie_pcie = {
> -	.name = "qnm_pcie_pcie",
> -	.id = X1E80100_MASTER_ANOC_PCIE_GEM_NOC_PCIE,
> -	.channels = 1,
> -	.buswidth = 64,
> -	.num_links = 1,
> -	.links = { X1E80100_SLAVE_LLCC_PCIE },
> -};
> -
> -static struct qcom_icc_node llcc_mc_pcie = {
> -	.name = "llcc_mc_pcie",
> -	.id = X1E80100_MASTER_LLCC_PCIE,
> -	.channels = 8,
> -	.buswidth = 4,
> -	.num_links = 1,
> -	.links = { X1E80100_SLAVE_EBI1_PCIE },
> -};
> -
> -static struct qcom_icc_node qnm_pcie_north_gem_noc_pcie = {
> -	.name = "qnm_pcie_north_gem_noc_pcie",
> -	.id = X1E80100_MASTER_PCIE_NORTH_PCIE,
> -	.channels = 1,
> -	.buswidth = 64,
> -	.num_links = 1,
> -	.links = { X1E80100_SLAVE_ANOC_PCIE_GEM_NOC_PCIE },
> -};
> -
> -static struct qcom_icc_node qnm_pcie_south_gem_noc_pcie = {
> -	.name = "qnm_pcie_south_gem_noc_pcie",
> -	.id = X1E80100_MASTER_PCIE_SOUTH_PCIE,
> -	.channels = 1,
> -	.buswidth = 64,
> -	.num_links = 1,
> -	.links = { X1E80100_SLAVE_ANOC_PCIE_GEM_NOC_PCIE },
> -};
> -
> -static struct qcom_icc_node xm_pcie_3_pcie = {
> -	.name = "xm_pcie_3_pcie",
> -	.id = X1E80100_MASTER_PCIE_3_PCIE,
> -	.channels = 1,
> -	.buswidth = 64,
> -	.num_links = 1,
> -	.links = { X1E80100_SLAVE_PCIE_NORTH_PCIE },
> -};
> -
> -static struct qcom_icc_node xm_pcie_4_pcie = {
> -	.name = "xm_pcie_4_pcie",
> -	.id = X1E80100_MASTER_PCIE_4_PCIE,
> -	.channels = 1,
> -	.buswidth = 8,
> -	.num_links = 1,
> -	.links = { X1E80100_SLAVE_PCIE_NORTH_PCIE },
> -};
> -
> -static struct qcom_icc_node xm_pcie_5_pcie = {
> -	.name = "xm_pcie_5_pcie",
> -	.id = X1E80100_MASTER_PCIE_5_PCIE,
> -	.channels = 1,
> -	.buswidth = 8,
> -	.num_links = 1,
> -	.links = { X1E80100_SLAVE_PCIE_NORTH_PCIE },
> -};
> -
> -static struct qcom_icc_node xm_pcie_0_pcie = {
> -	.name = "xm_pcie_0_pcie",
> -	.id = X1E80100_MASTER_PCIE_0_PCIE,
> -	.channels = 1,
> -	.buswidth = 16,
> -	.num_links = 1,
> -	.links = { X1E80100_SLAVE_PCIE_SOUTH_PCIE },
> -};
> -
> -static struct qcom_icc_node xm_pcie_1_pcie = {
> -	.name = "xm_pcie_1_pcie",
> -	.id = X1E80100_MASTER_PCIE_1_PCIE,
> -	.channels = 1,
> -	.buswidth = 16,
> -	.num_links = 1,
> -	.links = { X1E80100_SLAVE_PCIE_SOUTH_PCIE },
> -};
> -
> -static struct qcom_icc_node xm_pcie_2_pcie = {
> -	.name = "xm_pcie_2_pcie",
> -	.id = X1E80100_MASTER_PCIE_2_PCIE,
> -	.channels = 1,
> -	.buswidth = 16,
> -	.num_links = 1,
> -	.links = { X1E80100_SLAVE_PCIE_SOUTH_PCIE },
> -};
> -
> -static struct qcom_icc_node xm_pcie_6a_pcie = {
> -	.name = "xm_pcie_6a_pcie",
> -	.id = X1E80100_MASTER_PCIE_6A_PCIE,
> -	.channels = 1,
> -	.buswidth = 32,
> -	.num_links = 1,
> -	.links = { X1E80100_SLAVE_PCIE_SOUTH_PCIE },
> -};
> -
> -static struct qcom_icc_node xm_pcie_6b_pcie = {
> -	.name = "xm_pcie_6b_pcie",
> -	.id = X1E80100_MASTER_PCIE_6B_PCIE,
> -	.channels = 1,
> -	.buswidth = 16,
> -	.num_links = 1,
> -	.links = { X1E80100_SLAVE_PCIE_SOUTH_PCIE },
> -};
> -
>   static struct qcom_icc_node qns_a1noc_snoc = {
>   	.name = "qns_a1noc_snoc",
>   	.id = X1E80100_SLAVE_A1NOC_SNOC,
> @@ -1514,76 +1370,6 @@ static struct qcom_icc_node qns_aggre_usb_south_snoc = {
>   	.links = { X1E80100_MASTER_AGGRE_USB_SOUTH },
>   };
>   
> -static struct qcom_icc_node qns_llcc_disp = {
> -	.name = "qns_llcc_disp",
> -	.id = X1E80100_SLAVE_LLCC_DISP,
> -	.channels = 8,
> -	.buswidth = 16,
> -	.num_links = 1,
> -	.links = { X1E80100_MASTER_LLCC_DISP },
> -};
> -
> -static struct qcom_icc_node ebi_disp = {
> -	.name = "ebi_disp",
> -	.id = X1E80100_SLAVE_EBI1_DISP,
> -	.channels = 8,
> -	.buswidth = 4,
> -	.num_links = 0,
> -};
> -
> -static struct qcom_icc_node qns_mem_noc_hf_disp = {
> -	.name = "qns_mem_noc_hf_disp",
> -	.id = X1E80100_SLAVE_MNOC_HF_MEM_NOC_DISP,
> -	.channels = 2,
> -	.buswidth = 32,
> -	.num_links = 1,
> -	.links = { X1E80100_MASTER_MNOC_HF_MEM_NOC_DISP },
> -};
> -
> -static struct qcom_icc_node qns_llcc_pcie = {
> -	.name = "qns_llcc_pcie",
> -	.id = X1E80100_SLAVE_LLCC_PCIE,
> -	.channels = 8,
> -	.buswidth = 16,
> -	.num_links = 1,
> -	.links = { X1E80100_MASTER_LLCC_PCIE },
> -};
> -
> -static struct qcom_icc_node ebi_pcie = {
> -	.name = "ebi_pcie",
> -	.id = X1E80100_SLAVE_EBI1_PCIE,
> -	.channels = 8,
> -	.buswidth = 4,
> -	.num_links = 0,
> -};
> -
> -static struct qcom_icc_node qns_pcie_mem_noc_pcie = {
> -	.name = "qns_pcie_mem_noc_pcie",
> -	.id = X1E80100_SLAVE_ANOC_PCIE_GEM_NOC_PCIE,
> -	.channels = 1,
> -	.buswidth = 64,
> -	.num_links = 1,
> -	.links = { X1E80100_MASTER_ANOC_PCIE_GEM_NOC_PCIE },
> -};
> -
> -static struct qcom_icc_node qns_pcie_north_gem_noc_pcie = {
> -	.name = "qns_pcie_north_gem_noc_pcie",
> -	.id = X1E80100_SLAVE_PCIE_NORTH_PCIE,
> -	.channels = 1,
> -	.buswidth = 64,
> -	.num_links = 1,
> -	.links = { X1E80100_MASTER_PCIE_NORTH_PCIE },
> -};
> -
> -static struct qcom_icc_node qns_pcie_south_gem_noc_pcie = {
> -	.name = "qns_pcie_south_gem_noc_pcie",
> -	.id = X1E80100_SLAVE_PCIE_SOUTH_PCIE,
> -	.channels = 1,
> -	.buswidth = 64,
> -	.num_links = 1,
> -	.links = { X1E80100_MASTER_PCIE_SOUTH_PCIE },
> -};
> -
>   static struct qcom_icc_bcm bcm_acv = {
>   	.name = "ACV",
>   	.num_nodes = 1,
> @@ -1755,72 +1541,6 @@ static struct qcom_icc_bcm bcm_sn4 = {
>   	.nodes = { &qnm_usb_anoc },
>   };
>   
> -static struct qcom_icc_bcm bcm_acv_disp = {
> -	.name = "ACV",
> -	.num_nodes = 1,
> -	.nodes = { &ebi_disp },
> -};
> -
> -static struct qcom_icc_bcm bcm_mc0_disp = {
> -	.name = "MC0",
> -	.num_nodes = 1,
> -	.nodes = { &ebi_disp },
> -};
> -
> -static struct qcom_icc_bcm bcm_mm0_disp = {
> -	.name = "MM0",
> -	.num_nodes = 1,
> -	.nodes = { &qns_mem_noc_hf_disp },
> -};
> -
> -static struct qcom_icc_bcm bcm_mm1_disp = {
> -	.name = "MM1",
> -	.num_nodes = 1,
> -	.nodes = { &qnm_mdp_disp },
> -};
> -
> -static struct qcom_icc_bcm bcm_sh0_disp = {
> -	.name = "SH0",
> -	.num_nodes = 1,
> -	.nodes = { &qns_llcc_disp },
> -};
> -
> -static struct qcom_icc_bcm bcm_sh1_disp = {
> -	.name = "SH1",
> -	.num_nodes = 2,
> -	.nodes = { &qnm_mnoc_hf_disp, &qnm_pcie_disp },
> -};
> -
> -static struct qcom_icc_bcm bcm_acv_pcie = {
> -	.name = "ACV",
> -	.num_nodes = 1,
> -	.nodes = { &ebi_pcie },
> -};
> -
> -static struct qcom_icc_bcm bcm_mc0_pcie = {
> -	.name = "MC0",
> -	.num_nodes = 1,
> -	.nodes = { &ebi_pcie },
> -};
> -
> -static struct qcom_icc_bcm bcm_pc0_pcie = {
> -	.name = "PC0",
> -	.num_nodes = 1,
> -	.nodes = { &qns_pcie_mem_noc_pcie },
> -};
> -
> -static struct qcom_icc_bcm bcm_sh0_pcie = {
> -	.name = "SH0",
> -	.num_nodes = 1,
> -	.nodes = { &qns_llcc_pcie },
> -};
> -
> -static struct qcom_icc_bcm bcm_sh1_pcie = {
> -	.name = "SH1",
> -	.num_nodes = 1,
> -	.nodes = { &qnm_pcie_pcie },
> -};
> -
>   static struct qcom_icc_bcm *aggre1_noc_bcms[] = {
>   };
>   
> @@ -1982,10 +1702,6 @@ static const struct qcom_icc_desc x1e80100_cnoc_main = {
>   static struct qcom_icc_bcm * const gem_noc_bcms[] = {
>   	&bcm_sh0,
>   	&bcm_sh1,
> -	&bcm_sh0_disp,
> -	&bcm_sh1_disp,
> -	&bcm_sh0_pcie,
> -	&bcm_sh1_pcie,
>   };
>   
>   static struct qcom_icc_node * const gem_noc_nodes[] = {
> @@ -2004,11 +1720,6 @@ static struct qcom_icc_node * const gem_noc_nodes[] = {
>   	[SLAVE_GEM_NOC_CNOC] = &qns_gem_noc_cnoc,
>   	[SLAVE_LLCC] = &qns_llcc,
>   	[SLAVE_MEM_NOC_PCIE_SNOC] = &qns_pcie,
> -	[MASTER_MNOC_HF_MEM_NOC_DISP] = &qnm_mnoc_hf_disp,
> -	[MASTER_ANOC_PCIE_GEM_NOC_DISP] = &qnm_pcie_disp,
> -	[SLAVE_LLCC_DISP] = &qns_llcc_disp,
> -	[MASTER_ANOC_PCIE_GEM_NOC_PCIE] = &qnm_pcie_pcie,
> -	[SLAVE_LLCC_PCIE] = &qns_llcc_pcie,
>   };
>   
>   static const struct qcom_icc_desc x1e80100_gem_noc = {
> @@ -2067,19 +1778,11 @@ static const struct qcom_icc_desc x1e80100_lpass_lpicx_noc = {
>   static struct qcom_icc_bcm * const mc_virt_bcms[] = {
>   	&bcm_acv,
>   	&bcm_mc0,
> -	&bcm_acv_disp,
> -	&bcm_mc0_disp,
> -	&bcm_acv_pcie,
> -	&bcm_mc0_pcie,
>   };
>   
>   static struct qcom_icc_node * const mc_virt_nodes[] = {
>   	[MASTER_LLCC] = &llcc_mc,
>   	[SLAVE_EBI1] = &ebi,
> -	[MASTER_LLCC_DISP] = &llcc_mc_disp,
> -	[SLAVE_EBI1_DISP] = &ebi_disp,
> -	[MASTER_LLCC_PCIE] = &llcc_mc_pcie,
> -	[SLAVE_EBI1_PCIE] = &ebi_pcie,
>   };
>   
>   static const struct qcom_icc_desc x1e80100_mc_virt = {
> @@ -2092,8 +1795,6 @@ static const struct qcom_icc_desc x1e80100_mc_virt = {
>   static struct qcom_icc_bcm * const mmss_noc_bcms[] = {
>   	&bcm_mm0,
>   	&bcm_mm1,
> -	&bcm_mm0_disp,
> -	&bcm_mm1_disp,
>   };
>   
>   static struct qcom_icc_node * const mmss_noc_nodes[] = {
> @@ -2110,8 +1811,6 @@ static struct qcom_icc_node * const mmss_noc_nodes[] = {
>   	[SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf,
>   	[SLAVE_MNOC_SF_MEM_NOC] = &qns_mem_noc_sf,
>   	[SLAVE_SERVICE_MNOC] = &srvc_mnoc,
> -	[MASTER_MDP_DISP] = &qnm_mdp_disp,
> -	[SLAVE_MNOC_HF_MEM_NOC_DISP] = &qns_mem_noc_hf_disp,
>   };
>   
>   static const struct qcom_icc_desc x1e80100_mmss_noc = {
> @@ -2139,16 +1838,12 @@ static const struct qcom_icc_desc x1e80100_nsp_noc = {
>   
>   static struct qcom_icc_bcm * const pcie_center_anoc_bcms[] = {
>   	&bcm_pc0,
> -	&bcm_pc0_pcie,
>   };
>   
>   static struct qcom_icc_node * const pcie_center_anoc_nodes[] = {
>   	[MASTER_PCIE_NORTH] = &qnm_pcie_north_gem_noc,
>   	[MASTER_PCIE_SOUTH] = &qnm_pcie_south_gem_noc,
>   	[SLAVE_ANOC_PCIE_GEM_NOC] = &qns_pcie_mem_noc,
> -	[MASTER_PCIE_NORTH_PCIE] = &qnm_pcie_north_gem_noc_pcie,
> -	[MASTER_PCIE_SOUTH_PCIE] = &qnm_pcie_south_gem_noc_pcie,
> -	[SLAVE_ANOC_PCIE_GEM_NOC_PCIE] = &qns_pcie_mem_noc_pcie,
>   };
>   
>   static const struct qcom_icc_desc x1e80100_pcie_center_anoc = {
> @@ -2166,10 +1861,6 @@ static struct qcom_icc_node * const pcie_north_anoc_nodes[] = {
>   	[MASTER_PCIE_4] = &xm_pcie_4,
>   	[MASTER_PCIE_5] = &xm_pcie_5,
>   	[SLAVE_PCIE_NORTH] = &qns_pcie_north_gem_noc,
> -	[MASTER_PCIE_3_PCIE] = &xm_pcie_3_pcie,
> -	[MASTER_PCIE_4_PCIE] = &xm_pcie_4_pcie,
> -	[MASTER_PCIE_5_PCIE] = &xm_pcie_5_pcie,
> -	[SLAVE_PCIE_NORTH_PCIE] = &qns_pcie_north_gem_noc_pcie,
>   };
>   
>   static const struct qcom_icc_desc x1e80100_pcie_north_anoc = {
> @@ -2189,12 +1880,6 @@ static struct qcom_icc_node * const pcie_south_anoc_nodes[] = {
>   	[MASTER_PCIE_6A] = &xm_pcie_6a,
>   	[MASTER_PCIE_6B] = &xm_pcie_6b,
>   	[SLAVE_PCIE_SOUTH] = &qns_pcie_south_gem_noc,
> -	[MASTER_PCIE_0_PCIE] = &xm_pcie_0_pcie,
> -	[MASTER_PCIE_1_PCIE] = &xm_pcie_1_pcie,
> -	[MASTER_PCIE_2_PCIE] = &xm_pcie_2_pcie,
> -	[MASTER_PCIE_6A_PCIE] = &xm_pcie_6a_pcie,
> -	[MASTER_PCIE_6B_PCIE] = &xm_pcie_6b_pcie,
> -	[SLAVE_PCIE_SOUTH_PCIE] = &qns_pcie_south_gem_noc_pcie,
>   };
>   
>   static const struct qcom_icc_desc x1e80100_pcie_south_anoc = {
> 

Re: [PATCH 1/4] interconnect: qcom: x1e80100: Remove bogus per-RSC BCMs and nodes

[Konrad Dybcio]

On 4.01.2024 10:59, Rajendra Nayak wrote:
> 
> 
> On 1/2/2024 11:59 PM, Konrad Dybcio wrote:
>> The downstream kernel has infrastructure for passing votes from different
>> interconnect nodes onto different RPMh RSCs. This neither implemented, not
>> is going to be implemented upstream (in favor of a different solution
>> using ICC tags through the same node).
>>
>> Unfortunately, as it happens, meaningless (in the upstream context) parts
>> of the vendor driver were copied, ending up causing havoc - since all
>> "per-RSC" (in quotes because they all point to the main APPS one) BCMs
>> defined within the driver overwrite the value in RPMh on every
>> aggregation.
>>
>> To both avoid keeping bogus code around and possibly introducing
>> impossible-to-track-down bugs (busses shutting down for no reason), get
>> rid of the duplicated BCMs and their associated ICC nodes.
> 
> Thanks Konrad for catching this, I do see these nodes in other Qualcomm SoCs upstream (atleast sm8350/sm8450 and sm8550), perhaps they need to be cleaned up as well?
Yes, I cleaned up 8550 last week, I'll look into the rest.

Konrad

Re: [PATCH 0/4] X Elite fixups

[Bjorn Andersson]

On Tue, 02 Jan 2024 19:29:46 +0100, Konrad Dybcio wrote:
> Just a couple of "usual" fixups that slipped through introduction
> reviews..
> 
> p1-2 for icc
> p3-4 for qcom
> 
> 
> [...]

Applied, thanks!

[1/4] interconnect: qcom: x1e80100: Remove bogus per-RSC BCMs and nodes
      (no commit info)
[2/4] dt-bindings: interconnect: Remove bogus interconnect nodes
      (no commit info)
[3/4] arm64: dts: qcom: x1e80100: Add missing system-wide PSCI power domain
      commit: f33767e3cfa5d40d751340dce05d316b3a151041
[4/4] arm64: dts: qcom: x1e80100: Flush RSC sleep & wake votes
      commit: 7d62dbd1b3b22ef73ed5a13f416ee21ee61c450b

Best regards,
-- 
Bjorn Andersson <andersson@kernel.org>