From: Tao Zhang <quic_taozha@quicinc.com>
To: Mathieu Poirier <mathieu.poirier@linaro.org>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
Konrad Dybcio <konradybcio@gmail.com>,
Mike Leach <mike.leach@linaro.org>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
Cc: Tao Zhang <quic_taozha@quicinc.com>,
Jinlong Mao <quic_jinlmao@quicinc.com>,
Leo Yan <leo.yan@linaro.org>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
<coresight@lists.linaro.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-kernel@vger.kernel.org>, <devicetree@vger.kernel.org>,
Tingwei Zhang <quic_tingweiz@quicinc.com>,
Yuanfang Zhang <quic_yuanfang@quicinc.com>,
Trilok Soni <quic_tsoni@quicinc.com>,
Song Chai <quic_songchai@quicinc.com>,
<linux-arm-msm@vger.kernel.org>, <andersson@kernel.org>
Subject: [PATCH v5 04/10] coresight-tpdm: Add CMB dataset support
Date: Tue, 30 Jan 2024 17:02:40 +0800 [thread overview]
Message-ID: <1706605366-31705-5-git-send-email-quic_taozha@quicinc.com> (raw)
In-Reply-To: <1706605366-31705-1-git-send-email-quic_taozha@quicinc.com>
CMB (continuous multi-bit) is one of TPDM's dataset type. CMB subunit
can be enabled for data collection by writing 1 to the first bit of
CMB_CR register. This change is to add enable/disable function for
CMB dataset by writing CMB_CR register.
Reviewed-by: James Clark <james.clark@arm.com>
Signed-off-by: Tao Zhang <quic_taozha@quicinc.com>
Signed-off-by: Jinlong Mao <quic_jinlmao@quicinc.com>
---
drivers/hwtracing/coresight/coresight-tpdm.c | 28 ++++++++++++++++++++
drivers/hwtracing/coresight/coresight-tpdm.h | 13 +++++++++
2 files changed, 41 insertions(+)
diff --git a/drivers/hwtracing/coresight/coresight-tpdm.c b/drivers/hwtracing/coresight/coresight-tpdm.c
index 4b1296d11360..1bb1d8e83501 100644
--- a/drivers/hwtracing/coresight/coresight-tpdm.c
+++ b/drivers/hwtracing/coresight/coresight-tpdm.c
@@ -263,6 +263,19 @@ static void tpdm_enable_dsb(struct tpdm_drvdata *drvdata)
writel_relaxed(val, drvdata->base + TPDM_DSB_CR);
}
+static void tpdm_enable_cmb(struct tpdm_drvdata *drvdata)
+{
+ u32 val;
+
+ if (!tpdm_has_cmb_dataset(drvdata))
+ return;
+
+ val = readl_relaxed(drvdata->base + TPDM_CMB_CR);
+ /* Set the enable bit of CMB control register to 1 */
+ val |= TPDM_CMB_CR_ENA;
+ writel_relaxed(val, drvdata->base + TPDM_CMB_CR);
+}
+
/*
* TPDM enable operations
* The TPDM or Monitor serves as data collection component for various
@@ -276,6 +289,7 @@ static void __tpdm_enable(struct tpdm_drvdata *drvdata)
CS_UNLOCK(drvdata->base);
tpdm_enable_dsb(drvdata);
+ tpdm_enable_cmb(drvdata);
CS_LOCK(drvdata->base);
}
@@ -312,12 +326,26 @@ static void tpdm_disable_dsb(struct tpdm_drvdata *drvdata)
writel_relaxed(val, drvdata->base + TPDM_DSB_CR);
}
+static void tpdm_disable_cmb(struct tpdm_drvdata *drvdata)
+{
+ u32 val;
+
+ if (!tpdm_has_cmb_dataset(drvdata))
+ return;
+
+ val = readl_relaxed(drvdata->base + TPDM_CMB_CR);
+ /* Set the enable bit of CMB control register to 0 */
+ val &= ~TPDM_CMB_CR_ENA;
+ writel_relaxed(val, drvdata->base + TPDM_CMB_CR);
+}
+
/* TPDM disable operations */
static void __tpdm_disable(struct tpdm_drvdata *drvdata)
{
CS_UNLOCK(drvdata->base);
tpdm_disable_dsb(drvdata);
+ tpdm_disable_cmb(drvdata);
CS_LOCK(drvdata->base);
}
diff --git a/drivers/hwtracing/coresight/coresight-tpdm.h b/drivers/hwtracing/coresight/coresight-tpdm.h
index ddaf333fa1c2..a442d9c6e4ac 100644
--- a/drivers/hwtracing/coresight/coresight-tpdm.h
+++ b/drivers/hwtracing/coresight/coresight-tpdm.h
@@ -9,6 +9,12 @@
/* The max number of the datasets that TPDM supports */
#define TPDM_DATASETS 7
+/* CMB Subunit Registers */
+#define TPDM_CMB_CR (0xA00)
+
+/* Enable bit for CMB subunit */
+#define TPDM_CMB_CR_ENA BIT(0)
+
/* DSB Subunit Registers */
#define TPDM_DSB_CR (0x780)
#define TPDM_DSB_TIER (0x784)
@@ -79,10 +85,12 @@
*
* PERIPHIDR0[0] : Fix to 1 if ImplDef subunit present, else 0
* PERIPHIDR0[1] : Fix to 1 if DSB subunit present, else 0
+ * PERIPHIDR0[2] : Fix to 1 if CMB subunit present, else 0
*/
#define TPDM_PIDR0_DS_IMPDEF BIT(0)
#define TPDM_PIDR0_DS_DSB BIT(1)
+#define TPDM_PIDR0_DS_CMB BIT(2)
#define TPDM_DSB_MAX_LINES 256
/* MAX number of EDCR registers */
@@ -224,4 +232,9 @@ static bool tpdm_has_dsb_dataset(struct tpdm_drvdata *drvdata)
{
return (drvdata->datasets & TPDM_PIDR0_DS_DSB);
}
+
+static bool tpdm_has_cmb_dataset(struct tpdm_drvdata *drvdata)
+{
+ return (drvdata->datasets & TPDM_PIDR0_DS_CMB);
+}
#endif /* _CORESIGHT_CORESIGHT_TPDM_H */
--
2.17.1
next prev parent reply other threads:[~2024-01-30 9:03 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-01-30 9:02 [PATCH v5 00/10] Add support to configure TPDM CMB subunit Tao Zhang
2024-01-30 9:02 ` [PATCH v5 01/10] coresight-tpdm: Optimize the store function of tpdm simple dataset Tao Zhang
2024-01-30 9:02 ` [PATCH v5 02/10] coresight-tpdm: Optimize the useage of tpdm_has_dsb_dataset Tao Zhang
2024-01-30 9:02 ` [PATCH v5 03/10] dt-bindings: arm: qcom,coresight-tpdm: Add support for CMB element size Tao Zhang
2024-01-31 7:42 ` Krzysztof Kozlowski
2024-01-30 9:02 ` Tao Zhang [this message]
2024-01-30 9:02 ` [PATCH v5 05/10] coresight-tpda: Add support to configure CMB element Tao Zhang
2024-01-30 12:35 ` Suzuki K Poulose
2024-01-31 1:39 ` Tao Zhang
2024-01-31 10:02 ` Suzuki K Poulose
2024-02-01 2:25 ` Tao Zhang
2024-02-01 10:26 ` Suzuki K Poulose
2024-01-30 9:02 ` [PATCH v5 06/10] coresight-tpdm: Add support to configure CMB Tao Zhang
2024-01-30 9:02 ` [PATCH v5 07/10] coresight-tpdm: Add pattern registers support for CMB Tao Zhang
2024-01-30 12:40 ` Suzuki K Poulose
2024-01-31 1:12 ` Tao Zhang
2024-01-30 9:02 ` [PATCH v5 08/10] coresight-tpdm: Add timestamp control register support for the CMB Tao Zhang
2024-01-30 12:42 ` Suzuki K Poulose
2024-01-31 1:12 ` Tao Zhang
2024-01-30 9:02 ` [PATCH v5 09/10] dt-bindings: arm: qcom,coresight-tpdm: Add support for TPDM CMB MSR register Tao Zhang
2024-01-30 9:02 ` [PATCH v5 10/10] coresight-tpdm: Add msr register support for CMB Tao Zhang
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