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From: Tao Zhang <quic_taozha@quicinc.com>
To: Suzuki K Poulose <suzuki.poulose@arm.com>,
	Mathieu Poirier <mathieu.poirier@linaro.org>,
	Alexander Shishkin <alexander.shishkin@linux.intel.com>,
	Konrad Dybcio <konradybcio@gmail.com>,
	Mike Leach <mike.leach@linaro.org>,
	Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
Cc: Jinlong Mao <quic_jinlmao@quicinc.com>,
	Leo Yan <leo.yan@linaro.org>,
	"Greg Kroah-Hartman" <gregkh@linuxfoundation.org>,
	<coresight@lists.linaro.org>,
	<linux-arm-kernel@lists.infradead.org>,
	<linux-kernel@vger.kernel.org>, <devicetree@vger.kernel.org>,
	Tingwei Zhang <quic_tingweiz@quicinc.com>,
	Yuanfang Zhang <quic_yuanfang@quicinc.com>,
	Trilok Soni <quic_tsoni@quicinc.com>,
	Song Chai <quic_songchai@quicinc.com>,
	<linux-arm-msm@vger.kernel.org>, <andersson@kernel.org>
Subject: Re: [PATCH v5 05/10] coresight-tpda: Add support to configure CMB element
Date: Wed, 31 Jan 2024 09:39:47 +0800	[thread overview]
Message-ID: <6fff5991-01ed-44ea-aa08-9f302d2465e8@quicinc.com> (raw)
In-Reply-To: <6ccb98f2-2f68-45db-9941-1c7b05da84d0@arm.com>


On 1/30/2024 8:35 PM, Suzuki K Poulose wrote:
> On 30/01/2024 09:02, Tao Zhang wrote:
>> Read the CMB element size from the device tree. Set the register
>> bit that controls the CMB element size of the corresponding port.
>>
>> Reviewed-by: James Clark <james.clark@arm.com>
>> Signed-off-by: Tao Zhang <quic_taozha@quicinc.com>
>> Signed-off-by: Mao Jinlong <quic_jinlmao@quicinc.com>
>> ---
>>   drivers/hwtracing/coresight/coresight-tpda.c | 123 +++++++++++--------
>>   drivers/hwtracing/coresight/coresight-tpda.h |   6 +
>>   2 files changed, 79 insertions(+), 50 deletions(-)
>>
>> diff --git a/drivers/hwtracing/coresight/coresight-tpda.c 
>> b/drivers/hwtracing/coresight/coresight-tpda.c
>> index 4ac954f4bc13..fcddff3ded81 100644
>> --- a/drivers/hwtracing/coresight/coresight-tpda.c
>> +++ b/drivers/hwtracing/coresight/coresight-tpda.c
>> @@ -18,6 +18,7 @@
>>   #include "coresight-priv.h"
>>   #include "coresight-tpda.h"
>>   #include "coresight-trace-id.h"
>> +#include "coresight-tpdm.h"
>>     DEFINE_CORESIGHT_DEVLIST(tpda_devs, "tpda");
>>   @@ -28,24 +29,57 @@ static bool coresight_device_is_tpdm(struct 
>> coresight_device *csdev)
>>               CORESIGHT_DEV_SUBTYPE_SOURCE_TPDM);
>>   }
>>   +static void tpdm_clear_element_size(struct coresight_device *csdev)
>> +{
>> +    struct tpda_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
>> +
>> +    drvdata->dsb_esize = 0;
>> +    drvdata->cmb_esize = 0;
>> +}
>> +
>> +static void tpda_set_element_size(struct tpda_drvdata *drvdata, u32 
>> *val)
>> +{
>> +
>
>
>
>> +    if (drvdata->dsb_esize == 64)
>> +        *val |= TPDA_Pn_CR_DSBSIZE;
>
> We don't seem to be clearing the fields we modify, before updating 
> them. This may be OK in real world where the device connected to TPDA 
> port
> may not change. But it is always safer to clear the bits and set it.
>
> e.g.:
>     *val &= ~(TPDA_Pn_CR_DSBSIZE | TPDA_Pn_CR_CMBSIZE);
>
>
>
>> +    else if (drvdata->dsb_esize == 32)
>> +        *val &= ~TPDA_Pn_CR_DSBSIZE;
>> +
>> +    if (drvdata->cmb_esize == 64)
>> +        *val |= FIELD_PREP(TPDA_Pn_CR_CMBSIZE, 0x2);
>> +    else if (drvdata->cmb_esize == 32)
>> +        *val |= FIELD_PREP(TPDA_Pn_CR_CMBSIZE, 0x1);
>
> Similarly here ^^^. I am happy to fix it up if you are OK with it 
> (unless there are other changes that need a respin)

Thank you. I would be very grateful if you could help for this.


Best,

Tao

>
>> +    else if (drvdata->cmb_esize == 8)
>> +        *val &= ~TPDA_Pn_CR_CMBSIZE;
>> +}
>
>> +
>>   /*
>> - * Read the DSB element size from the TPDM device
>> + * Read the element size from the TPDM device. One TPDM must have at 
>> least one of the
>> + * element size property.
>>    * Returns
>> - *    The dsb element size read from the devicetree if available.
>> - *    0 - Otherwise, with a warning once.
>> + *    0 - The element size property is read
>> + *    Others - Cannot read the property of the element size
>>    */
>> -static int tpdm_read_dsb_element_size(struct coresight_device *csdev)
>> +static int tpdm_read_element_size(struct tpda_drvdata *drvdata,
>> +                  struct coresight_device *csdev)
>>   {
>> -    int rc = 0;
>> -    u8 size = 0;
>> +    int rc = -EINVAL;
>> +    struct tpdm_drvdata *tpdm_data = 
>> dev_get_drvdata(csdev->dev.parent);
>> +
>> +    if (tpdm_has_dsb_dataset(tpdm_data)) {
>> +        rc = fwnode_property_read_u8(dev_fwnode(csdev->dev.parent),
>> +                "qcom,dsb-element-size", &drvdata->dsb_esize);
>> +    }
>> +    if (tpdm_has_cmb_dataset(tpdm_data)) {
>> +        rc = fwnode_property_read_u32(dev_fwnode(csdev->dev.parent),
>> +                "qcom,cmb-element-bits", &drvdata->cmb_esize);
>> +    }
>>   -    rc = fwnode_property_read_u8(dev_fwnode(csdev->dev.parent),
>> -            "qcom,dsb-element-size", &size);
>>       if (rc)
>>           dev_warn_once(&csdev->dev,
>> -            "Failed to read TPDM DSB Element size: %d\n", rc);
>> +            "Failed to read TPDM Element size: %d\n", rc);
>>   -    return size;
>> +    return rc;
>>   }
>>     /*
>> @@ -56,11 +90,12 @@ static int tpdm_read_dsb_element_size(struct 
>> coresight_device *csdev)
>>    * Parameter "inport" is used to pass in the input port number
>>    * of TPDA, and it is set to -1 in the recursize call.
>>    */
>> -static int tpda_get_element_size(struct coresight_device *csdev,
>> +static int tpda_get_element_size(struct tpda_drvdata *drvdata,
>> +                 struct coresight_device *csdev,
>>                    int inport)
>>   {
>> -    int dsb_size = -ENOENT;
>> -    int i, size;
>> +    int rc = 0;
>> +    int i;
>>       struct coresight_device *in;
>>         for (i = 0; i < csdev->pdata->nr_inconns; i++) {
>> @@ -69,30 +104,26 @@ static int tpda_get_element_size(struct 
>> coresight_device *csdev,
>>               continue;
>>             /* Ignore the paths that do not match port */
>> -        if (inport > 0 &&
>> +        if (inport >= 0 &&
>
> That looks like a bug fix, but if you don't care about fixing this in 
> < v6.8,  I don't mind.
>
>
> Rest looks fine to me
>
> Suzuki
>

  reply	other threads:[~2024-01-31  1:40 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-01-30  9:02 [PATCH v5 00/10] Add support to configure TPDM CMB subunit Tao Zhang
2024-01-30  9:02 ` [PATCH v5 01/10] coresight-tpdm: Optimize the store function of tpdm simple dataset Tao Zhang
2024-01-30  9:02 ` [PATCH v5 02/10] coresight-tpdm: Optimize the useage of tpdm_has_dsb_dataset Tao Zhang
2024-01-30  9:02 ` [PATCH v5 03/10] dt-bindings: arm: qcom,coresight-tpdm: Add support for CMB element size Tao Zhang
2024-01-31  7:42   ` Krzysztof Kozlowski
2024-01-30  9:02 ` [PATCH v5 04/10] coresight-tpdm: Add CMB dataset support Tao Zhang
2024-01-30  9:02 ` [PATCH v5 05/10] coresight-tpda: Add support to configure CMB element Tao Zhang
2024-01-30 12:35   ` Suzuki K Poulose
2024-01-31  1:39     ` Tao Zhang [this message]
2024-01-31 10:02       ` Suzuki K Poulose
2024-02-01  2:25         ` Tao Zhang
2024-02-01 10:26           ` Suzuki K Poulose
2024-01-30  9:02 ` [PATCH v5 06/10] coresight-tpdm: Add support to configure CMB Tao Zhang
2024-01-30  9:02 ` [PATCH v5 07/10] coresight-tpdm: Add pattern registers support for CMB Tao Zhang
2024-01-30 12:40   ` Suzuki K Poulose
2024-01-31  1:12     ` Tao Zhang
2024-01-30  9:02 ` [PATCH v5 08/10] coresight-tpdm: Add timestamp control register support for the CMB Tao Zhang
2024-01-30 12:42   ` Suzuki K Poulose
2024-01-31  1:12     ` Tao Zhang
2024-01-30  9:02 ` [PATCH v5 09/10] dt-bindings: arm: qcom,coresight-tpdm: Add support for TPDM CMB MSR register Tao Zhang
2024-01-30  9:02 ` [PATCH v5 10/10] coresight-tpdm: Add msr register support for CMB Tao Zhang

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