* [PATCH] clk: rk3399: Allow to set rate of clk_i2s0_frac's parent
@ 2024-02-17 19:34 Ondřej Jirman
2024-02-27 23:13 ` Heiko Stuebner
0 siblings, 1 reply; 2+ messages in thread
From: Ondřej Jirman @ 2024-02-17 19:34 UTC (permalink / raw)
To: linux-kernel
Cc: Ondrej Jirman, Michael Turquette, Stephen Boyd, Heiko Stuebner,
open list:COMMON CLK FRAMEWORK,
moderated list:ARM/Rockchip SoC support,
open list:ARM/Rockchip SoC support
From: Ondrej Jirman <megi@xff.cz>
Otherwise when when clk_i2s0 muxes to clk_i2s0_div which requires
setting high divider value on clk_i2s0_div, and then muxes back to
clk_i2s0_frac, clk_i2s0_frac would have no way to change the
clk_i2s0_div's divider ratio back to 1 so that it can satisfy the
condition for m/n > 20 for fractional division to work correctly.
Bug is reproducible by playing 44.1k audio, then 48k audio, and then
44.1k audio again. This results in clk_i2s0_div being set to 49 and
clk_i2s0_frac not being able to cope with such a low input clock rate
and audio playing extremely slowly.
The identical issue is on i2s1 and i2s2 clocks, too.
Signed-off-by: Ondrej Jirman <megi@xff.cz>
---
drivers/clk/rockchip/clk-rk3399.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c
index 5efac2ca3048..a17996acd065 100644
--- a/drivers/clk/rockchip/clk-rk3399.c
+++ b/drivers/clk/rockchip/clk-rk3399.c
@@ -597,7 +597,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
COMPOSITE(0, "clk_i2s0_div", mux_pll_src_cpll_gpll_p, 0,
RK3399_CLKSEL_CON(28), 7, 1, MFLAGS, 0, 7, DFLAGS,
RK3399_CLKGATE_CON(8), 3, GFLAGS),
- COMPOSITE_FRACMUX(0, "clk_i2s0_frac", "clk_i2s0_div", 0,
+ COMPOSITE_FRACMUX(0, "clk_i2s0_frac", "clk_i2s0_div", CLK_SET_RATE_PARENT,
RK3399_CLKSEL_CON(96), 0,
RK3399_CLKGATE_CON(8), 4, GFLAGS,
&rk3399_i2s0_fracmux),
@@ -607,7 +607,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
COMPOSITE(0, "clk_i2s1_div", mux_pll_src_cpll_gpll_p, 0,
RK3399_CLKSEL_CON(29), 7, 1, MFLAGS, 0, 7, DFLAGS,
RK3399_CLKGATE_CON(8), 6, GFLAGS),
- COMPOSITE_FRACMUX(0, "clk_i2s1_frac", "clk_i2s1_div", 0,
+ COMPOSITE_FRACMUX(0, "clk_i2s1_frac", "clk_i2s1_div", CLK_SET_RATE_PARENT,
RK3399_CLKSEL_CON(97), 0,
RK3399_CLKGATE_CON(8), 7, GFLAGS,
&rk3399_i2s1_fracmux),
@@ -617,7 +617,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
COMPOSITE(0, "clk_i2s2_div", mux_pll_src_cpll_gpll_p, 0,
RK3399_CLKSEL_CON(30), 7, 1, MFLAGS, 0, 7, DFLAGS,
RK3399_CLKGATE_CON(8), 9, GFLAGS),
- COMPOSITE_FRACMUX(0, "clk_i2s2_frac", "clk_i2s2_div", 0,
+ COMPOSITE_FRACMUX(0, "clk_i2s2_frac", "clk_i2s2_div", CLK_SET_RATE_PARENT,
RK3399_CLKSEL_CON(98), 0,
RK3399_CLKGATE_CON(8), 10, GFLAGS,
&rk3399_i2s2_fracmux),
--
2.43.0
^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [PATCH] clk: rk3399: Allow to set rate of clk_i2s0_frac's parent
2024-02-17 19:34 [PATCH] clk: rk3399: Allow to set rate of clk_i2s0_frac's parent Ondřej Jirman
@ 2024-02-27 23:13 ` Heiko Stuebner
0 siblings, 0 replies; 2+ messages in thread
From: Heiko Stuebner @ 2024-02-27 23:13 UTC (permalink / raw)
To: linux-kernel, Ondřej Jirman
Cc: Heiko Stuebner, open list:COMMON CLK FRAMEWORK, Stephen Boyd,
moderated list:ARM/Rockchip SoC support, Michael Turquette,
open list:ARM/Rockchip SoC support
On Sat, 17 Feb 2024 20:34:38 +0100, Ondřej Jirman wrote:
> From: Ondrej Jirman <megi@xff.cz>
>
> Otherwise when when clk_i2s0 muxes to clk_i2s0_div which requires
> setting high divider value on clk_i2s0_div, and then muxes back to
> clk_i2s0_frac, clk_i2s0_frac would have no way to change the
> clk_i2s0_div's divider ratio back to 1 so that it can satisfy the
> condition for m/n > 20 for fractional division to work correctly.
>
> [...]
Applied, thanks!
[1/1] clk: rk3399: Allow to set rate of clk_i2s0_frac's parent
commit: 1361d75503fccc0e6b3ecbcd5bb53bbdfdc52f0a
Best regards,
--
Heiko Stuebner <heiko@sntech.de>
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