* [PATCH v3 01/10] Use IDR to maintain all the enabled sources' paths.
2022-02-09 10:56 [PATCH v3 00/10] Coresight: Add support for TPDM and TPDA Mao Jinlong
@ 2022-02-09 10:56 ` Mao Jinlong
2022-02-09 15:34 ` Mike Leach
2022-02-09 10:56 ` [PATCH v3 02/10] coresight: Use bitmap to assign trace id to the sources Mao Jinlong
` (9 subsequent siblings)
10 siblings, 1 reply; 22+ messages in thread
From: Mao Jinlong @ 2022-02-09 10:56 UTC (permalink / raw)
To: Mathieu Poirier, Suzuki K Poulose, Alexander Shishkin
Cc: Mao Jinlong, Mike Leach, Leo Yan, Greg Kroah-Hartman, coresight,
linux-arm-kernel, linux-kernel, Tingwei Zhang, Yuanfang Zhang,
Tao Zhang, Trilok Soni, Hao Zhang, linux-arm-msm
Use hash length of the source's device name to map to the pointer
of the enabled path. Using IDR will be more efficient than using
the list. And there could be other sources except STM and CPU etms
in the new HWs. It is better to maintain all the paths together.
Signed-off-by: Mao Jinlong <quic_jinlmao@quicinc.com>
---
drivers/hwtracing/coresight/coresight-core.c | 76 +++++++-------------
1 file changed, 27 insertions(+), 49 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtracing/coresight/coresight-core.c
index 88653d1c06a4..a90097f88425 100644
--- a/drivers/hwtracing/coresight/coresight-core.c
+++ b/drivers/hwtracing/coresight/coresight-core.c
@@ -7,6 +7,7 @@
#include <linux/init.h>
#include <linux/types.h>
#include <linux/device.h>
+#include <linux/idr.h>
#include <linux/io.h>
#include <linux/err.h>
#include <linux/export.h>
@@ -26,6 +27,12 @@
static DEFINE_MUTEX(coresight_mutex);
static DEFINE_PER_CPU(struct coresight_device *, csdev_sink);
+/*
+ * Use IDR to map the hash length of the source's device name
+ * to the pointer of path for the source
+ */
+static DEFINE_IDR(path_idr);
+
/**
* struct coresight_node - elements of a path, from source to sink
* @csdev: Address of an element.
@@ -36,20 +43,6 @@ struct coresight_node {
struct list_head link;
};
-/*
- * When operating Coresight drivers from the sysFS interface, only a single
- * path can exist from a tracer (associated to a CPU) to a sink.
- */
-static DEFINE_PER_CPU(struct list_head *, tracer_path);
-
-/*
- * As of this writing only a single STM can be found in CS topologies. Since
- * there is no way to know if we'll ever see more and what kind of
- * configuration they will enact, for the time being only define a single path
- * for STM.
- */
-static struct list_head *stm_path;
-
/*
* When losing synchronisation a new barrier packet needs to be inserted at the
* beginning of the data collected in a buffer. That way the decoder knows that
@@ -1088,10 +1081,11 @@ static int coresight_validate_source(struct coresight_device *csdev,
int coresight_enable(struct coresight_device *csdev)
{
- int cpu, ret = 0;
+ int ret = 0;
struct coresight_device *sink;
struct list_head *path;
enum coresight_dev_subtype_source subtype;
+ u32 hash;
subtype = csdev->subtype.source_subtype;
@@ -1133,26 +1127,14 @@ int coresight_enable(struct coresight_device *csdev)
if (ret)
goto err_source;
- switch (subtype) {
- case CORESIGHT_DEV_SUBTYPE_SOURCE_PROC:
- /*
- * When working from sysFS it is important to keep track
- * of the paths that were created so that they can be
- * undone in 'coresight_disable()'. Since there can only
- * be a single session per tracer (when working from sysFS)
- * a per-cpu variable will do just fine.
- */
- cpu = source_ops(csdev)->cpu_id(csdev);
- per_cpu(tracer_path, cpu) = path;
- break;
- case CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE:
- stm_path = path;
- break;
- default:
- /* We can't be here */
- break;
- }
-
+ /*
+ * Use the hash length of source's device name as ID
+ * and map the ID to the pointer of the path.
+ */
+ hash = hashlen_hash(hashlen_string(NULL, dev_name(&csdev->dev)));
+ ret = idr_alloc_u32(&path_idr, path, &hash, hash, GFP_KERNEL);
+ if (ret)
+ goto err_source;
out:
mutex_unlock(&coresight_mutex);
return ret;
@@ -1168,8 +1150,9 @@ EXPORT_SYMBOL_GPL(coresight_enable);
void coresight_disable(struct coresight_device *csdev)
{
- int cpu, ret;
+ int ret;
struct list_head *path = NULL;
+ u32 hash;
mutex_lock(&coresight_mutex);
@@ -1180,21 +1163,16 @@ void coresight_disable(struct coresight_device *csdev)
if (!csdev->enable || !coresight_disable_source(csdev))
goto out;
- switch (csdev->subtype.source_subtype) {
- case CORESIGHT_DEV_SUBTYPE_SOURCE_PROC:
- cpu = source_ops(csdev)->cpu_id(csdev);
- path = per_cpu(tracer_path, cpu);
- per_cpu(tracer_path, cpu) = NULL;
- break;
- case CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE:
- path = stm_path;
- stm_path = NULL;
- break;
- default:
- /* We can't be here */
- break;
+ hash = hashlen_hash(hashlen_string(NULL, dev_name(&csdev->dev)));
+ /* Find the path by the hash length. */
+ path = idr_find(&path_idr, hash);
+ if (path == NULL) {
+ dev_info(&csdev->dev, "Path is not found for %s\n",
+ dev_name(&csdev->dev));
+ return;
}
+ idr_remove(&path_idr, hash);
coresight_disable_path(path);
coresight_release_path(path);
--
2.17.1
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH v3 01/10] Use IDR to maintain all the enabled sources' paths.
2022-02-09 10:56 ` [PATCH v3 01/10] Use IDR to maintain all the enabled sources' paths Mao Jinlong
@ 2022-02-09 15:34 ` Mike Leach
0 siblings, 0 replies; 22+ messages in thread
From: Mike Leach @ 2022-02-09 15:34 UTC (permalink / raw)
To: Mao Jinlong
Cc: Mathieu Poirier, Suzuki K Poulose, Alexander Shishkin, Leo Yan,
Greg Kroah-Hartman, coresight, linux-arm-kernel, linux-kernel,
Tingwei Zhang, Yuanfang Zhang, Tao Zhang, Trilok Soni, Hao Zhang,
linux-arm-msm
Hi,
On Wed, 9 Feb 2022 at 10:57, Mao Jinlong <quic_jinlmao@quicinc.com> wrote:
>
> Use hash length of the source's device name to map to the pointer
> of the enabled path. Using IDR will be more efficient than using
> the list. And there could be other sources except STM and CPU etms
> in the new HWs. It is better to maintain all the paths together.
>
> Signed-off-by: Mao Jinlong <quic_jinlmao@quicinc.com>
> ---
> drivers/hwtracing/coresight/coresight-core.c | 76 +++++++-------------
> 1 file changed, 27 insertions(+), 49 deletions(-)
>
> diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtracing/coresight/coresight-core.c
> index 88653d1c06a4..a90097f88425 100644
> --- a/drivers/hwtracing/coresight/coresight-core.c
> +++ b/drivers/hwtracing/coresight/coresight-core.c
> @@ -7,6 +7,7 @@
> #include <linux/init.h>
> #include <linux/types.h>
> #include <linux/device.h>
> +#include <linux/idr.h>
> #include <linux/io.h>
> #include <linux/err.h>
> #include <linux/export.h>
> @@ -26,6 +27,12 @@
> static DEFINE_MUTEX(coresight_mutex);
> static DEFINE_PER_CPU(struct coresight_device *, csdev_sink);
>
> +/*
> + * Use IDR to map the hash length of the source's device name
> + * to the pointer of path for the source
> + */
> +static DEFINE_IDR(path_idr);
> +
> /**
> * struct coresight_node - elements of a path, from source to sink
> * @csdev: Address of an element.
> @@ -36,20 +43,6 @@ struct coresight_node {
> struct list_head link;
> };
>
> -/*
> - * When operating Coresight drivers from the sysFS interface, only a single
> - * path can exist from a tracer (associated to a CPU) to a sink.
> - */
> -static DEFINE_PER_CPU(struct list_head *, tracer_path);
> -
> -/*
> - * As of this writing only a single STM can be found in CS topologies. Since
> - * there is no way to know if we'll ever see more and what kind of
> - * configuration they will enact, for the time being only define a single path
> - * for STM.
> - */
> -static struct list_head *stm_path;
> -
> /*
> * When losing synchronisation a new barrier packet needs to be inserted at the
> * beginning of the data collected in a buffer. That way the decoder knows that
> @@ -1088,10 +1081,11 @@ static int coresight_validate_source(struct coresight_device *csdev,
>
> int coresight_enable(struct coresight_device *csdev)
> {
> - int cpu, ret = 0;
> + int ret = 0;
> struct coresight_device *sink;
> struct list_head *path;
> enum coresight_dev_subtype_source subtype;
> + u32 hash;
>
> subtype = csdev->subtype.source_subtype;
>
> @@ -1133,26 +1127,14 @@ int coresight_enable(struct coresight_device *csdev)
> if (ret)
> goto err_source;
>
> - switch (subtype) {
> - case CORESIGHT_DEV_SUBTYPE_SOURCE_PROC:
> - /*
> - * When working from sysFS it is important to keep track
> - * of the paths that were created so that they can be
> - * undone in 'coresight_disable()'. Since there can only
> - * be a single session per tracer (when working from sysFS)
> - * a per-cpu variable will do just fine.
> - */
> - cpu = source_ops(csdev)->cpu_id(csdev);
> - per_cpu(tracer_path, cpu) = path;
> - break;
> - case CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE:
> - stm_path = path;
> - break;
> - default:
> - /* We can't be here */
> - break;
> - }
> -
> + /*
> + * Use the hash length of source's device name as ID
Slightly confusing comment:
hashlen_string creates a hash and a length for the string. We are
using the hash here so comment should be:
"Use the hash of source's device name as ID"
> + * and map the ID to the pointer of the path.
> + */
> + hash = hashlen_hash(hashlen_string(NULL, dev_name(&csdev->dev)));
> + ret = idr_alloc_u32(&path_idr, path, &hash, hash, GFP_KERNEL);
> + if (ret)
> + goto err_source;
> out:
> mutex_unlock(&coresight_mutex);
> return ret;
> @@ -1168,8 +1150,9 @@ EXPORT_SYMBOL_GPL(coresight_enable);
>
> void coresight_disable(struct coresight_device *csdev)
> {
> - int cpu, ret;
> + int ret;
> struct list_head *path = NULL;
> + u32 hash;
>
> mutex_lock(&coresight_mutex);
>
> @@ -1180,21 +1163,16 @@ void coresight_disable(struct coresight_device *csdev)
> if (!csdev->enable || !coresight_disable_source(csdev))
> goto out;
>
> - switch (csdev->subtype.source_subtype) {
> - case CORESIGHT_DEV_SUBTYPE_SOURCE_PROC:
> - cpu = source_ops(csdev)->cpu_id(csdev);
> - path = per_cpu(tracer_path, cpu);
> - per_cpu(tracer_path, cpu) = NULL;
> - break;
> - case CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE:
> - path = stm_path;
> - stm_path = NULL;
> - break;
> - default:
> - /* We can't be here */
> - break;
> + hash = hashlen_hash(hashlen_string(NULL, dev_name(&csdev->dev)));
> + /* Find the path by the hash length. */
same comment as above re hash / hash length
> + path = idr_find(&path_idr, hash);
> + if (path == NULL) {
> + dev_info(&csdev->dev, "Path is not found for %s\n",
> + dev_name(&csdev->dev));
pr_err() is used in other parts of this file to print error messages.
> + return;
this skips the mutex_unlock(). use goto out;
> }
>
> + idr_remove(&path_idr, hash);
> coresight_disable_path(path);
> coresight_release_path(path);
>
> --
> 2.17.1
>
Regards
Mike
--
Mike Leach
Principal Engineer, ARM Ltd.
Manchester Design Centre. UK
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH v3 02/10] coresight: Use bitmap to assign trace id to the sources
2022-02-09 10:56 [PATCH v3 00/10] Coresight: Add support for TPDM and TPDA Mao Jinlong
2022-02-09 10:56 ` [PATCH v3 01/10] Use IDR to maintain all the enabled sources' paths Mao Jinlong
@ 2022-02-09 10:56 ` Mao Jinlong
2022-02-17 17:35 ` Mike Leach
2022-02-09 10:56 ` [PATCH v3 03/10] Coresight: Add coresight TPDM source driver Mao Jinlong
` (8 subsequent siblings)
10 siblings, 1 reply; 22+ messages in thread
From: Mao Jinlong @ 2022-02-09 10:56 UTC (permalink / raw)
To: Mathieu Poirier, Suzuki K Poulose, Alexander Shishkin
Cc: Mao Jinlong, Mike Leach, Leo Yan, Greg Kroah-Hartman, coresight,
linux-arm-kernel, linux-kernel, Tingwei Zhang, Yuanfang Zhang,
Tao Zhang, Trilok Soni, Hao Zhang, linux-arm-msm
Except from STM and ETM/ETE, there could be other sources. Each
source needs a unique trace id. Define a bitmap for the trace ids.
The position of each bit represents trace id of the source.
Signed-off-by: Mao Jinlong <quic_jinlmao@quicinc.com>
---
drivers/hwtracing/coresight/coresight-core.c | 48 ++++++++++++++++++++
include/linux/coresight-pmu.h | 11 +++++
2 files changed, 59 insertions(+)
diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtracing/coresight/coresight-core.c
index a90097f88425..6cb55c3f41d5 100644
--- a/drivers/hwtracing/coresight/coresight-core.c
+++ b/drivers/hwtracing/coresight/coresight-core.c
@@ -16,6 +16,7 @@
#include <linux/mutex.h>
#include <linux/clk.h>
#include <linux/coresight.h>
+#include <linux/coresight-pmu.h>
#include <linux/of_platform.h>
#include <linux/delay.h>
#include <linux/pm_runtime.h>
@@ -25,8 +26,11 @@
#include "coresight-syscfg.h"
static DEFINE_MUTEX(coresight_mutex);
+static DEFINE_MUTEX(coresight_id_mutex);
static DEFINE_PER_CPU(struct coresight_device *, csdev_sink);
+static DECLARE_BITMAP(coresight_trace_id, CORESIGHT_TRACE_ID_NUM);
+
/*
* Use IDR to map the hash length of the source's device name
* to the pointer of path for the source
@@ -51,6 +55,48 @@ struct coresight_node {
const u32 coresight_barrier_pkt[4] = {0x7fffffff, 0x7fffffff, 0x7fffffff, 0x7fffffff};
EXPORT_SYMBOL_GPL(coresight_barrier_pkt);
+/* Init the coresight_trace_id bit map. */
+static void coresight_init_trace_id(void)
+{
+ int i;
+
+ /* Trace id 0 is invalid. */
+ set_bit(CORESIGHT_TRACE_ID_0, coresight_trace_id);
+ /* Trace id 1 is fixed for STM. */
+ set_bit(CORESIGHT_TRACE_ID_1, coresight_trace_id);
+ /* Trace id from 112 to 127 are reserved. */
+ for (i = CORESIGHT_TRACE_ID_112; i <= CORESIGHT_TRACE_ID_127; i++)
+ set_bit(i, coresight_trace_id);
+ /* Skip the trace ids of ETM/ETE. */
+ for (i = 0; i <= cpumask_last(cpu_possible_mask); i++)
+ set_bit(coresight_get_trace_id(i), coresight_trace_id);
+
+}
+
+/*
+ * Return the first zero bit position of bitmap coresight_trace_id
+ * as source's trace id.
+ *
+ */
+int coresight_get_system_trace_id(void)
+{
+ int id;
+
+ mutex_lock(&coresight_id_mutex);
+ id = find_first_zero_bit(coresight_trace_id, CORESIGHT_TRACE_ID_NUM);
+ /* If no zero bit is found, return error value. */
+ if (id == CORESIGHT_TRACE_ID_NUM) {
+ mutex_unlock(&coresight_id_mutex);
+ return -EINVAL;
+ }
+
+ set_bit(id, coresight_trace_id);
+ mutex_unlock(&coresight_id_mutex);
+
+ return id;
+}
+EXPORT_SYMBOL(coresight_get_system_trace_id);
+
static const struct cti_assoc_op *cti_assoc_ops;
void coresight_set_cti_ops(const struct cti_assoc_op *cti_op)
@@ -1750,6 +1796,8 @@ static int __init coresight_init(void)
return 0;
etm_perf_exit();
+
+ coresight_init_trace_id();
exit_bus_unregister:
bus_unregister(&coresight_bustype);
return ret;
diff --git a/include/linux/coresight-pmu.h b/include/linux/coresight-pmu.h
index 4ac5c081af93..1e2c5ca4c6e6 100644
--- a/include/linux/coresight-pmu.h
+++ b/include/linux/coresight-pmu.h
@@ -32,6 +32,14 @@
#define ETM4_CFG_BIT_RETSTK 12
#define ETM4_CFG_BIT_VMID_OPT 15
+/* Coresight component supports 7 bits trace id. */
+#define CORESIGHT_TRACE_ID_NUM 128
+
+#define CORESIGHT_TRACE_ID_0 0
+#define CORESIGHT_TRACE_ID_1 1
+#define CORESIGHT_TRACE_ID_112 112
+#define CORESIGHT_TRACE_ID_127 127
+
static inline int coresight_get_trace_id(int cpu)
{
/*
@@ -43,4 +51,7 @@ static inline int coresight_get_trace_id(int cpu)
return (CORESIGHT_ETM_PMU_SEED + (cpu * 2));
}
+/* Get the trace id for the sources except from STM, ETM/ETE. */
+extern int coresight_get_system_trace_id(void);
+
#endif
--
2.17.1
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH v3 02/10] coresight: Use bitmap to assign trace id to the sources
2022-02-09 10:56 ` [PATCH v3 02/10] coresight: Use bitmap to assign trace id to the sources Mao Jinlong
@ 2022-02-17 17:35 ` Mike Leach
0 siblings, 0 replies; 22+ messages in thread
From: Mike Leach @ 2022-02-17 17:35 UTC (permalink / raw)
To: Mao Jinlong
Cc: Mathieu Poirier, Suzuki K Poulose, Alexander Shishkin, Leo Yan,
Greg Kroah-Hartman, coresight, linux-arm-kernel, linux-kernel,
Tingwei Zhang, Yuanfang Zhang, Tao Zhang, Trilok Soni, Hao Zhang,
linux-arm-msm
Hi,
On Wed, 9 Feb 2022 at 10:57, Mao Jinlong <quic_jinlmao@quicinc.com> wrote:
>
> Except from STM and ETM/ETE, there could be other sources. Each
> source needs a unique trace id. Define a bitmap for the trace ids.
> The position of each bit represents trace id of the source.
>
> Signed-off-by: Mao Jinlong <quic_jinlmao@quicinc.com>
> ---
> drivers/hwtracing/coresight/coresight-core.c | 48 ++++++++++++++++++++
> include/linux/coresight-pmu.h | 11 +++++
> 2 files changed, 59 insertions(+)
>
> diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtracing/coresight/coresight-core.c
> index a90097f88425..6cb55c3f41d5 100644
> --- a/drivers/hwtracing/coresight/coresight-core.c
> +++ b/drivers/hwtracing/coresight/coresight-core.c
> @@ -16,6 +16,7 @@
> #include <linux/mutex.h>
> #include <linux/clk.h>
> #include <linux/coresight.h>
> +#include <linux/coresight-pmu.h>
see my comment below about using coresigh-priv.h
> #include <linux/of_platform.h>
> #include <linux/delay.h>
> #include <linux/pm_runtime.h>
> @@ -25,8 +26,11 @@
> #include "coresight-syscfg.h"
>
> static DEFINE_MUTEX(coresight_mutex);
> +static DEFINE_MUTEX(coresight_id_mutex);
> static DEFINE_PER_CPU(struct coresight_device *, csdev_sink);
>
> +static DECLARE_BITMAP(coresight_trace_id, CORESIGHT_TRACE_ID_NUM);
> +
> /*
> * Use IDR to map the hash length of the source's device name
> * to the pointer of path for the source
> @@ -51,6 +55,48 @@ struct coresight_node {
> const u32 coresight_barrier_pkt[4] = {0x7fffffff, 0x7fffffff, 0x7fffffff, 0x7fffffff};
> EXPORT_SYMBOL_GPL(coresight_barrier_pkt);
>
> +/* Init the coresight_trace_id bit map. */
> +static void coresight_init_trace_id(void)
> +{
> + int i;
> +
> + /* Trace id 0 is invalid. */
> + set_bit(CORESIGHT_TRACE_ID_0, coresight_trace_id);
> + /* Trace id 1 is fixed for STM. */
> + set_bit(CORESIGHT_TRACE_ID_1, coresight_trace_id);
> + /* Trace id from 112 to 127 are reserved. */
> + for (i = CORESIGHT_TRACE_ID_112; i <= CORESIGHT_TRACE_ID_127; i++)
> + set_bit(i, coresight_trace_id);
> + /* Skip the trace ids of ETM/ETE. */
> + for (i = 0; i <= cpumask_last(cpu_possible_mask); i++)
> + set_bit(coresight_get_trace_id(i), coresight_trace_id);
> +
> +}
> +
> +/*
> + * Return the first zero bit position of bitmap coresight_trace_id
> + * as source's trace id.
> + *
> + */
> +int coresight_get_system_trace_id(void)
> +{
> + int id;
> +
> + mutex_lock(&coresight_id_mutex);
> + id = find_first_zero_bit(coresight_trace_id, CORESIGHT_TRACE_ID_NUM);
> + /* If no zero bit is found, return error value. */
> + if (id == CORESIGHT_TRACE_ID_NUM) {
> + mutex_unlock(&coresight_id_mutex);
> + return -EINVAL;
> + }
> +
> + set_bit(id, coresight_trace_id);
> + mutex_unlock(&coresight_id_mutex);
> +
> + return id;
> +}
> +EXPORT_SYMBOL(coresight_get_system_trace_id);
> +
> static const struct cti_assoc_op *cti_assoc_ops;
>
> void coresight_set_cti_ops(const struct cti_assoc_op *cti_op)
> @@ -1750,6 +1796,8 @@ static int __init coresight_init(void)
> return 0;
>
> etm_perf_exit();
> +
> + coresight_init_trace_id();
> exit_bus_unregister:
> bus_unregister(&coresight_bustype);
> return ret;
> diff --git a/include/linux/coresight-pmu.h b/include/linux/coresight-pmu.h
> index 4ac5c081af93..1e2c5ca4c6e6 100644
> --- a/include/linux/coresight-pmu.h
> +++ b/include/linux/coresight-pmu.h
> @@ -32,6 +32,14 @@
> #define ETM4_CFG_BIT_RETSTK 12
> #define ETM4_CFG_BIT_VMID_OPT 15
>
The following additional defines and function should appear in coresight-priv.h
The coresight-pmu.h file contains data for the interface between the
drivers and perf.
> +/* Coresight component supports 7 bits trace id. */
additional comment here to explain that 0, 0x70- 0x7F IDs are reserved
by the architecture, 1 is default for STM
> +#define CORESIGHT_TRACE_ID_NUM 128
> +
> +#define CORESIGHT_TRACE_ID_0 0
> +#define CORESIGHT_TRACE_ID_1 1
> +#define CORESIGHT_TRACE_ID_112 112
> +#define CORESIGHT_TRACE_ID_127 127
> +
can we have these names a little more descriptive -
e.g.
CORESIGHT_TRACE_ID_0_RES 0
CORESIGHT_TRACE_ID_STM 1
CORESIGHT_TRACE_ID_RANGE_LO_RES 0x70
CORESIGHT_TRACE_ID_RANGE_HI_RES 0x7F
Additionally - now we are declaring a #define for the STM ID - it
would be better to use that in coresight-stm.c stm_init_default_data()
to set the trace id for the STM.
Regards
Mike
> static inline int coresight_get_trace_id(int cpu)
> {
> /*
> @@ -43,4 +51,7 @@ static inline int coresight_get_trace_id(int cpu)
> return (CORESIGHT_ETM_PMU_SEED + (cpu * 2));
> }
>
> +/* Get the trace id for the sources except from STM, ETM/ETE. */
> +extern int coresight_get_system_trace_id(void);
> +
> #endif
> --
> 2.17.1
>
--
Mike Leach
Principal Engineer, ARM Ltd.
Manchester Design Centre. UK
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH v3 03/10] Coresight: Add coresight TPDM source driver
2022-02-09 10:56 [PATCH v3 00/10] Coresight: Add support for TPDM and TPDA Mao Jinlong
2022-02-09 10:56 ` [PATCH v3 01/10] Use IDR to maintain all the enabled sources' paths Mao Jinlong
2022-02-09 10:56 ` [PATCH v3 02/10] coresight: Use bitmap to assign trace id to the sources Mao Jinlong
@ 2022-02-09 10:56 ` Mao Jinlong
2022-02-18 16:10 ` Mike Leach
2022-02-09 10:57 ` [PATCH v3 04/10] dt-bindings: arm: Adds CoreSight TPDM hardware definitions Mao Jinlong
` (7 subsequent siblings)
10 siblings, 1 reply; 22+ messages in thread
From: Mao Jinlong @ 2022-02-09 10:56 UTC (permalink / raw)
To: Mathieu Poirier, Suzuki K Poulose, Alexander Shishkin
Cc: Mao Jinlong, Mike Leach, Leo Yan, Greg Kroah-Hartman, coresight,
linux-arm-kernel, linux-kernel, Tingwei Zhang, Yuanfang Zhang,
Tao Zhang, Trilok Soni, Hao Zhang, linux-arm-msm
Add driver to support Coresight device TPDM (Trace, Profiling and
Diagnostics Monitor). TPDM is a monitor to collect data from
different datasets. This change is to add probe/enable/disable
functions for tpdm source.
Signed-off-by: Tao Zhang <quic_taozha@quicinc.com>
Signed-off-by: Mao Jinlong <quic_jinlmao@quicinc.com>
---
drivers/hwtracing/coresight/Kconfig | 13 ++
drivers/hwtracing/coresight/Makefile | 1 +
drivers/hwtracing/coresight/coresight-core.c | 3 +-
drivers/hwtracing/coresight/coresight-tpdm.c | 159 +++++++++++++++++++
drivers/hwtracing/coresight/coresight-tpdm.h | 28 ++++
include/linux/coresight.h | 1 +
6 files changed, 204 insertions(+), 1 deletion(-)
create mode 100644 drivers/hwtracing/coresight/coresight-tpdm.c
create mode 100644 drivers/hwtracing/coresight/coresight-tpdm.h
diff --git a/drivers/hwtracing/coresight/Kconfig b/drivers/hwtracing/coresight/Kconfig
index 514a9b8086e3..5c506a1cd08f 100644
--- a/drivers/hwtracing/coresight/Kconfig
+++ b/drivers/hwtracing/coresight/Kconfig
@@ -201,4 +201,17 @@ config CORESIGHT_TRBE
To compile this driver as a module, choose M here: the module will be
called coresight-trbe.
+
+config CORESIGHT_TPDM
+ tristate "CoreSight Trace, Profiling & Diagnostics Monitor driver"
+ select CORESIGHT_LINKS_AND_SINKS
+ help
+ This driver provides support for configuring monitor. Monitors are
+ primarily responsible for data set collection and support the
+ ability to collect any permutation of data set types. Monitors are
+ also responsible for interaction with system cross triggering.
+
+ To compile this driver as a module, choose M here: the module will be
+ called coresight-tpdm.
+
endif
diff --git a/drivers/hwtracing/coresight/Makefile b/drivers/hwtracing/coresight/Makefile
index b6c4a48140ec..e7392a0dddeb 100644
--- a/drivers/hwtracing/coresight/Makefile
+++ b/drivers/hwtracing/coresight/Makefile
@@ -25,5 +25,6 @@ obj-$(CONFIG_CORESIGHT_CPU_DEBUG) += coresight-cpu-debug.o
obj-$(CONFIG_CORESIGHT_CATU) += coresight-catu.o
obj-$(CONFIG_CORESIGHT_CTI) += coresight-cti.o
obj-$(CONFIG_CORESIGHT_TRBE) += coresight-trbe.o
+obj-$(CONFIG_CORESIGHT_TPDM) += coresight-tpdm.o
coresight-cti-y := coresight-cti-core.o coresight-cti-platform.o \
coresight-cti-sysfs.o
diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtracing/coresight/coresight-core.c
index 6cb55c3f41d5..b56826d9a2b3 100644
--- a/drivers/hwtracing/coresight/coresight-core.c
+++ b/drivers/hwtracing/coresight/coresight-core.c
@@ -1117,7 +1117,8 @@ static int coresight_validate_source(struct coresight_device *csdev,
}
if (subtype != CORESIGHT_DEV_SUBTYPE_SOURCE_PROC &&
- subtype != CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE) {
+ subtype != CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE &&
+ subtype != CORESIGHT_DEV_SUBTYPE_SOURCE_SYS) {
dev_err(&csdev->dev, "wrong device subtype in %s\n", function);
return -EINVAL;
}
diff --git a/drivers/hwtracing/coresight/coresight-tpdm.c b/drivers/hwtracing/coresight/coresight-tpdm.c
new file mode 100644
index 000000000000..51b8b17e6a80
--- /dev/null
+++ b/drivers/hwtracing/coresight/coresight-tpdm.c
@@ -0,0 +1,159 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include <linux/amba/bus.h>
+#include <linux/bitmap.h>
+#include <linux/coresight.h>
+#include <linux/coresight-pmu.h>
+#include <linux/device.h>
+#include <linux/err.h>
+#include <linux/fs.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of.h>
+
+#include "coresight-priv.h"
+#include "coresight-tpdm.h"
+
+DEFINE_CORESIGHT_DEVLIST(tpdm_devs, "tpdm");
+
+/* TPDM enable operations */
+static int tpdm_enable(struct coresight_device *csdev,
+ struct perf_event *event, u32 mode)
+{
+ struct tpdm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
+
+ mutex_lock(&drvdata->lock);
+ if (drvdata->enable) {
+ mutex_unlock(&drvdata->lock);
+ return -EBUSY;
+ }
+
+ drvdata->enable = true;
+ mutex_unlock(&drvdata->lock);
+
+ dev_info(drvdata->dev, "TPDM tracing enabled\n");
+ return 0;
+}
+
+/* TPDM disable operations */
+static void tpdm_disable(struct coresight_device *csdev,
+ struct perf_event *event)
+{
+ struct tpdm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
+
+ mutex_lock(&drvdata->lock);
+ if (!drvdata->enable) {
+ mutex_unlock(&drvdata->lock);
+ return;
+ }
+
+ drvdata->enable = false;
+ mutex_unlock(&drvdata->lock);
+
+ dev_info(drvdata->dev, "TPDM tracing disabled\n");
+}
+
+static int tpdm_trace_id(struct coresight_device *csdev)
+{
+ struct tpdm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
+
+ return drvdata->traceid;
+}
+
+static const struct coresight_ops_source tpdm_source_ops = {
+ .trace_id = tpdm_trace_id,
+ .enable = tpdm_enable,
+ .disable = tpdm_disable,
+};
+
+static const struct coresight_ops tpdm_cs_ops = {
+ .source_ops = &tpdm_source_ops,
+};
+
+static void tpdm_init_default_data(struct tpdm_drvdata *drvdata)
+{
+ drvdata->traceid = coresight_get_system_trace_id();
+}
+
+static int tpdm_probe(struct amba_device *adev, const struct amba_id *id)
+{
+ struct device *dev = &adev->dev;
+ struct coresight_platform_data *pdata;
+ struct tpdm_drvdata *drvdata;
+ struct coresight_desc desc = { 0 };
+
+ pdata = coresight_get_platform_data(dev);
+ if (IS_ERR(pdata))
+ return PTR_ERR(pdata);
+ adev->dev.platform_data = pdata;
+
+ /* driver data*/
+ drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
+ if (!drvdata)
+ return -ENOMEM;
+ drvdata->dev = &adev->dev;
+ dev_set_drvdata(dev, drvdata);
+
+ drvdata->base = devm_ioremap_resource(dev, &adev->res);
+ if (!drvdata->base)
+ return -ENOMEM;
+
+ mutex_init(&drvdata->lock);
+ tpdm_init_default_data(drvdata);
+
+ /* Set up coresight component description */
+ desc.name = coresight_alloc_device_name(&tpdm_devs, dev);
+ if (!desc.name)
+ return -ENOMEM;
+ desc.type = CORESIGHT_DEV_TYPE_SOURCE;
+ desc.subtype.source_subtype = CORESIGHT_DEV_SUBTYPE_SOURCE_SYS;
+ desc.ops = &tpdm_cs_ops;
+ desc.pdata = adev->dev.platform_data;
+ desc.dev = &adev->dev;
+ drvdata->csdev = coresight_register(&desc);
+ if (IS_ERR(drvdata->csdev))
+ return PTR_ERR(drvdata->csdev);
+
+ /* Decrease pm refcount when probe is done.*/
+ pm_runtime_put(&adev->dev);
+
+ return 0;
+}
+
+static void __exit tpdm_remove(struct amba_device *adev)
+{
+ struct tpdm_drvdata *drvdata = dev_get_drvdata(&adev->dev);
+
+ coresight_unregister(drvdata->csdev);
+}
+
+/*
+ * Different TPDM has different periph id.
+ * The difference is 0-7 bits' value. So ignore 0-7 bits.
+ */
+static struct amba_id tpdm_ids[] = {
+ {
+ .id = 0x000f0e00,
+ .mask = 0x000fff00,
+ },
+ { 0, 0},
+};
+
+static struct amba_driver tpdm_driver = {
+ .drv = {
+ .name = "coresight-tpdm",
+ .owner = THIS_MODULE,
+ .suppress_bind_attrs = true,
+ },
+ .probe = tpdm_probe,
+ .id_table = tpdm_ids,
+};
+
+module_amba_driver(tpdm_driver);
+
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("Trace, Profiling & Diagnostic Monitor driver");
diff --git a/drivers/hwtracing/coresight/coresight-tpdm.h b/drivers/hwtracing/coresight/coresight-tpdm.h
new file mode 100644
index 000000000000..2effbabf349b
--- /dev/null
+++ b/drivers/hwtracing/coresight/coresight-tpdm.h
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef _CORESIGHT_CORESIGHT_TPDM_H
+#define _CORESIGHT_CORESIGHT_TPDM_H
+
+/**
+ * struct tpdm_drvdata - specifics associated to an TPDM component
+ * @base: memory mapped base address for this component.
+ * @dev: The device entity associated to this component.
+ * @csdev: component vitals needed by the framework.
+ * @lock: lock for the enable value.
+ * @enable: enable status of the component.
+ * @traceid: value of the current ID for this component.
+ */
+
+struct tpdm_drvdata {
+ void __iomem *base;
+ struct device *dev;
+ struct coresight_device *csdev;
+ struct mutex lock;
+ bool enable;
+ int traceid;
+};
+
+#endif /* _CORESIGHT_CORESIGHT_TPDM_H */
diff --git a/include/linux/coresight.h b/include/linux/coresight.h
index 93a2922b7653..e48d463be63b 100644
--- a/include/linux/coresight.h
+++ b/include/linux/coresight.h
@@ -65,6 +65,7 @@ enum coresight_dev_subtype_source {
CORESIGHT_DEV_SUBTYPE_SOURCE_PROC,
CORESIGHT_DEV_SUBTYPE_SOURCE_BUS,
CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE,
+ CORESIGHT_DEV_SUBTYPE_SOURCE_SYS,
};
enum coresight_dev_subtype_helper {
--
2.17.1
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH v3 03/10] Coresight: Add coresight TPDM source driver
2022-02-09 10:56 ` [PATCH v3 03/10] Coresight: Add coresight TPDM source driver Mao Jinlong
@ 2022-02-18 16:10 ` Mike Leach
0 siblings, 0 replies; 22+ messages in thread
From: Mike Leach @ 2022-02-18 16:10 UTC (permalink / raw)
To: Mao Jinlong
Cc: Mathieu Poirier, Suzuki K Poulose, Alexander Shishkin, Leo Yan,
Greg Kroah-Hartman, coresight, linux-arm-kernel, linux-kernel,
Tingwei Zhang, Yuanfang Zhang, Tao Zhang, Trilok Soni, Hao Zhang,
linux-arm-msm
HI,
On Wed, 9 Feb 2022 at 10:57, Mao Jinlong <quic_jinlmao@quicinc.com> wrote:
>
> Add driver to support Coresight device TPDM (Trace, Profiling and
> Diagnostics Monitor). TPDM is a monitor to collect data from
> different datasets. This change is to add probe/enable/disable
> functions for tpdm source.
>
> Signed-off-by: Tao Zhang <quic_taozha@quicinc.com>
> Signed-off-by: Mao Jinlong <quic_jinlmao@quicinc.com>
> ---
> drivers/hwtracing/coresight/Kconfig | 13 ++
> drivers/hwtracing/coresight/Makefile | 1 +
> drivers/hwtracing/coresight/coresight-core.c | 3 +-
> drivers/hwtracing/coresight/coresight-tpdm.c | 159 +++++++++++++++++++
> drivers/hwtracing/coresight/coresight-tpdm.h | 28 ++++
> include/linux/coresight.h | 1 +
> 6 files changed, 204 insertions(+), 1 deletion(-)
> create mode 100644 drivers/hwtracing/coresight/coresight-tpdm.c
> create mode 100644 drivers/hwtracing/coresight/coresight-tpdm.h
>
> diff --git a/drivers/hwtracing/coresight/Kconfig b/drivers/hwtracing/coresight/Kconfig
> index 514a9b8086e3..5c506a1cd08f 100644
> --- a/drivers/hwtracing/coresight/Kconfig
> +++ b/drivers/hwtracing/coresight/Kconfig
> @@ -201,4 +201,17 @@ config CORESIGHT_TRBE
>
> To compile this driver as a module, choose M here: the module will be
> called coresight-trbe.
> +
> +config CORESIGHT_TPDM
> + tristate "CoreSight Trace, Profiling & Diagnostics Monitor driver"
> + select CORESIGHT_LINKS_AND_SINKS
> + help
> + This driver provides support for configuring monitor. Monitors are
> + primarily responsible for data set collection and support the
> + ability to collect any permutation of data set types. Monitors are
> + also responsible for interaction with system cross triggering.
> +
> + To compile this driver as a module, choose M here: the module will be
> + called coresight-tpdm.
> +
> endif
> diff --git a/drivers/hwtracing/coresight/Makefile b/drivers/hwtracing/coresight/Makefile
> index b6c4a48140ec..e7392a0dddeb 100644
> --- a/drivers/hwtracing/coresight/Makefile
> +++ b/drivers/hwtracing/coresight/Makefile
> @@ -25,5 +25,6 @@ obj-$(CONFIG_CORESIGHT_CPU_DEBUG) += coresight-cpu-debug.o
> obj-$(CONFIG_CORESIGHT_CATU) += coresight-catu.o
> obj-$(CONFIG_CORESIGHT_CTI) += coresight-cti.o
> obj-$(CONFIG_CORESIGHT_TRBE) += coresight-trbe.o
> +obj-$(CONFIG_CORESIGHT_TPDM) += coresight-tpdm.o
> coresight-cti-y := coresight-cti-core.o coresight-cti-platform.o \
> coresight-cti-sysfs.o
> diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtracing/coresight/coresight-core.c
> index 6cb55c3f41d5..b56826d9a2b3 100644
> --- a/drivers/hwtracing/coresight/coresight-core.c
> +++ b/drivers/hwtracing/coresight/coresight-core.c
> @@ -1117,7 +1117,8 @@ static int coresight_validate_source(struct coresight_device *csdev,
> }
>
> if (subtype != CORESIGHT_DEV_SUBTYPE_SOURCE_PROC &&
> - subtype != CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE) {
> + subtype != CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE &&
> + subtype != CORESIGHT_DEV_SUBTYPE_SOURCE_SYS) {
> dev_err(&csdev->dev, "wrong device subtype in %s\n", function);
> return -EINVAL;
> }
> diff --git a/drivers/hwtracing/coresight/coresight-tpdm.c b/drivers/hwtracing/coresight/coresight-tpdm.c
> new file mode 100644
> index 000000000000..51b8b17e6a80
> --- /dev/null
> +++ b/drivers/hwtracing/coresight/coresight-tpdm.c
> @@ -0,0 +1,159 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
> + */
> +
> +#include <linux/amba/bus.h>
> +#include <linux/bitmap.h>
> +#include <linux/coresight.h>
> +#include <linux/coresight-pmu.h>
> +#include <linux/device.h>
> +#include <linux/err.h>
> +#include <linux/fs.h>
> +#include <linux/io.h>
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +
> +#include "coresight-priv.h"
> +#include "coresight-tpdm.h"
> +
> +DEFINE_CORESIGHT_DEVLIST(tpdm_devs, "tpdm");
> +
> +/* TPDM enable operations */
> +static int tpdm_enable(struct coresight_device *csdev,
> + struct perf_event *event, u32 mode)
> +{
> + struct tpdm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
> +
> + mutex_lock(&drvdata->lock);
> + if (drvdata->enable) {
> + mutex_unlock(&drvdata->lock);
> + return -EBUSY;
> + }
> +
> + drvdata->enable = true;
> + mutex_unlock(&drvdata->lock);
> +
> + dev_info(drvdata->dev, "TPDM tracing enabled\n");
> + return 0;
> +}
> +
> +/* TPDM disable operations */
> +static void tpdm_disable(struct coresight_device *csdev,
> + struct perf_event *event)
> +{
> + struct tpdm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
> +
> + mutex_lock(&drvdata->lock);
> + if (!drvdata->enable) {
> + mutex_unlock(&drvdata->lock);
> + return;
> + }
> +
> + drvdata->enable = false;
> + mutex_unlock(&drvdata->lock);
> +
> + dev_info(drvdata->dev, "TPDM tracing disabled\n");
> +}
> +
> +static int tpdm_trace_id(struct coresight_device *csdev)
> +{
> + struct tpdm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
> +
> + return drvdata->traceid;
> +}
> +
> +static const struct coresight_ops_source tpdm_source_ops = {
> + .trace_id = tpdm_trace_id,
> + .enable = tpdm_enable,
> + .disable = tpdm_disable,
> +};
> +
> +static const struct coresight_ops tpdm_cs_ops = {
> + .source_ops = &tpdm_source_ops,
> +};
> +
> +static void tpdm_init_default_data(struct tpdm_drvdata *drvdata)
> +{
> + drvdata->traceid = coresight_get_system_trace_id();
> +}
> +
> +static int tpdm_probe(struct amba_device *adev, const struct amba_id *id)
> +{
> + struct device *dev = &adev->dev;
> + struct coresight_platform_data *pdata;
> + struct tpdm_drvdata *drvdata;
> + struct coresight_desc desc = { 0 };
> +
> + pdata = coresight_get_platform_data(dev);
> + if (IS_ERR(pdata))
> + return PTR_ERR(pdata);
> + adev->dev.platform_data = pdata;
> +
> + /* driver data*/
> + drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
> + if (!drvdata)
> + return -ENOMEM;
> + drvdata->dev = &adev->dev;
> + dev_set_drvdata(dev, drvdata);
> +
> + drvdata->base = devm_ioremap_resource(dev, &adev->res);
> + if (!drvdata->base)
> + return -ENOMEM;
> +
> + mutex_init(&drvdata->lock);
> + tpdm_init_default_data(drvdata);
> +
> + /* Set up coresight component description */
> + desc.name = coresight_alloc_device_name(&tpdm_devs, dev);
> + if (!desc.name)
> + return -ENOMEM;
> + desc.type = CORESIGHT_DEV_TYPE_SOURCE;
> + desc.subtype.source_subtype = CORESIGHT_DEV_SUBTYPE_SOURCE_SYS;
> + desc.ops = &tpdm_cs_ops;
> + desc.pdata = adev->dev.platform_data;
> + desc.dev = &adev->dev;
> + drvdata->csdev = coresight_register(&desc);
> + if (IS_ERR(drvdata->csdev))
> + return PTR_ERR(drvdata->csdev);
> +
> + /* Decrease pm refcount when probe is done.*/
> + pm_runtime_put(&adev->dev);
> +
> + return 0;
> +}
> +
> +static void __exit tpdm_remove(struct amba_device *adev)
> +{
> + struct tpdm_drvdata *drvdata = dev_get_drvdata(&adev->dev);
> +
> + coresight_unregister(drvdata->csdev);
> +}
> +
> +/*
> + * Different TPDM has different periph id.
> + * The difference is 0-7 bits' value. So ignore 0-7 bits.
> + */
> +static struct amba_id tpdm_ids[] = {
> + {
> + .id = 0x000f0e00,
> + .mask = 0x000fff00,
> + },
> + { 0, 0},
> +};
> +
> +static struct amba_driver tpdm_driver = {
> + .drv = {
> + .name = "coresight-tpdm",
> + .owner = THIS_MODULE,
> + .suppress_bind_attrs = true,
> + },
> + .probe = tpdm_probe,
> + .id_table = tpdm_ids,
> +};
> +
> +module_amba_driver(tpdm_driver);
> +
> +MODULE_LICENSE("GPL v2");
> +MODULE_DESCRIPTION("Trace, Profiling & Diagnostic Monitor driver");
> diff --git a/drivers/hwtracing/coresight/coresight-tpdm.h b/drivers/hwtracing/coresight/coresight-tpdm.h
> new file mode 100644
> index 000000000000..2effbabf349b
> --- /dev/null
> +++ b/drivers/hwtracing/coresight/coresight-tpdm.h
> @@ -0,0 +1,28 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
> + */
> +
> +#ifndef _CORESIGHT_CORESIGHT_TPDM_H
> +#define _CORESIGHT_CORESIGHT_TPDM_H
> +
> +/**
> + * struct tpdm_drvdata - specifics associated to an TPDM component
> + * @base: memory mapped base address for this component.
> + * @dev: The device entity associated to this component.
> + * @csdev: component vitals needed by the framework.
> + * @lock: lock for the enable value.
> + * @enable: enable status of the component.
> + * @traceid: value of the current ID for this component.
> + */
> +
> +struct tpdm_drvdata {
> + void __iomem *base;
> + struct device *dev;
> + struct coresight_device *csdev;
> + struct mutex lock;
> + bool enable;
> + int traceid;
TraceID appears to have no purpose in the hardware and does not
apparently drive onto the ATB - ATID signals from this device.
This should be dropped and the core code fixed to allow for sources
that have no trace id.
Regards
Mike
> +};
> +
> +#endif /* _CORESIGHT_CORESIGHT_TPDM_H */
> diff --git a/include/linux/coresight.h b/include/linux/coresight.h
> index 93a2922b7653..e48d463be63b 100644
> --- a/include/linux/coresight.h
> +++ b/include/linux/coresight.h
> @@ -65,6 +65,7 @@ enum coresight_dev_subtype_source {
> CORESIGHT_DEV_SUBTYPE_SOURCE_PROC,
> CORESIGHT_DEV_SUBTYPE_SOURCE_BUS,
> CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE,
> + CORESIGHT_DEV_SUBTYPE_SOURCE_SYS,
> };
>
> enum coresight_dev_subtype_helper {
> --
> 2.17.1
>
--
Mike Leach
Principal Engineer, ARM Ltd.
Manchester Design Centre. UK
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH v3 04/10] dt-bindings: arm: Adds CoreSight TPDM hardware definitions
2022-02-09 10:56 [PATCH v3 00/10] Coresight: Add support for TPDM and TPDA Mao Jinlong
` (2 preceding siblings ...)
2022-02-09 10:56 ` [PATCH v3 03/10] Coresight: Add coresight TPDM source driver Mao Jinlong
@ 2022-02-09 10:57 ` Mao Jinlong
2022-02-17 17:48 ` Mike Leach
2022-02-09 10:57 ` [PATCH v3 05/10] coresight-tpdm: Add DSB dataset support Mao Jinlong
` (6 subsequent siblings)
10 siblings, 1 reply; 22+ messages in thread
From: Mao Jinlong @ 2022-02-09 10:57 UTC (permalink / raw)
To: Mathieu Poirier, Suzuki K Poulose, Alexander Shishkin
Cc: Mao Jinlong, Mike Leach, Leo Yan, Greg Kroah-Hartman, coresight,
linux-arm-kernel, linux-kernel, Tingwei Zhang, Yuanfang Zhang,
Tao Zhang, Trilok Soni, Hao Zhang, linux-arm-msm
Adds new coresight-tpdm.yaml file describing the bindings required
to define tpdm in the device trees.
Signed-off-by: Tao Zhang <quic_taozha@quicinc.com>
Signed-off-by: Mao Jinlong <quic_jinlmao@quicinc.com>
---
.../bindings/arm/coresight-tpdm.yaml | 81 +++++++++++++++++++
.../devicetree/bindings/arm/coresight.txt | 7 ++
MAINTAINERS | 1 +
3 files changed, 89 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/coresight-tpdm.yaml
diff --git a/Documentation/devicetree/bindings/arm/coresight-tpdm.yaml b/Documentation/devicetree/bindings/arm/coresight-tpdm.yaml
new file mode 100644
index 000000000000..7ebc1bf7abc2
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/coresight-tpdm.yaml
@@ -0,0 +1,81 @@
+# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
+# Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/coresight-tpdm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Trace, Profiling and Diagnostics Monitor - TPDM
+
+description: |
+ The TPDM or Monitor serves as data collection component for various dataset
+ types specified in the QPMDA spec. It covers Implementation defined ((ImplDef),
+ Basic Counts (BC), Tenure Counts (TC), Continuous Multi-Bit (CMB), and Discrete
+ Single Bit (DSB). It performs data collection in the data producing clock
+ domain and transfers it to the data collection time domain, generally ATB
+ clock domain.
+
+ The primary use case of the TPDM is to collect data from different data
+ sources and send it to a TPDA for packetization, timestamping, and funneling.
+
+maintainers:
+ - Suzuki K Poulose <suzuki.poulose@arm.com>
+ - Mathieu Poirier <mathieu.poirier@linaro.org>
+
+properties:
+ $nodename:
+ pattern: "^tpdm(@[0-9a-f]+)$"
+ compatible:
+ items:
+ - const: qcom,coresight-tpdm
+ - const: arm,primecell
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ items:
+ - const: apb_pclk
+
+ out-ports:
+ description: |
+ Output connections from the TPDM to legacy CoreSight trace bus.
+ $ref: /schemas/graph.yaml#/properties/ports
+ properties:
+ port:
+ description: Output connection from the TPDM to legacy CoreSight
+ Trace bus.
+ $ref: /schemas/graph.yaml#/properties/port
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+
+additionalProperties: false
+
+examples:
+ # minimum TPDM definition.
+ - |
+ tpdm@6980000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x6980000 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ port {
+ tpdm_turing_out_funnel_turing: endpoint {
+ remote-endpoint =
+ <&funnel_turing_in_tpdm_turing>;
+ };
+ };
+ };
+ };
+
+...
diff --git a/Documentation/devicetree/bindings/arm/coresight.txt b/Documentation/devicetree/bindings/arm/coresight.txt
index c68d93a35b6c..f7ce8af48574 100644
--- a/Documentation/devicetree/bindings/arm/coresight.txt
+++ b/Documentation/devicetree/bindings/arm/coresight.txt
@@ -52,6 +52,10 @@ its hardware characteristcs.
"arm,coresight-cti", "arm,primecell";
See coresight-cti.yaml for full CTI definitions.
+ - Trace, Profiling and Diagnostics Monitor (TPDM):
+ "qcom,coresight-tpdm", "arm,primecell";
+ See coresight-tpdm.yaml for full TPDM definitions.
+
* reg: physical base address and length of the register
set(s) of the component.
@@ -82,6 +86,9 @@ its hardware characteristcs.
* Required properties for Coresight Cross Trigger Interface (CTI)
See coresight-cti.yaml for full CTI definitions.
+* Required properties for Trace, Profiling and Diagnostics Monitor (TPDM)
+ See coresight-tpdm.yaml for full TPDM definitions.
+
* Required properties for devices that don't show up on the AMBA bus, such as
non-configurable replicators and non-configurable funnels:
diff --git a/MAINTAINERS b/MAINTAINERS
index ea3e6c914384..434bbe98d22b 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1906,6 +1906,7 @@ T: git git://git.kernel.org/pub/scm/linux/kernel/git/coresight/linux.git
F: Documentation/ABI/testing/sysfs-bus-coresight-devices-*
F: Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt
F: Documentation/devicetree/bindings/arm/coresight-cti.yaml
+F: Documentation/devicetree/bindings/arm/coresight-tpdm.yaml
F: Documentation/devicetree/bindings/arm/coresight.txt
F: Documentation/devicetree/bindings/arm/ete.yaml
F: Documentation/devicetree/bindings/arm/trbe.yaml
--
2.17.1
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH v3 04/10] dt-bindings: arm: Adds CoreSight TPDM hardware definitions
2022-02-09 10:57 ` [PATCH v3 04/10] dt-bindings: arm: Adds CoreSight TPDM hardware definitions Mao Jinlong
@ 2022-02-17 17:48 ` Mike Leach
0 siblings, 0 replies; 22+ messages in thread
From: Mike Leach @ 2022-02-17 17:48 UTC (permalink / raw)
To: Mao Jinlong
Cc: Mathieu Poirier, Suzuki K Poulose, Alexander Shishkin, Leo Yan,
Greg Kroah-Hartman, coresight, linux-arm-kernel, linux-kernel,
Tingwei Zhang, Yuanfang Zhang, Tao Zhang, Trilok Soni, Hao Zhang,
linux-arm-msm
Hi,
On Wed, 9 Feb 2022 at 10:57, Mao Jinlong <quic_jinlmao@quicinc.com> wrote:
>
> Adds new coresight-tpdm.yaml file describing the bindings required
> to define tpdm in the device trees.
>
> Signed-off-by: Tao Zhang <quic_taozha@quicinc.com>
> Signed-off-by: Mao Jinlong <quic_jinlmao@quicinc.com>
> ---
> .../bindings/arm/coresight-tpdm.yaml | 81 +++++++++++++++++++
> .../devicetree/bindings/arm/coresight.txt | 7 ++
> MAINTAINERS | 1 +
> 3 files changed, 89 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/arm/coresight-tpdm.yaml
>
> diff --git a/Documentation/devicetree/bindings/arm/coresight-tpdm.yaml b/Documentation/devicetree/bindings/arm/coresight-tpdm.yaml
> new file mode 100644
> index 000000000000..7ebc1bf7abc2
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/coresight-tpdm.yaml
> @@ -0,0 +1,81 @@
> +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
> +# Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/arm/coresight-tpdm.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Trace, Profiling and Diagnostics Monitor - TPDM
> +
> +description: |
> + The TPDM or Monitor serves as data collection component for various dataset
> + types specified in the QPMDA spec. It covers Implementation defined ((ImplDef),
> + Basic Counts (BC), Tenure Counts (TC), Continuous Multi-Bit (CMB), and Discrete
> + Single Bit (DSB). It performs data collection in the data producing clock
> + domain and transfers it to the data collection time domain, generally ATB
> + clock domain.
> +
> + The primary use case of the TPDM is to collect data from different data
> + sources and send it to a TPDA for packetization, timestamping, and funneling.
> +
> +maintainers:
> + - Suzuki K Poulose <suzuki.poulose@arm.com>
> + - Mathieu Poirier <mathieu.poirier@linaro.org>
> +
> +properties:
> + $nodename:
> + pattern: "^tpdm(@[0-9a-f]+)$"
> + compatible:
> + items:
> + - const: qcom,coresight-tpdm
> + - const: arm,primecell
> +
> + reg:
> + maxItems: 1
> +
> + clocks:
> + maxItems: 1
> +
> + clock-names:
> + items:
> + - const: apb_pclk
> +
> + out-ports:
> + description: |
> + Output connections from the TPDM to legacy CoreSight trace bus.
> + $ref: /schemas/graph.yaml#/properties/ports
> + properties:
> + port:
> + description: Output connection from the TPDM to legacy CoreSight
> + Trace bus.
> + $ref: /schemas/graph.yaml#/properties/port
> +
As we discussed in patch 0/10 of this set - the TDPM actually sends
data to TDPA - not to coresight. These descriptions should match that.
> +required:
> + - compatible
> + - reg
> + - clocks
> + - clock-names
> +
> +additionalProperties: false
> +
> +examples:
> + # minimum TPDM definition.
> + - |
> + tpdm@6980000 {
> + compatible = "qcom,coresight-tpdm", "arm,primecell";
> + reg = <0x6980000 0x1000>;
> +
> + clocks = <&aoss_qmp>;
> + clock-names = "apb_pclk";
> +
> + out-ports {
> + port {
> + tpdm_turing_out_funnel_turing: endpoint {
> + remote-endpoint =
> + <&funnel_turing_in_tpdm_turing>;
> + };
> + };
> + };
> + };
> +
example looks OK, but I would like to see something of a _tdpa in the
nameing as that is the funnel / link the tdpm sends data to.
Regards
Mike
> +...
> diff --git a/Documentation/devicetree/bindings/arm/coresight.txt b/Documentation/devicetree/bindings/arm/coresight.txt
> index c68d93a35b6c..f7ce8af48574 100644
> --- a/Documentation/devicetree/bindings/arm/coresight.txt
> +++ b/Documentation/devicetree/bindings/arm/coresight.txt
> @@ -52,6 +52,10 @@ its hardware characteristcs.
> "arm,coresight-cti", "arm,primecell";
> See coresight-cti.yaml for full CTI definitions.
>
> + - Trace, Profiling and Diagnostics Monitor (TPDM):
> + "qcom,coresight-tpdm", "arm,primecell";
> + See coresight-tpdm.yaml for full TPDM definitions.
> +
> * reg: physical base address and length of the register
> set(s) of the component.
>
> @@ -82,6 +86,9 @@ its hardware characteristcs.
> * Required properties for Coresight Cross Trigger Interface (CTI)
> See coresight-cti.yaml for full CTI definitions.
>
> +* Required properties for Trace, Profiling and Diagnostics Monitor (TPDM)
> + See coresight-tpdm.yaml for full TPDM definitions.
> +
> * Required properties for devices that don't show up on the AMBA bus, such as
> non-configurable replicators and non-configurable funnels:
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index ea3e6c914384..434bbe98d22b 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -1906,6 +1906,7 @@ T: git git://git.kernel.org/pub/scm/linux/kernel/git/coresight/linux.git
> F: Documentation/ABI/testing/sysfs-bus-coresight-devices-*
> F: Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt
> F: Documentation/devicetree/bindings/arm/coresight-cti.yaml
> +F: Documentation/devicetree/bindings/arm/coresight-tpdm.yaml
> F: Documentation/devicetree/bindings/arm/coresight.txt
> F: Documentation/devicetree/bindings/arm/ete.yaml
> F: Documentation/devicetree/bindings/arm/trbe.yaml
> --
> 2.17.1
>
--
Mike Leach
Principal Engineer, ARM Ltd.
Manchester Design Centre. UK
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH v3 05/10] coresight-tpdm: Add DSB dataset support
2022-02-09 10:56 [PATCH v3 00/10] Coresight: Add support for TPDM and TPDA Mao Jinlong
` (3 preceding siblings ...)
2022-02-09 10:57 ` [PATCH v3 04/10] dt-bindings: arm: Adds CoreSight TPDM hardware definitions Mao Jinlong
@ 2022-02-09 10:57 ` Mao Jinlong
2022-02-18 16:10 ` Mike Leach
2022-02-09 10:57 ` [PATCH v3 06/10] coresight-tpdm: Add integration test support Mao Jinlong
` (5 subsequent siblings)
10 siblings, 1 reply; 22+ messages in thread
From: Mao Jinlong @ 2022-02-09 10:57 UTC (permalink / raw)
To: Mathieu Poirier, Suzuki K Poulose, Alexander Shishkin
Cc: Mao Jinlong, Mike Leach, Leo Yan, Greg Kroah-Hartman, coresight,
linux-arm-kernel, linux-kernel, Tingwei Zhang, Yuanfang Zhang,
Tao Zhang, Trilok Soni, Hao Zhang, linux-arm-msm
TPDM serves as data collection component for various dataset types.
DSB(Discrete Single Bit) is one of the dataset types. DSB subunit
can be enabled for data collection by writing 1 to the first bit of
DSB_CR register. This change is to add enable/disable function for
DSB dataset by writing DSB_CR register.
Signed-off-by: Tao Zhang <quic_taozha@quicinc.com>
Signed-off-by: Mao Jinlong <quic_jinlmao@quicinc.com>
---
drivers/hwtracing/coresight/coresight-tpdm.c | 57 ++++++++++++++++++++
drivers/hwtracing/coresight/coresight-tpdm.h | 21 ++++++++
2 files changed, 78 insertions(+)
diff --git a/drivers/hwtracing/coresight/coresight-tpdm.c b/drivers/hwtracing/coresight/coresight-tpdm.c
index 51b8b17e6a80..c6480b7389b0 100644
--- a/drivers/hwtracing/coresight/coresight-tpdm.c
+++ b/drivers/hwtracing/coresight/coresight-tpdm.c
@@ -20,7 +20,28 @@
DEFINE_CORESIGHT_DEVLIST(tpdm_devs, "tpdm");
+static void tpdm_enable_dsb(struct tpdm_drvdata *drvdata)
+{
+ u32 val;
+
+ /* Set the enable bit of DSB control register to 1 */
+ val = readl_relaxed(drvdata->base + TPDM_DSB_CR);
+ val = val | BIT(0);
+ writel_relaxed(val, drvdata->base + TPDM_DSB_CR);
+}
+
/** TPDM enable operations **/
+static void _tpdm_enable(struct tpdm_drvdata *drvdata)
+{
+ CS_UNLOCK(drvdata->base);
+
+ /* Check if DSB datasets is present for TPDM. */
+ if (test_bit(TPDM_DS_DSB, drvdata->datasets))
+ tpdm_enable_dsb(drvdata);
+
+ CS_LOCK(drvdata->base);
+}
+
static int tpdm_enable(struct coresight_device *csdev,
struct perf_event *event, u32 mode)
{
@@ -32,6 +53,7 @@ static int tpdm_enable(struct coresight_device *csdev,
return -EBUSY;
}
+ _tpdm_enable(drvdata);
drvdata->enable = true;
mutex_unlock(&drvdata->lock);
@@ -39,7 +61,29 @@ static int tpdm_enable(struct coresight_device *csdev,
return 0;
}
+static void tpdm_disable_dsb(struct tpdm_drvdata *drvdata)
+{
+ u32 val;
+
+ /* Set the enable bit of DSB control register to 0 */
+ val = readl_relaxed(drvdata->base + TPDM_DSB_CR);
+ val = val & ~BIT(0);
+ writel_relaxed(val, drvdata->base + TPDM_DSB_CR);
+}
+
/** TPDM disable operations **/
+static void _tpdm_disable(struct tpdm_drvdata *drvdata)
+{
+ CS_UNLOCK(drvdata->base);
+
+ /* Check if DSB datasets is present for TPDM. */
+ if (test_bit(TPDM_DS_DSB, drvdata->datasets))
+ tpdm_disable_dsb(drvdata);
+
+ CS_LOCK(drvdata->base);
+
+}
+
static void tpdm_disable(struct coresight_device *csdev,
struct perf_event *event)
{
@@ -51,6 +95,7 @@ static void tpdm_disable(struct coresight_device *csdev,
return;
}
+ _tpdm_disable(drvdata);
drvdata->enable = false;
mutex_unlock(&drvdata->lock);
@@ -76,7 +121,19 @@ static const struct coresight_ops tpdm_cs_ops = {
static void tpdm_init_default_data(struct tpdm_drvdata *drvdata)
{
+ int i;
+ u32 pidr;
+
drvdata->traceid = coresight_get_system_trace_id();
+
+ CS_UNLOCK(drvdata->base);
+ /* Get the datasets present on the TPDM. */
+ pidr = readl_relaxed(drvdata->base + CORESIGHT_PERIPHIDR0);
+ for (i = 0; i < TPDM_DATASETS; i++) {
+ if (pidr & BIT(i))
+ __set_bit(i, drvdata->datasets);
+ }
+ CS_LOCK(drvdata->base);
}
static int tpdm_probe(struct amba_device *adev, const struct amba_id *id)
diff --git a/drivers/hwtracing/coresight/coresight-tpdm.h b/drivers/hwtracing/coresight/coresight-tpdm.h
index 2effbabf349b..cb3ddc6c89ae 100644
--- a/drivers/hwtracing/coresight/coresight-tpdm.h
+++ b/drivers/hwtracing/coresight/coresight-tpdm.h
@@ -6,6 +6,25 @@
#ifndef _CORESIGHT_CORESIGHT_TPDM_H
#define _CORESIGHT_CORESIGHT_TPDM_H
+/* The max number of the datasets that TPDM supports */
+#define TPDM_DATASETS 7
+
+/* DSB Subunit Registers */
+#define TPDM_DSB_CR (0x780)
+
+/**
+ * This enum is for PERIPHIDR0 register of TPDM.
+ * The fields [6:0] of PERIPHIDR0 are used to determine what
+ * interfaces and subunits are present on a given TPDM.
+ *
+ * PERIPHIDR0[0] : Fix to 1 if ImplDef subunit present, else 0
+ * PERIPHIDR0[1] : Fix to 1 if DSB subunit present, else 0
+ */
+enum tpdm_dataset {
+ TPDM_DS_IMPLDEF,
+ TPDM_DS_DSB,
+};
+
/**
* struct tpdm_drvdata - specifics associated to an TPDM component
* @base: memory mapped base address for this component.
@@ -13,6 +32,7 @@
* @csdev: component vitals needed by the framework.
* @lock: lock for the enable value.
* @enable: enable status of the component.
+ * @datasets: The datasets types present of the TPDM.
* @traceid: value of the current ID for this component.
*/
@@ -22,6 +42,7 @@ struct tpdm_drvdata {
struct coresight_device *csdev;
struct mutex lock;
bool enable;
+ DECLARE_BITMAP(datasets, TPDM_DATASETS);
int traceid;
};
--
2.17.1
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH v3 05/10] coresight-tpdm: Add DSB dataset support
2022-02-09 10:57 ` [PATCH v3 05/10] coresight-tpdm: Add DSB dataset support Mao Jinlong
@ 2022-02-18 16:10 ` Mike Leach
0 siblings, 0 replies; 22+ messages in thread
From: Mike Leach @ 2022-02-18 16:10 UTC (permalink / raw)
To: Mao Jinlong
Cc: Mathieu Poirier, Suzuki K Poulose, Alexander Shishkin, Leo Yan,
Greg Kroah-Hartman, coresight, linux-arm-kernel, linux-kernel,
Tingwei Zhang, Yuanfang Zhang, Tao Zhang, Trilok Soni, Hao Zhang,
linux-arm-msm
Hi
This patch does not apply cleanly:-
=======================================
git apply -v ../patch.in/qcom/qcom-05.patch
Checking patch drivers/hwtracing/coresight/coresight-tpdm.c...
error: while searching for:
DEFINE_CORESIGHT_DEVLIST(tpdm_devs, "tpdm");
/** TPDM enable operations **/
static int tpdm_enable(struct coresight_device *csdev,
struct perf_event *event, u32 mode)
{
error: patch failed: drivers/hwtracing/coresight/coresight-tpdm.c:20
error: drivers/hwtracing/coresight/coresight-tpdm.c: patch does not apply
Checking patch drivers/hwtracing/coresight/coresight-tpdm.h...
=======================================
In patch 3 - the first time coresight-tpdm.c. is added the comment line is
/* TPDM enable operations */
Note the single * in the comment.
This would seem to indicate missing intermediate patches, or patches
from different trees / times.
A coherent patch set is needed for review
Regards
Mike
On Wed, 9 Feb 2022 at 10:57, Mao Jinlong <quic_jinlmao@quicinc.com> wrote:
>
> TPDM serves as data collection component for various dataset types.
> DSB(Discrete Single Bit) is one of the dataset types. DSB subunit
> can be enabled for data collection by writing 1 to the first bit of
> DSB_CR register. This change is to add enable/disable function for
> DSB dataset by writing DSB_CR register.
>
> Signed-off-by: Tao Zhang <quic_taozha@quicinc.com>
> Signed-off-by: Mao Jinlong <quic_jinlmao@quicinc.com>
> ---
> drivers/hwtracing/coresight/coresight-tpdm.c | 57 ++++++++++++++++++++
> drivers/hwtracing/coresight/coresight-tpdm.h | 21 ++++++++
> 2 files changed, 78 insertions(+)
>
> diff --git a/drivers/hwtracing/coresight/coresight-tpdm.c b/drivers/hwtracing/coresight/coresight-tpdm.c
> index 51b8b17e6a80..c6480b7389b0 100644
> --- a/drivers/hwtracing/coresight/coresight-tpdm.c
> +++ b/drivers/hwtracing/coresight/coresight-tpdm.c
> @@ -20,7 +20,28 @@
>
> DEFINE_CORESIGHT_DEVLIST(tpdm_devs, "tpdm");
>
> +static void tpdm_enable_dsb(struct tpdm_drvdata *drvdata)
> +{
> + u32 val;
> +
> + /* Set the enable bit of DSB control register to 1 */
> + val = readl_relaxed(drvdata->base + TPDM_DSB_CR);
> + val = val | BIT(0);
> + writel_relaxed(val, drvdata->base + TPDM_DSB_CR);
> +}
> +
> /** TPDM enable operations **/
> +static void _tpdm_enable(struct tpdm_drvdata *drvdata)
> +{
> + CS_UNLOCK(drvdata->base);
> +
> + /* Check if DSB datasets is present for TPDM. */
> + if (test_bit(TPDM_DS_DSB, drvdata->datasets))
> + tpdm_enable_dsb(drvdata);
> +
> + CS_LOCK(drvdata->base);
> +}
> +
> static int tpdm_enable(struct coresight_device *csdev,
> struct perf_event *event, u32 mode)
> {
> @@ -32,6 +53,7 @@ static int tpdm_enable(struct coresight_device *csdev,
> return -EBUSY;
> }
>
> + _tpdm_enable(drvdata);
> drvdata->enable = true;
> mutex_unlock(&drvdata->lock);
>
> @@ -39,7 +61,29 @@ static int tpdm_enable(struct coresight_device *csdev,
> return 0;
> }
>
> +static void tpdm_disable_dsb(struct tpdm_drvdata *drvdata)
> +{
> + u32 val;
> +
> + /* Set the enable bit of DSB control register to 0 */
> + val = readl_relaxed(drvdata->base + TPDM_DSB_CR);
> + val = val & ~BIT(0);
> + writel_relaxed(val, drvdata->base + TPDM_DSB_CR);
> +}
> +
> /** TPDM disable operations **/
> +static void _tpdm_disable(struct tpdm_drvdata *drvdata)
> +{
> + CS_UNLOCK(drvdata->base);
> +
> + /* Check if DSB datasets is present for TPDM. */
> + if (test_bit(TPDM_DS_DSB, drvdata->datasets))
> + tpdm_disable_dsb(drvdata);
> +
> + CS_LOCK(drvdata->base);
> +
> +}
> +
> static void tpdm_disable(struct coresight_device *csdev,
> struct perf_event *event)
> {
> @@ -51,6 +95,7 @@ static void tpdm_disable(struct coresight_device *csdev,
> return;
> }
>
> + _tpdm_disable(drvdata);
> drvdata->enable = false;
> mutex_unlock(&drvdata->lock);
>
> @@ -76,7 +121,19 @@ static const struct coresight_ops tpdm_cs_ops = {
>
> static void tpdm_init_default_data(struct tpdm_drvdata *drvdata)
> {
> + int i;
> + u32 pidr;
> +
> drvdata->traceid = coresight_get_system_trace_id();
> +
> + CS_UNLOCK(drvdata->base);
> + /* Get the datasets present on the TPDM. */
> + pidr = readl_relaxed(drvdata->base + CORESIGHT_PERIPHIDR0);
> + for (i = 0; i < TPDM_DATASETS; i++) {
> + if (pidr & BIT(i))
> + __set_bit(i, drvdata->datasets);
> + }
> + CS_LOCK(drvdata->base);
> }
>
> static int tpdm_probe(struct amba_device *adev, const struct amba_id *id)
> diff --git a/drivers/hwtracing/coresight/coresight-tpdm.h b/drivers/hwtracing/coresight/coresight-tpdm.h
> index 2effbabf349b..cb3ddc6c89ae 100644
> --- a/drivers/hwtracing/coresight/coresight-tpdm.h
> +++ b/drivers/hwtracing/coresight/coresight-tpdm.h
> @@ -6,6 +6,25 @@
> #ifndef _CORESIGHT_CORESIGHT_TPDM_H
> #define _CORESIGHT_CORESIGHT_TPDM_H
>
> +/* The max number of the datasets that TPDM supports */
> +#define TPDM_DATASETS 7
> +
> +/* DSB Subunit Registers */
> +#define TPDM_DSB_CR (0x780)
> +
> +/**
> + * This enum is for PERIPHIDR0 register of TPDM.
> + * The fields [6:0] of PERIPHIDR0 are used to determine what
> + * interfaces and subunits are present on a given TPDM.
> + *
> + * PERIPHIDR0[0] : Fix to 1 if ImplDef subunit present, else 0
> + * PERIPHIDR0[1] : Fix to 1 if DSB subunit present, else 0
> + */
> +enum tpdm_dataset {
> + TPDM_DS_IMPLDEF,
> + TPDM_DS_DSB,
> +};
> +
> /**
> * struct tpdm_drvdata - specifics associated to an TPDM component
> * @base: memory mapped base address for this component.
> @@ -13,6 +32,7 @@
> * @csdev: component vitals needed by the framework.
> * @lock: lock for the enable value.
> * @enable: enable status of the component.
> + * @datasets: The datasets types present of the TPDM.
> * @traceid: value of the current ID for this component.
> */
>
> @@ -22,6 +42,7 @@ struct tpdm_drvdata {
> struct coresight_device *csdev;
> struct mutex lock;
> bool enable;
> + DECLARE_BITMAP(datasets, TPDM_DATASETS);
> int traceid;
> };
>
> --
> 2.17.1
>
--
Mike Leach
Principal Engineer, ARM Ltd.
Manchester Design Centre. UK
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH v3 06/10] coresight-tpdm: Add integration test support
2022-02-09 10:56 [PATCH v3 00/10] Coresight: Add support for TPDM and TPDA Mao Jinlong
` (4 preceding siblings ...)
2022-02-09 10:57 ` [PATCH v3 05/10] coresight-tpdm: Add DSB dataset support Mao Jinlong
@ 2022-02-09 10:57 ` Mao Jinlong
2022-02-09 10:57 ` [PATCH v3 07/10] docs: sysfs: coresight: Add sysfs ABI documentation for TPDM Mao Jinlong
` (4 subsequent siblings)
10 siblings, 0 replies; 22+ messages in thread
From: Mao Jinlong @ 2022-02-09 10:57 UTC (permalink / raw)
To: Mathieu Poirier, Suzuki K Poulose, Alexander Shishkin
Cc: Mao Jinlong, Mike Leach, Leo Yan, Greg Kroah-Hartman, coresight,
linux-arm-kernel, linux-kernel, Tingwei Zhang, Yuanfang Zhang,
Tao Zhang, Trilok Soni, Hao Zhang, linux-arm-msm
Integration test for tpdm can help to generate the data for
verification of the topology during TPDM software bring up.
Sample:
echo 1 > /sys/bus/coresight/devices/tmc_etf0/enable_sink
echo 1 > /sys/bus/coresight/devices/tpdm1/enable_source
echo 1 > /sys/bus/coresight/devices/tpdm1/integration_test
echo 2 > /sys/bus/coresight/devices/tpdm1/integration_test
cat /dev/tmc_etf0 > /data/etf-tpdm1.bin
Signed-off-by: Tao Zhang <quic_taozha@quicinc.com>
Signed-off-by: Mao Jinlong <quic_jinlmao@quicinc.com>
---
drivers/hwtracing/coresight/Kconfig | 9 ++++
drivers/hwtracing/coresight/coresight-tpdm.c | 54 ++++++++++++++++++++
drivers/hwtracing/coresight/coresight-tpdm.h | 8 +++
3 files changed, 71 insertions(+)
diff --git a/drivers/hwtracing/coresight/Kconfig b/drivers/hwtracing/coresight/Kconfig
index 5c506a1cd08f..60248fef4089 100644
--- a/drivers/hwtracing/coresight/Kconfig
+++ b/drivers/hwtracing/coresight/Kconfig
@@ -214,4 +214,13 @@ config CORESIGHT_TPDM
To compile this driver as a module, choose M here: the module will be
called coresight-tpdm.
+config CORESIGHT_TPDM_INTEGRATION_TEST
+ bool "Enable CoreSight Integration Test For TPDM"
+ depends on CORESIGHT_TPDM
+ help
+ This option adds support for the CoreSight integration test on this
+ devie. Coresight architecture provides integration control modes of
+ operation to facilitate integration testing and software bringup
+ and/or to instrument topology discovery. The TPDM utilizes integration
+ mode to accomplish integration testing and software bringup.
endif
diff --git a/drivers/hwtracing/coresight/coresight-tpdm.c b/drivers/hwtracing/coresight/coresight-tpdm.c
index c6480b7389b0..7a2b9097b470 100644
--- a/drivers/hwtracing/coresight/coresight-tpdm.c
+++ b/drivers/hwtracing/coresight/coresight-tpdm.c
@@ -136,6 +136,59 @@ static void tpdm_init_default_data(struct tpdm_drvdata *drvdata)
CS_LOCK(drvdata->base);
}
+#ifdef CONFIG_CORESIGHT_TPDM_INTEGRATION_TEST
+static ssize_t integration_test_store(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf,
+ size_t size)
+{
+ int i, ret = 0;
+ unsigned long val;
+ struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent);
+
+ ret = kstrtoul(buf, 10, &val);
+ if (ret)
+ return ret;
+
+ if (val != 1 && val != 2)
+ return -EINVAL;
+
+ if (!drvdata->enable)
+ return -EINVAL;
+
+ if (val == 1)
+ val = ATBCNTRL_VAL_64;
+ else
+ val = ATBCNTRL_VAL_32;
+ CS_UNLOCK(drvdata->base);
+ writel_relaxed(0x1, drvdata->base + TPDM_ITCNTRL);
+
+ for (i = 1; i < 5; i++)
+ writel_relaxed(val, drvdata->base + TPDM_ITATBCNTRL);
+
+ writel_relaxed(0, drvdata->base + TPDM_ITCNTRL);
+ CS_LOCK(drvdata->base);
+ return size;
+}
+static DEVICE_ATTR_WO(integration_test);
+#endif /* CORESIGHT_TPDM_INTEGRATION_TEST */
+
+static struct attribute *tpdm_attrs[] = {
+#ifdef CONFIG_CORESIGHT_TPDM_INTEGRATION_TEST
+ &dev_attr_integration_test.attr,
+#endif /* CORESIGHT_TPDM_INTEGRATION_TEST */
+ NULL,
+};
+
+static struct attribute_group tpdm_attr_grp = {
+ .attrs = tpdm_attrs,
+};
+
+static const struct attribute_group *tpdm_attr_grps[] = {
+ &tpdm_attr_grp,
+ NULL,
+};
+
static int tpdm_probe(struct amba_device *adev, const struct amba_id *id)
{
struct device *dev = &adev->dev;
@@ -171,6 +224,7 @@ static int tpdm_probe(struct amba_device *adev, const struct amba_id *id)
desc.ops = &tpdm_cs_ops;
desc.pdata = adev->dev.platform_data;
desc.dev = &adev->dev;
+ desc.groups = tpdm_attr_grps;
drvdata->csdev = coresight_register(&desc);
if (IS_ERR(drvdata->csdev))
return PTR_ERR(drvdata->csdev);
diff --git a/drivers/hwtracing/coresight/coresight-tpdm.h b/drivers/hwtracing/coresight/coresight-tpdm.h
index cb3ddc6c89ae..128fcff37192 100644
--- a/drivers/hwtracing/coresight/coresight-tpdm.h
+++ b/drivers/hwtracing/coresight/coresight-tpdm.h
@@ -12,6 +12,14 @@
/* DSB Subunit Registers */
#define TPDM_DSB_CR (0x780)
+/* TPDM integration test registers */
+#define TPDM_ITATBCNTRL (0xEF0)
+#define TPDM_ITCNTRL (0xF00)
+
+/* Register value for integration test */
+#define ATBCNTRL_VAL_32 0xC00F1409
+#define ATBCNTRL_VAL_64 0xC01F1409
+
/**
* This enum is for PERIPHIDR0 register of TPDM.
* The fields [6:0] of PERIPHIDR0 are used to determine what
--
2.17.1
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH v3 07/10] docs: sysfs: coresight: Add sysfs ABI documentation for TPDM
2022-02-09 10:56 [PATCH v3 00/10] Coresight: Add support for TPDM and TPDA Mao Jinlong
` (5 preceding siblings ...)
2022-02-09 10:57 ` [PATCH v3 06/10] coresight-tpdm: Add integration test support Mao Jinlong
@ 2022-02-09 10:57 ` Mao Jinlong
2022-02-09 10:57 ` [PATCH v3 08/10] Coresight: Add TPDA link driver Mao Jinlong
` (3 subsequent siblings)
10 siblings, 0 replies; 22+ messages in thread
From: Mao Jinlong @ 2022-02-09 10:57 UTC (permalink / raw)
To: Mathieu Poirier, Suzuki K Poulose, Alexander Shishkin
Cc: Mao Jinlong, Mike Leach, Leo Yan, Greg Kroah-Hartman, coresight,
linux-arm-kernel, linux-kernel, Tingwei Zhang, Yuanfang Zhang,
Tao Zhang, Trilok Soni, Hao Zhang, linux-arm-msm
Add API usage document for sysfs API in TPDM driver.
Signed-off-by: Mao Jinlong <quic_jinlmao@quicinc.com>
---
Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm | 6 ++++++
1 file changed, 6 insertions(+)
create mode 100644 Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm
diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm
new file mode 100644
index 000000000000..da6c2c336e10
--- /dev/null
+++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm
@@ -0,0 +1,6 @@
+What: /sys/bus/coresight/devices/<tpdm-name>/integration_test
+Date: February 2022
+KernelVersion 5.17
+Contact: Jinlong Mao or Tao Zhang
+Description: (Write) Run integration test for tpdm.
+
--
2.17.1
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH v3 08/10] Coresight: Add TPDA link driver
2022-02-09 10:56 [PATCH v3 00/10] Coresight: Add support for TPDM and TPDA Mao Jinlong
` (6 preceding siblings ...)
2022-02-09 10:57 ` [PATCH v3 07/10] docs: sysfs: coresight: Add sysfs ABI documentation for TPDM Mao Jinlong
@ 2022-02-09 10:57 ` Mao Jinlong
2022-02-09 10:57 ` [PATCH v3 09/10] dt-bindings: arm: Adds CoreSight TPDA hardware definitions Mao Jinlong
` (2 subsequent siblings)
10 siblings, 0 replies; 22+ messages in thread
From: Mao Jinlong @ 2022-02-09 10:57 UTC (permalink / raw)
To: Mathieu Poirier, Suzuki K Poulose, Alexander Shishkin
Cc: Mao Jinlong, Mike Leach, Leo Yan, Greg Kroah-Hartman, coresight,
linux-arm-kernel, linux-kernel, Tingwei Zhang, Yuanfang Zhang,
Tao Zhang, Trilok Soni, Hao Zhang, linux-arm-msm
TPDA(Trace, Profiling and Diagnostics Aggregator) is
to provide packetization, funneling and timestamping of
TPDM data. Multiple monitors are connected to different
input ports of TPDA.This change is to add tpda
enable/disable/probe functions for coresight tpda driver.
- - - - - - - - - - - -
| TPDM 0| | TPDM 1 | | TPDM 2|
- - - - - - - - - - - -
| | |
|_ _ _ _ _ _ | _ _ _ _ |
| | |
| | |
------------------
| TPDA |
------------------
|
|
------------------
| Trace Funnel |
------------------
Signed-off-by: Tao Zhang <quic_taozha@quicinc.com>
Signed-off-by: Mao Jinlong <quic_jinlmao@quicinc.com>
---
drivers/hwtracing/coresight/Kconfig | 11 ++
drivers/hwtracing/coresight/Makefile | 1 +
drivers/hwtracing/coresight/coresight-tpda.c | 193 +++++++++++++++++++
drivers/hwtracing/coresight/coresight-tpda.h | 32 +++
4 files changed, 237 insertions(+)
create mode 100644 drivers/hwtracing/coresight/coresight-tpda.c
create mode 100644 drivers/hwtracing/coresight/coresight-tpda.h
diff --git a/drivers/hwtracing/coresight/Kconfig b/drivers/hwtracing/coresight/Kconfig
index 60248fef4089..317c5e7f4819 100644
--- a/drivers/hwtracing/coresight/Kconfig
+++ b/drivers/hwtracing/coresight/Kconfig
@@ -223,4 +223,15 @@ config CORESIGHT_TPDM_INTEGRATION_TEST
operation to facilitate integration testing and software bringup
and/or to instrument topology discovery. The TPDM utilizes integration
mode to accomplish integration testing and software bringup.
+
+config CORESIGHT_TPDA
+ tristate "CoreSight Trace, Profiling & Diagnostics Aggregator driver"
+ help
+ This driver provides support for configuring aggregator. This is
+ primarily useful for pulling the data sets from one or more
+ attached monitors and pushing the resultant data out. Multiple
+ monitors are connected on different input ports of TPDA.
+
+ To compile this driver as a module, choose M here: the module will be
+ called coresight-tpda.
endif
diff --git a/drivers/hwtracing/coresight/Makefile b/drivers/hwtracing/coresight/Makefile
index e7392a0dddeb..cd8079ec276d 100644
--- a/drivers/hwtracing/coresight/Makefile
+++ b/drivers/hwtracing/coresight/Makefile
@@ -26,5 +26,6 @@ obj-$(CONFIG_CORESIGHT_CATU) += coresight-catu.o
obj-$(CONFIG_CORESIGHT_CTI) += coresight-cti.o
obj-$(CONFIG_CORESIGHT_TRBE) += coresight-trbe.o
obj-$(CONFIG_CORESIGHT_TPDM) += coresight-tpdm.o
+obj-$(CONFIG_CORESIGHT_TPDA) += coresight-tpda.o
coresight-cti-y := coresight-cti-core.o coresight-cti-platform.o \
coresight-cti-sysfs.o
diff --git a/drivers/hwtracing/coresight/coresight-tpda.c b/drivers/hwtracing/coresight/coresight-tpda.c
new file mode 100644
index 000000000000..c86ae5cdc3e0
--- /dev/null
+++ b/drivers/hwtracing/coresight/coresight-tpda.c
@@ -0,0 +1,193 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include <linux/amba/bus.h>
+#include <linux/bitmap.h>
+#include <linux/coresight.h>
+#include <linux/device.h>
+#include <linux/err.h>
+#include <linux/fs.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+
+#include "coresight-priv.h"
+#include "coresight-tpda.h"
+
+DEFINE_CORESIGHT_DEVLIST(tpda_devs, "tpda");
+
+/* Settings pre enabling port control register */
+static void tpda_enable_pre_port(struct tpda_drvdata *drvdata)
+{
+ u32 val;
+
+ val = readl_relaxed(drvdata->base + TPDA_CR);
+ val |= (drvdata->atid << 6);
+ writel_relaxed(val, drvdata->base + TPDA_CR);
+}
+
+static void tpda_enable_port(struct tpda_drvdata *drvdata, int port)
+{
+ u32 val;
+
+ val = readl_relaxed(drvdata->base + TPDA_Pn_CR(port));
+ /* Enable the port */
+ val = val | BIT(0);
+ writel_relaxed(val, drvdata->base + TPDA_Pn_CR(port));
+}
+
+static void _tpda_enable(struct tpda_drvdata *drvdata, int port)
+{
+ CS_UNLOCK(drvdata->base);
+
+ if (!drvdata->enable)
+ tpda_enable_pre_port(drvdata);
+
+ tpda_enable_port(drvdata, port);
+
+ CS_LOCK(drvdata->base);
+}
+
+static int tpda_enable(struct coresight_device *csdev, int inport, int outport)
+{
+ struct tpda_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
+
+ mutex_lock(&drvdata->lock);
+ _tpda_enable(drvdata, inport);
+ drvdata->enable = true;
+ mutex_unlock(&drvdata->lock);
+
+ dev_info(drvdata->dev, "TPDA inport %d enabled\n", inport);
+ return 0;
+}
+
+static void _tpda_disable(struct tpda_drvdata *drvdata, int port)
+{
+ u32 val;
+
+ CS_UNLOCK(drvdata->base);
+
+ val = readl_relaxed(drvdata->base + TPDA_Pn_CR(port));
+ val = val & ~BIT(0);
+ writel_relaxed(val, drvdata->base + TPDA_Pn_CR(port));
+
+ CS_LOCK(drvdata->base);
+}
+
+static void tpda_disable(struct coresight_device *csdev, int inport,
+ int outport)
+{
+ struct tpda_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
+
+ mutex_lock(&drvdata->lock);
+ _tpda_disable(drvdata, inport);
+ drvdata->enable = false;
+ mutex_unlock(&drvdata->lock);
+
+ dev_info(drvdata->dev, "TPDA inport %d disabled\n", inport);
+}
+
+static const struct coresight_ops_link tpda_link_ops = {
+ .enable = tpda_enable,
+ .disable = tpda_disable,
+};
+
+static const struct coresight_ops tpda_cs_ops = {
+ .link_ops = &tpda_link_ops,
+};
+
+static int tpda_parse_of_data(struct tpda_drvdata *drvdata)
+{
+ int ret;
+ struct device_node *node = drvdata->dev->of_node;
+
+ /*
+ * TPDA must has a unique atid. This atid can uniquely
+ * identify the TPDM trace source connect to the TPDA.
+ */
+ ret = of_property_read_u32(node, "qcom,tpda-atid", &drvdata->atid);
+ if (ret) {
+ dev_err(drvdata->dev, "TPDA ATID is not specified\n");
+ return -EINVAL;
+ }
+ return 0;
+}
+
+static int tpda_probe(struct amba_device *adev, const struct amba_id *id)
+{
+ int ret;
+ struct device *dev = &adev->dev;
+ struct coresight_platform_data *pdata;
+ struct tpda_drvdata *drvdata;
+ struct coresight_desc desc = { 0 };
+
+ pdata = coresight_get_platform_data(dev);
+ if (IS_ERR(pdata))
+ return PTR_ERR(pdata);
+ adev->dev.platform_data = pdata;
+
+ drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
+ if (!drvdata)
+ return -ENOMEM;
+
+ drvdata->dev = &adev->dev;
+ dev_set_drvdata(dev, drvdata);
+
+ drvdata->base = devm_ioremap_resource(dev, &adev->res);
+ if (!drvdata->base)
+ return -ENOMEM;
+
+ mutex_init(&drvdata->lock);
+
+ ret = tpda_parse_of_data(drvdata);
+ if (ret)
+ return ret;
+
+ desc.name = coresight_alloc_device_name(&tpda_devs, dev);
+ if (!desc.name)
+ return -ENOMEM;
+ desc.type = CORESIGHT_DEV_TYPE_LINK;
+ desc.subtype.link_subtype = CORESIGHT_DEV_SUBTYPE_LINK_MERG;
+ desc.ops = &tpda_cs_ops;
+ desc.pdata = adev->dev.platform_data;
+ desc.dev = &adev->dev;
+ drvdata->csdev = coresight_register(&desc);
+ if (IS_ERR(drvdata->csdev))
+ return PTR_ERR(drvdata->csdev);
+
+ pm_runtime_put(&adev->dev);
+
+ dev_dbg(drvdata->dev, "TPDA initialized\n");
+ return 0;
+}
+
+/*
+ * Different TPDA has different periph id.
+ * The difference is 0-7 bits' value. So ignore 0-7 bits.
+ */
+static struct amba_id tpda_ids[] = {
+ {
+ .id = 0x000f0f00,
+ .mask = 0x000fff00,
+ },
+ { 0, 0},
+};
+
+static struct amba_driver tpda_driver = {
+ .drv = {
+ .name = "coresight-tpda",
+ .owner = THIS_MODULE,
+ .suppress_bind_attrs = true,
+ },
+ .probe = tpda_probe,
+ .id_table = tpda_ids,
+};
+
+module_amba_driver(tpda_driver);
+
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("Trace, Profiling & Diagnostic Aggregator driver");
diff --git a/drivers/hwtracing/coresight/coresight-tpda.h b/drivers/hwtracing/coresight/coresight-tpda.h
new file mode 100644
index 000000000000..6ac33b9c1ea4
--- /dev/null
+++ b/drivers/hwtracing/coresight/coresight-tpda.h
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef _CORESIGHT_CORESIGHT_TPDA_H
+#define _CORESIGHT_CORESIGHT_TPDA_H
+
+#define TPDA_CR (0x000)
+#define TPDA_Pn_CR(n) (0x004 + (n * 4))
+
+#define TPDA_MAX_INPORTS 32
+
+/**
+ * struct tpda_drvdata - specifics associated to an TPDA component
+ * @base: memory mapped base address for this component.
+ * @dev: The device entity associated to this component.
+ * @csdev: component vitals needed by the framework.
+ * @lock: lock for the enable value.
+ * @enable: enable status of the component.
+ * @traceid: trace source identification for the data packet by TPDA.
+ */
+struct tpda_drvdata {
+ void __iomem *base;
+ struct device *dev;
+ struct coresight_device *csdev;
+ struct mutex lock;
+ bool enable;
+ u32 atid;
+};
+
+#endif /* _CORESIGHT_CORESIGHT_TPDA_H */
--
2.17.1
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH v3 09/10] dt-bindings: arm: Adds CoreSight TPDA hardware definitions
2022-02-09 10:56 [PATCH v3 00/10] Coresight: Add support for TPDM and TPDA Mao Jinlong
` (7 preceding siblings ...)
2022-02-09 10:57 ` [PATCH v3 08/10] Coresight: Add TPDA link driver Mao Jinlong
@ 2022-02-09 10:57 ` Mao Jinlong
2022-02-09 10:57 ` [PATCH v3 10/10] ARM: dts: msm: Add coresight components for SM8250 Mao Jinlong
2022-02-10 10:30 ` [PATCH v3 00/10] Coresight: Add support for TPDM and TPDA Mike Leach
10 siblings, 0 replies; 22+ messages in thread
From: Mao Jinlong @ 2022-02-09 10:57 UTC (permalink / raw)
To: Mathieu Poirier, Suzuki K Poulose, Alexander Shishkin
Cc: Mao Jinlong, Mike Leach, Leo Yan, Greg Kroah-Hartman, coresight,
linux-arm-kernel, linux-kernel, Tingwei Zhang, Yuanfang Zhang,
Tao Zhang, Trilok Soni, Hao Zhang, linux-arm-msm
Adds new coresight-tpda.yaml file describing the bindings required
to define tpda in the device trees.
Signed-off-by: Tao Zhang <quic_taozha@quicinc.com>
Signed-off-by: Mao Jinlong <quic_jinlmao@quicinc.com>
---
.../bindings/arm/coresight-tpda.yaml | 129 ++++++++++++++++++
1 file changed, 129 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/coresight-tpda.yaml
diff --git a/Documentation/devicetree/bindings/arm/coresight-tpda.yaml b/Documentation/devicetree/bindings/arm/coresight-tpda.yaml
new file mode 100644
index 000000000000..311a70a1fcc6
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/coresight-tpda.yaml
@@ -0,0 +1,129 @@
+# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
+# Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/coresight-tpda.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Trace, Profiling and Diagnostics Aggregator - TPDA
+
+description: |
+ TPDAs are responsible for packetization and timestamping of data sets
+ utilizing the MIPI STPv2 packet protocol. Pulling data sets from one or
+ more attached TPDM and pushing the resultant (packetized) data out a
+ master ATB interface. Performing an arbitrated ATB interleaving (funneling)
+ task for free-flowing data from TPDM (i.e. CMB and DSB data set flows).
+
+maintainers:
+ - Suzuki K Poulose <suzuki.poulose@arm.com>
+ - Mathieu Poirier <mathieu.poirier@linaro.org>
+
+properties:
+ $nodename:
+ pattern: "^tpda(@[0-9a-f]+)$"
+ compatible:
+ items:
+ - const: qcom,coresight-tpda
+ - const: arm,primecell
+
+ reg:
+ maxItems: 1
+
+ qcom,tpda-atid:
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ maxItems: 1
+ description: |
+ Use the ATID field for trace source identification. This allows
+ multiple TPDMs to be interleaved and formatted via the Coresight
+ trace formatter framing protocol and de-formatted/parsed on a host
+ or debugger.
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ items:
+ - const: apb_pclk
+
+ in-ports:
+ type: object
+ description: |
+ Input connections from TPDM to TPDA
+ $ref: /schemas/graph.yaml#/properties/ports
+
+ properties:
+ '#address-cells':
+ const: 1
+
+ '#size-cells':
+ const: 0
+
+ patternProperties:
+ "^port@[0-9a-f]+$":
+ type: object
+ required:
+ - reg
+
+ required:
+ - '#size-cells'
+ - '#address-cells'
+
+ out-ports:
+ type: object
+ description: |
+ Output connections from the TPDA to legacy CoreSight trace bus.
+ $ref: /schemas/graph.yaml#/properties/ports
+
+ properties:
+ port:
+ description:
+ Output connection from the TPDA to legacy CoreSight Trace bus.
+ $ref: /schemas/graph.yaml#/properties/port
+
+required:
+ - compatible
+ - reg
+ - qcom,tpda-atid
+ - clocks
+ - clock-names
+ - in-ports
+ - out-ports
+
+additionalProperties: false
+
+examples:
+ # minimum tpda definition.
+ - |
+ tpda@6004000 {
+ compatible = "qcom,coresight-tpda", "arm,primecell";
+ reg = <0x6004000 0x1000>;
+
+ qcom,tpda-atid = <65>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ tpda_qdss_0_in_tpdm_dcc: endpoint {
+ remote-endpoint =
+ <&tpdm_dcc_out_tpda_qdss_0>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ tpda_qdss_out_funnel_in0: endpoint {
+ remote-endpoint =
+ <&funnel_in0_in_tpda_qdss>;
+ };
+ };
+ };
+ };
+
+...
--
2.17.1
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH v3 10/10] ARM: dts: msm: Add coresight components for SM8250
2022-02-09 10:56 [PATCH v3 00/10] Coresight: Add support for TPDM and TPDA Mao Jinlong
` (8 preceding siblings ...)
2022-02-09 10:57 ` [PATCH v3 09/10] dt-bindings: arm: Adds CoreSight TPDA hardware definitions Mao Jinlong
@ 2022-02-09 10:57 ` Mao Jinlong
2022-02-18 16:10 ` Mike Leach
2022-02-10 10:30 ` [PATCH v3 00/10] Coresight: Add support for TPDM and TPDA Mike Leach
10 siblings, 1 reply; 22+ messages in thread
From: Mao Jinlong @ 2022-02-09 10:57 UTC (permalink / raw)
To: Mathieu Poirier, Suzuki K Poulose, Alexander Shishkin
Cc: Mao Jinlong, Mike Leach, Leo Yan, Greg Kroah-Hartman, coresight,
linux-arm-kernel, linux-kernel, Tingwei Zhang, Yuanfang Zhang,
Tao Zhang, Trilok Soni, Hao Zhang, linux-arm-msm
Add coresight device tree for sm8250. STM/ETM/TPDM are added.
Signed-off-by: Tao Zhang <quic_taozha@quicinc.com>
Signed-off-by: Mao Jinlong <quic_jinlmao@quicinc.com>
---
.../arm64/boot/dts/qcom/sm8250-coresight.dtsi | 690 ++++++++++++++++++
arch/arm64/boot/dts/qcom/sm8250.dtsi | 2 +
2 files changed, 692 insertions(+)
create mode 100644 arch/arm64/boot/dts/qcom/sm8250-coresight.dtsi
diff --git a/arch/arm64/boot/dts/qcom/sm8250-coresight.dtsi b/arch/arm64/boot/dts/qcom/sm8250-coresight.dtsi
new file mode 100644
index 000000000000..732dab7f8674
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sm8250-coresight.dtsi
@@ -0,0 +1,690 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+&soc {
+
+ stm@6002000 {
+ compatible = "arm,coresight-stm", "arm,primecell";
+ reg = <0 0x06002000 0 0x1000>,
+ <0 0x16280000 0 0x180000>;
+ reg-names = "stm-base", "stm-stimulus-base";
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ port {
+ stm_out: endpoint {
+ remote-endpoint =
+ <&funnel0_in7>;
+ };
+ };
+ };
+ };
+
+ funnel@6041000 {
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+ reg = <0 0x06041000 0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ port {
+ funnel0_out: endpoint {
+ remote-endpoint =
+ <&merge_funnel_in0>;
+ };
+ };
+ };
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@6 {
+ reg = <6>;
+ funnel_in0_in_funnel_qatb: endpoint {
+ remote-endpoint =
+ <&funnel_qatb_out_funnel_in0>;
+ };
+ };
+
+ port@7 {
+ reg = <7>;
+ funnel0_in7: endpoint {
+ remote-endpoint = <&stm_out>;
+ };
+ };
+ };
+ };
+
+ funnel@6042000 {
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+ reg = <0 0x06042000 0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ port {
+ funnel2_out: endpoint {
+ remote-endpoint =
+ <&merge_funnel_in2>;
+ };
+ };
+ };
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@2 {
+ reg = <4>;
+ funnel2_in5: endpoint {
+ remote-endpoint =
+ <&apss_merge_funnel_out>;
+ };
+ };
+ };
+ };
+
+ funnel@6b04000 {
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+ arm,primecell-periphid = <0x000bb908>;
+
+ reg = <0 0x6b04000 0 0x1000>;
+ reg-names = "funnel-base";
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ port {
+ merge_funnel_out: endpoint {
+ remote-endpoint =
+ <&etf_in>;
+ };
+ };
+ };
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@7 {
+ reg = <7>;
+ funnel_swao_in_funnel_merg: endpoint {
+ remote-endpoint=
+ <&funnel_merg_out_funnel_swao>;
+ };
+ };
+ };
+
+ };
+
+ funnel@6045000 {
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+ reg = <0 0x06045000 0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ port {
+ funnel_merg_out_funnel_swao: endpoint {
+ remote-endpoint = <&funnel_swao_in_funnel_merg>;
+ };
+ };
+ };
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ reg = <0>;
+ merge_funnel_in0: endpoint {
+ remote-endpoint =
+ <&funnel0_out>;
+ };
+ };
+
+ port@2 {
+ reg = <1>;
+ merge_funnel_in2: endpoint {
+ remote-endpoint =
+ <&funnel2_out>;
+ };
+ };
+ };
+ };
+
+ replicator@6046000 {
+ compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
+ reg = <0 0x06046000 0 0x1000>;
+
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ port {
+ replicator_out: endpoint {
+ remote-endpoint = <&etr_in>;
+ };
+ };
+ };
+
+ in-ports {
+ port {
+ replicator_cx_in_swao_out: endpoint {
+ remote-endpoint = <&replicator_swao_out_cx_in>;
+ };
+ };
+ };
+ };
+
+ replicator@6b06000 {
+ compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
+ reg = <0 0x06b06000 0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ port {
+ replicator_swao_out_cx_in: endpoint {
+ remote-endpoint = <&replicator_cx_in_swao_out>;
+ };
+ };
+ };
+
+ in-ports {
+ port {
+ replicator_in: endpoint {
+ remote-endpoint = <&etf_out>;
+ };
+ };
+ };
+ };
+
+ etf@6b05000 {
+ compatible = "arm,coresight-tmc", "arm,primecell";
+ reg = <0 0x6b05000 0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ port {
+ etf_out: endpoint {
+ remote-endpoint =
+ <&replicator_in>;
+ };
+ };
+ };
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ reg = <0>;
+ etf_in: endpoint {
+ remote-endpoint =
+ <&merge_funnel_out>;
+ };
+ };
+ };
+ };
+
+ etr@6048000 {
+ compatible = "arm,coresight-tmc", "arm,primecell";
+ reg = <0 0x06048000 0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ arm,scatter-gather;
+
+ in-ports {
+ port {
+ etr_in: endpoint {
+ remote-endpoint =
+ <&replicator_out>;
+ };
+ };
+ };
+ };
+
+ etm@7040000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0 0x07040000 0 0x1000>;
+
+ cpu = <&CPU0>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ arm,coresight-loses-context-with-cpu;
+
+ out-ports {
+ port {
+ etm0_out: endpoint {
+ remote-endpoint =
+ <&apss_funnel_in0>;
+ };
+ };
+ };
+ };
+
+ etm@7140000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0 0x07140000 0 0x1000>;
+
+ cpu = <&CPU1>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ arm,coresight-loses-context-with-cpu;
+
+ out-ports {
+ port {
+ etm1_out: endpoint {
+ remote-endpoint =
+ <&apss_funnel_in1>;
+ };
+ };
+ };
+ };
+
+ etm@7240000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0 0x07240000 0 0x1000>;
+
+ cpu = <&CPU2>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ arm,coresight-loses-context-with-cpu;
+
+ out-ports {
+ port {
+ etm2_out: endpoint {
+ remote-endpoint =
+ <&apss_funnel_in2>;
+ };
+ };
+ };
+ };
+
+ etm@7340000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0 0x07340000 0 0x1000>;
+
+ cpu = <&CPU3>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ arm,coresight-loses-context-with-cpu;
+
+ out-ports {
+ port {
+ etm3_out: endpoint {
+ remote-endpoint =
+ <&apss_funnel_in3>;
+ };
+ };
+ };
+ };
+
+ etm@7440000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0 0x07440000 0 0x1000>;
+
+ cpu = <&CPU4>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ arm,coresight-loses-context-with-cpu;
+
+ out-ports {
+ port {
+ etm4_out: endpoint {
+ remote-endpoint =
+ <&apss_funnel_in4>;
+ };
+ };
+ };
+ };
+
+ etm@7540000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0 0x07540000 0 0x1000>;
+
+ cpu = <&CPU5>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ arm,coresight-loses-context-with-cpu;
+
+ out-ports {
+ port {
+ etm5_out: endpoint {
+ remote-endpoint =
+ <&apss_funnel_in5>;
+ };
+ };
+ };
+ };
+
+ etm@7640000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0 0x07640000 0 0x1000>;
+
+ cpu = <&CPU6>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ arm,coresight-loses-context-with-cpu;
+
+ out-ports {
+ port {
+ etm6_out: endpoint {
+ remote-endpoint =
+ <&apss_funnel_in6>;
+ };
+ };
+ };
+ };
+
+ etm@7740000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0 0x07740000 0 0x1000>;
+
+ cpu = <&CPU7>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ arm,coresight-loses-context-with-cpu;
+
+ out-ports {
+ port {
+ etm7_out: endpoint {
+ remote-endpoint =
+ <&apss_funnel_in7>;
+ };
+ };
+ };
+ };
+
+ funnel@7800000 {
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+ reg = <0 0x07800000 0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ port {
+ apss_funnel_out: endpoint {
+ remote-endpoint =
+ <&apss_merge_funnel_in>;
+ };
+ };
+ };
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ apss_funnel_in0: endpoint {
+ remote-endpoint =
+ <&etm0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ apss_funnel_in1: endpoint {
+ remote-endpoint =
+ <&etm1_out>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+ apss_funnel_in2: endpoint {
+ remote-endpoint =
+ <&etm2_out>;
+ };
+ };
+
+ port@3 {
+ reg = <3>;
+ apss_funnel_in3: endpoint {
+ remote-endpoint =
+ <&etm3_out>;
+ };
+ };
+
+ port@4 {
+ reg = <4>;
+ apss_funnel_in4: endpoint {
+ remote-endpoint =
+ <&etm4_out>;
+ };
+ };
+
+ port@5 {
+ reg = <5>;
+ apss_funnel_in5: endpoint {
+ remote-endpoint =
+ <&etm5_out>;
+ };
+ };
+
+ port@6 {
+ reg = <6>;
+ apss_funnel_in6: endpoint {
+ remote-endpoint =
+ <&etm6_out>;
+ };
+ };
+
+ port@7 {
+ reg = <7>;
+ apss_funnel_in7: endpoint {
+ remote-endpoint =
+ <&etm7_out>;
+ };
+ };
+ };
+ };
+
+ funnel@7810000 {
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+ reg = <0 0x07810000 0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ port {
+ apss_merge_funnel_out: endpoint {
+ remote-endpoint =
+ <&funnel2_in5>;
+ };
+ };
+ };
+
+ in-ports {
+ port@1 {
+ reg = <0>;
+ apss_merge_funnel_in: endpoint {
+ remote-endpoint =
+ <&apss_funnel_out>;
+ };
+ };
+ };
+ };
+
+ tpdm_mm: mm.tpdm@6c08000 {
+ compatible = "arm,primecell";
+ reg = <0 0x6c08000 0 0x1000>;
+ reg-names = "tpdm-base";
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,msr-fix-req;
+
+ out-ports {
+ port {
+ tpdm_mm_out_funnel_dl_mm: endpoint {
+ remote-endpoint =
+ <&funnel_dl_mm_in_tpdm_mm>;
+ };
+ };
+ };
+ };
+
+ funnel@6c0b000 {
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+
+ reg = <0 0x6c0b000 0 0x1000>;
+ reg-names = "funnel-base";
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ port {
+ funnel_dl_mm_out_funnel_dl_center: endpoint {
+ remote-endpoint =
+ <&funnel_dl_center_in_funnel_dl_mm>;
+ };
+ };
+ };
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@3 {
+ reg = <3>;
+ funnel_dl_mm_in_tpdm_mm: endpoint {
+ remote-endpoint =
+ <&tpdm_mm_out_funnel_dl_mm>;
+ };
+ };
+ };
+ };
+
+ funnel@6c2d000 {
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+
+ reg = <0 0x6c2d000 0 0x1000>;
+ reg-names = "funnel-base";
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port {
+ tpdm_mm_out_tpda9: endpoint {
+ remote-endpoint =
+ <&tpda_9_in_tpdm_mm>;
+ };
+ };
+ };
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@2 {
+ reg = <2>;
+ funnel_dl_center_in_funnel_dl_mm: endpoint {
+ remote-endpoint =
+ <&funnel_dl_mm_out_funnel_dl_center>;
+ };
+ };
+ };
+ };
+
+ tpda@6004000 {
+ compatible = "arm,primecell";
+ reg = <0 0x6004000 0 0x1000>;
+ reg-names = "tpda-base";
+
+ qcom,tpda-atid = <65>;
+
+ qcom,dsb-elem-size = <9 32>,
+ <10 32>,
+ <14 32>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ port {
+ reg = <0>;
+ tpda_out_funnel_qatb: endpoint {
+ remote-endpoint =
+ <&funnel_qatb_in_tpda>;
+ };
+ };
+ };
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@9 {
+ reg = <9>;
+ tpda_9_in_tpdm_mm: endpoint {
+ remote-endpoint =
+ <&tpdm_mm_out_tpda9>;
+ };
+ };
+ };
+ };
+
+ funnel@6005000 {
+ compatible = "arm,primecell";
+
+ reg = <0 0x6005000 0 0x1000>;
+ reg-names = "funnel-base";
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ port {
+ funnel_qatb_out_funnel_in0: endpoint {
+ remote-endpoint =
+ <&funnel_in0_in_funnel_qatb>;
+ };
+ };
+ };
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ funnel_qatb_in_tpda: endpoint {
+ remote-endpoint =
+ <&tpda_out_funnel_qatb>;
+ };
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index 5617a46e5ccd..d1837e3df30a 100644
--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
@@ -5323,3 +5323,5 @@
};
};
};
+
+#include "sm8250-coresight.dtsi"
--
2.17.1
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH v3 10/10] ARM: dts: msm: Add coresight components for SM8250
2022-02-09 10:57 ` [PATCH v3 10/10] ARM: dts: msm: Add coresight components for SM8250 Mao Jinlong
@ 2022-02-18 16:10 ` Mike Leach
0 siblings, 0 replies; 22+ messages in thread
From: Mike Leach @ 2022-02-18 16:10 UTC (permalink / raw)
To: Mao Jinlong
Cc: Mathieu Poirier, Suzuki K Poulose, Alexander Shishkin, Leo Yan,
Greg Kroah-Hartman, coresight, linux-arm-kernel, linux-kernel,
Tingwei Zhang, Yuanfang Zhang, Tao Zhang, Trilok Soni, Hao Zhang,
linux-arm-msm
Hi,
It would appear here that normal coresight funnels appear between tpdm
and tpda devices. This is contrary to my understanding of your
hardware and the descriptions and conversations we had in patch 00/10
in this set.
trace path appears to be
tpdm_mm => funnel@6c0b000 => funnel@6c2d000 => tpda@6004000 =>
funnel@6005000 => rest of ATB
The documentation states that the TPDA is responsible for for
funneling and packetising - so why do we have extra funnels?
I have no way of knowing if that topology is right or wrong. Are the
funnels between tpdm and tpda actual coresight funnels, a component
that is register compatible with CS funnels but designed for the TPDM
/ TPDA transport, or the funnels are being used, but without driving
ATID from the sources.
It is difficult to review this set without better information on the
hardware represented.
Regards
Mike
On Wed, 9 Feb 2022 at 10:58, Mao Jinlong <quic_jinlmao@quicinc.com> wrote:
>
> Add coresight device tree for sm8250. STM/ETM/TPDM are added.
>
> Signed-off-by: Tao Zhang <quic_taozha@quicinc.com>
> Signed-off-by: Mao Jinlong <quic_jinlmao@quicinc.com>
> ---
> .../arm64/boot/dts/qcom/sm8250-coresight.dtsi | 690 ++++++++++++++++++
> arch/arm64/boot/dts/qcom/sm8250.dtsi | 2 +
> 2 files changed, 692 insertions(+)
> create mode 100644 arch/arm64/boot/dts/qcom/sm8250-coresight.dtsi
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8250-coresight.dtsi b/arch/arm64/boot/dts/qcom/sm8250-coresight.dtsi
> new file mode 100644
> index 000000000000..732dab7f8674
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/sm8250-coresight.dtsi
> @@ -0,0 +1,690 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
> + */
> +
> +&soc {
> +
> + stm@6002000 {
> + compatible = "arm,coresight-stm", "arm,primecell";
> + reg = <0 0x06002000 0 0x1000>,
> + <0 0x16280000 0 0x180000>;
> + reg-names = "stm-base", "stm-stimulus-base";
> +
> + clocks = <&aoss_qmp>;
> + clock-names = "apb_pclk";
> +
> + out-ports {
> + port {
> + stm_out: endpoint {
> + remote-endpoint =
> + <&funnel0_in7>;
> + };
> + };
> + };
> + };
> +
> + funnel@6041000 {
> + compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
> + reg = <0 0x06041000 0 0x1000>;
> +
> + clocks = <&aoss_qmp>;
> + clock-names = "apb_pclk";
> +
> + out-ports {
> + port {
> + funnel0_out: endpoint {
> + remote-endpoint =
> + <&merge_funnel_in0>;
> + };
> + };
> + };
> +
> + in-ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@6 {
> + reg = <6>;
> + funnel_in0_in_funnel_qatb: endpoint {
> + remote-endpoint =
> + <&funnel_qatb_out_funnel_in0>;
> + };
> + };
> +
> + port@7 {
> + reg = <7>;
> + funnel0_in7: endpoint {
> + remote-endpoint = <&stm_out>;
> + };
> + };
> + };
> + };
> +
> + funnel@6042000 {
> + compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
> + reg = <0 0x06042000 0 0x1000>;
> +
> + clocks = <&aoss_qmp>;
> + clock-names = "apb_pclk";
> +
> + out-ports {
> + port {
> + funnel2_out: endpoint {
> + remote-endpoint =
> + <&merge_funnel_in2>;
> + };
> + };
> + };
> +
> + in-ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@2 {
> + reg = <4>;
> + funnel2_in5: endpoint {
> + remote-endpoint =
> + <&apss_merge_funnel_out>;
> + };
> + };
> + };
> + };
> +
> + funnel@6b04000 {
> + compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
> + arm,primecell-periphid = <0x000bb908>;
> +
> + reg = <0 0x6b04000 0 0x1000>;
> + reg-names = "funnel-base";
> +
> + clocks = <&aoss_qmp>;
> + clock-names = "apb_pclk";
> +
> + out-ports {
> + port {
> + merge_funnel_out: endpoint {
> + remote-endpoint =
> + <&etf_in>;
> + };
> + };
> + };
> +
> + in-ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@7 {
> + reg = <7>;
> + funnel_swao_in_funnel_merg: endpoint {
> + remote-endpoint=
> + <&funnel_merg_out_funnel_swao>;
> + };
> + };
> + };
> +
> + };
> +
> + funnel@6045000 {
> + compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
> + reg = <0 0x06045000 0 0x1000>;
> +
> + clocks = <&aoss_qmp>;
> + clock-names = "apb_pclk";
> +
> + out-ports {
> + port {
> + funnel_merg_out_funnel_swao: endpoint {
> + remote-endpoint = <&funnel_swao_in_funnel_merg>;
> + };
> + };
> + };
> +
> + in-ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@1 {
> + reg = <0>;
> + merge_funnel_in0: endpoint {
> + remote-endpoint =
> + <&funnel0_out>;
> + };
> + };
> +
> + port@2 {
> + reg = <1>;
> + merge_funnel_in2: endpoint {
> + remote-endpoint =
> + <&funnel2_out>;
> + };
> + };
> + };
> + };
> +
> + replicator@6046000 {
> + compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
> + reg = <0 0x06046000 0 0x1000>;
> +
> +
> + clocks = <&aoss_qmp>;
> + clock-names = "apb_pclk";
> +
> + out-ports {
> + port {
> + replicator_out: endpoint {
> + remote-endpoint = <&etr_in>;
> + };
> + };
> + };
> +
> + in-ports {
> + port {
> + replicator_cx_in_swao_out: endpoint {
> + remote-endpoint = <&replicator_swao_out_cx_in>;
> + };
> + };
> + };
> + };
> +
> + replicator@6b06000 {
> + compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
> + reg = <0 0x06b06000 0 0x1000>;
> +
> + clocks = <&aoss_qmp>;
> + clock-names = "apb_pclk";
> +
> + out-ports {
> + port {
> + replicator_swao_out_cx_in: endpoint {
> + remote-endpoint = <&replicator_cx_in_swao_out>;
> + };
> + };
> + };
> +
> + in-ports {
> + port {
> + replicator_in: endpoint {
> + remote-endpoint = <&etf_out>;
> + };
> + };
> + };
> + };
> +
> + etf@6b05000 {
> + compatible = "arm,coresight-tmc", "arm,primecell";
> + reg = <0 0x6b05000 0 0x1000>;
> +
> + clocks = <&aoss_qmp>;
> + clock-names = "apb_pclk";
> +
> + out-ports {
> + port {
> + etf_out: endpoint {
> + remote-endpoint =
> + <&replicator_in>;
> + };
> + };
> + };
> +
> + in-ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@1 {
> + reg = <0>;
> + etf_in: endpoint {
> + remote-endpoint =
> + <&merge_funnel_out>;
> + };
> + };
> + };
> + };
> +
> + etr@6048000 {
> + compatible = "arm,coresight-tmc", "arm,primecell";
> + reg = <0 0x06048000 0 0x1000>;
> +
> + clocks = <&aoss_qmp>;
> + clock-names = "apb_pclk";
> + arm,scatter-gather;
> +
> + in-ports {
> + port {
> + etr_in: endpoint {
> + remote-endpoint =
> + <&replicator_out>;
> + };
> + };
> + };
> + };
> +
> + etm@7040000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + reg = <0 0x07040000 0 0x1000>;
> +
> + cpu = <&CPU0>;
> +
> + clocks = <&aoss_qmp>;
> + clock-names = "apb_pclk";
> + arm,coresight-loses-context-with-cpu;
> +
> + out-ports {
> + port {
> + etm0_out: endpoint {
> + remote-endpoint =
> + <&apss_funnel_in0>;
> + };
> + };
> + };
> + };
> +
> + etm@7140000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + reg = <0 0x07140000 0 0x1000>;
> +
> + cpu = <&CPU1>;
> +
> + clocks = <&aoss_qmp>;
> + clock-names = "apb_pclk";
> + arm,coresight-loses-context-with-cpu;
> +
> + out-ports {
> + port {
> + etm1_out: endpoint {
> + remote-endpoint =
> + <&apss_funnel_in1>;
> + };
> + };
> + };
> + };
> +
> + etm@7240000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + reg = <0 0x07240000 0 0x1000>;
> +
> + cpu = <&CPU2>;
> +
> + clocks = <&aoss_qmp>;
> + clock-names = "apb_pclk";
> + arm,coresight-loses-context-with-cpu;
> +
> + out-ports {
> + port {
> + etm2_out: endpoint {
> + remote-endpoint =
> + <&apss_funnel_in2>;
> + };
> + };
> + };
> + };
> +
> + etm@7340000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + reg = <0 0x07340000 0 0x1000>;
> +
> + cpu = <&CPU3>;
> +
> + clocks = <&aoss_qmp>;
> + clock-names = "apb_pclk";
> + arm,coresight-loses-context-with-cpu;
> +
> + out-ports {
> + port {
> + etm3_out: endpoint {
> + remote-endpoint =
> + <&apss_funnel_in3>;
> + };
> + };
> + };
> + };
> +
> + etm@7440000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + reg = <0 0x07440000 0 0x1000>;
> +
> + cpu = <&CPU4>;
> +
> + clocks = <&aoss_qmp>;
> + clock-names = "apb_pclk";
> + arm,coresight-loses-context-with-cpu;
> +
> + out-ports {
> + port {
> + etm4_out: endpoint {
> + remote-endpoint =
> + <&apss_funnel_in4>;
> + };
> + };
> + };
> + };
> +
> + etm@7540000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + reg = <0 0x07540000 0 0x1000>;
> +
> + cpu = <&CPU5>;
> +
> + clocks = <&aoss_qmp>;
> + clock-names = "apb_pclk";
> + arm,coresight-loses-context-with-cpu;
> +
> + out-ports {
> + port {
> + etm5_out: endpoint {
> + remote-endpoint =
> + <&apss_funnel_in5>;
> + };
> + };
> + };
> + };
> +
> + etm@7640000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + reg = <0 0x07640000 0 0x1000>;
> +
> + cpu = <&CPU6>;
> +
> + clocks = <&aoss_qmp>;
> + clock-names = "apb_pclk";
> + arm,coresight-loses-context-with-cpu;
> +
> + out-ports {
> + port {
> + etm6_out: endpoint {
> + remote-endpoint =
> + <&apss_funnel_in6>;
> + };
> + };
> + };
> + };
> +
> + etm@7740000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + reg = <0 0x07740000 0 0x1000>;
> +
> + cpu = <&CPU7>;
> +
> + clocks = <&aoss_qmp>;
> + clock-names = "apb_pclk";
> + arm,coresight-loses-context-with-cpu;
> +
> + out-ports {
> + port {
> + etm7_out: endpoint {
> + remote-endpoint =
> + <&apss_funnel_in7>;
> + };
> + };
> + };
> + };
> +
> + funnel@7800000 {
> + compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
> + reg = <0 0x07800000 0 0x1000>;
> +
> + clocks = <&aoss_qmp>;
> + clock-names = "apb_pclk";
> +
> + out-ports {
> + port {
> + apss_funnel_out: endpoint {
> + remote-endpoint =
> + <&apss_merge_funnel_in>;
> + };
> + };
> + };
> +
> + in-ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + apss_funnel_in0: endpoint {
> + remote-endpoint =
> + <&etm0_out>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + apss_funnel_in1: endpoint {
> + remote-endpoint =
> + <&etm1_out>;
> + };
> + };
> +
> + port@2 {
> + reg = <2>;
> + apss_funnel_in2: endpoint {
> + remote-endpoint =
> + <&etm2_out>;
> + };
> + };
> +
> + port@3 {
> + reg = <3>;
> + apss_funnel_in3: endpoint {
> + remote-endpoint =
> + <&etm3_out>;
> + };
> + };
> +
> + port@4 {
> + reg = <4>;
> + apss_funnel_in4: endpoint {
> + remote-endpoint =
> + <&etm4_out>;
> + };
> + };
> +
> + port@5 {
> + reg = <5>;
> + apss_funnel_in5: endpoint {
> + remote-endpoint =
> + <&etm5_out>;
> + };
> + };
> +
> + port@6 {
> + reg = <6>;
> + apss_funnel_in6: endpoint {
> + remote-endpoint =
> + <&etm6_out>;
> + };
> + };
> +
> + port@7 {
> + reg = <7>;
> + apss_funnel_in7: endpoint {
> + remote-endpoint =
> + <&etm7_out>;
> + };
> + };
> + };
> + };
> +
> + funnel@7810000 {
> + compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
> + reg = <0 0x07810000 0 0x1000>;
> +
> + clocks = <&aoss_qmp>;
> + clock-names = "apb_pclk";
> +
> + out-ports {
> + port {
> + apss_merge_funnel_out: endpoint {
> + remote-endpoint =
> + <&funnel2_in5>;
> + };
> + };
> + };
> +
> + in-ports {
> + port@1 {
> + reg = <0>;
> + apss_merge_funnel_in: endpoint {
> + remote-endpoint =
> + <&apss_funnel_out>;
> + };
> + };
> + };
> + };
> +
> + tpdm_mm: mm.tpdm@6c08000 {
> + compatible = "arm,primecell";
> + reg = <0 0x6c08000 0 0x1000>;
> + reg-names = "tpdm-base";
> +
> + clocks = <&aoss_qmp>;
> + clock-names = "apb_pclk";
> +
> + qcom,msr-fix-req;
> +
> + out-ports {
> + port {
> + tpdm_mm_out_funnel_dl_mm: endpoint {
> + remote-endpoint =
> + <&funnel_dl_mm_in_tpdm_mm>;
> + };
> + };
> + };
> + };
> +
> + funnel@6c0b000 {
> + compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
> +
> + reg = <0 0x6c0b000 0 0x1000>;
> + reg-names = "funnel-base";
> +
> + clocks = <&aoss_qmp>;
> + clock-names = "apb_pclk";
> +
> + out-ports {
> + port {
> + funnel_dl_mm_out_funnel_dl_center: endpoint {
> + remote-endpoint =
> + <&funnel_dl_center_in_funnel_dl_mm>;
> + };
> + };
> + };
> +
> + in-ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@3 {
> + reg = <3>;
> + funnel_dl_mm_in_tpdm_mm: endpoint {
> + remote-endpoint =
> + <&tpdm_mm_out_funnel_dl_mm>;
> + };
> + };
> + };
> + };
> +
> + funnel@6c2d000 {
> + compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
> +
> + reg = <0 0x6c2d000 0 0x1000>;
> + reg-names = "funnel-base";
> +
> + clocks = <&aoss_qmp>;
> + clock-names = "apb_pclk";
> +
> + out-ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + port {
> + tpdm_mm_out_tpda9: endpoint {
> + remote-endpoint =
> + <&tpda_9_in_tpdm_mm>;
> + };
> + };
> + };
> +
> + in-ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@2 {
> + reg = <2>;
> + funnel_dl_center_in_funnel_dl_mm: endpoint {
> + remote-endpoint =
> + <&funnel_dl_mm_out_funnel_dl_center>;
> + };
> + };
> + };
> + };
> +
> + tpda@6004000 {
> + compatible = "arm,primecell";
> + reg = <0 0x6004000 0 0x1000>;
> + reg-names = "tpda-base";
> +
> + qcom,tpda-atid = <65>;
> +
> + qcom,dsb-elem-size = <9 32>,
> + <10 32>,
> + <14 32>;
> +
> + clocks = <&aoss_qmp>;
> + clock-names = "apb_pclk";
> +
> + out-ports {
> + port {
> + reg = <0>;
> + tpda_out_funnel_qatb: endpoint {
> + remote-endpoint =
> + <&funnel_qatb_in_tpda>;
> + };
> + };
> + };
> +
> + in-ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@9 {
> + reg = <9>;
> + tpda_9_in_tpdm_mm: endpoint {
> + remote-endpoint =
> + <&tpdm_mm_out_tpda9>;
> + };
> + };
> + };
> + };
> +
> + funnel@6005000 {
> + compatible = "arm,primecell";
> +
> + reg = <0 0x6005000 0 0x1000>;
> + reg-names = "funnel-base";
> +
> + clocks = <&aoss_qmp>;
> + clock-names = "apb_pclk";
> +
> + out-ports {
> + port {
> + funnel_qatb_out_funnel_in0: endpoint {
> + remote-endpoint =
> + <&funnel_in0_in_funnel_qatb>;
> + };
> + };
> + };
> +
> + in-ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + funnel_qatb_in_tpda: endpoint {
> + remote-endpoint =
> + <&tpda_out_funnel_qatb>;
> + };
> + };
> + };
> + };
> +};
> diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
> index 5617a46e5ccd..d1837e3df30a 100644
> --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
> @@ -5323,3 +5323,5 @@
> };
> };
> };
> +
> +#include "sm8250-coresight.dtsi"
> --
> 2.17.1
>
--
Mike Leach
Principal Engineer, ARM Ltd.
Manchester Design Centre. UK
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v3 00/10] Coresight: Add support for TPDM and TPDA
2022-02-09 10:56 [PATCH v3 00/10] Coresight: Add support for TPDM and TPDA Mao Jinlong
` (9 preceding siblings ...)
2022-02-09 10:57 ` [PATCH v3 10/10] ARM: dts: msm: Add coresight components for SM8250 Mao Jinlong
@ 2022-02-10 10:30 ` Mike Leach
2022-02-11 4:17 ` Jinlong Mao
10 siblings, 1 reply; 22+ messages in thread
From: Mike Leach @ 2022-02-10 10:30 UTC (permalink / raw)
To: Mao Jinlong
Cc: Mathieu Poirier, Suzuki K Poulose, Alexander Shishkin, Leo Yan,
Greg Kroah-Hartman, coresight, linux-arm-kernel, linux-kernel,
Tingwei Zhang, Yuanfang Zhang, Tao Zhang, Trilok Soni, Hao Zhang,
linux-arm-msm
Hello Mao,
I have looked through this set and have a few general questions.
My understanding based on the information in the code is that the TPDM
devices will always send data to the TPDA device, the TPDM is not
capable of directly driving the ATB itself?
The TPDA device will then packetize the inputs and output these to
the ATB over the normal CoreSight architecture to a standard ETR / ETF
for collection.
Looking at the TPDM driver - it is assigned a trace ID but never
actually uses it in the hardware. My assumption here is that this is
used purely to satisfy the requirement that the CoreSight core has
that all sources have a unique trace id?
For the TPDA driver you assign an ATID as an attribute in device tree,
and then program this into the devices control register.
The trace IDs in ETM / ETE / STM, are programmed into the hardware and
these values drive the ATID value on the trace bus. So assigning an
ATID value to the TPDA driver through device tree will lead to clashes
with the assignment of trace IDs in the other driver software.
The topology here appears to me that you have multiple "data source"
devices TPDM, supplying a TPDA - which is the real CoreSight "trace
source" from the viewpoint of the trace bus and CoreSight
infrastructure.
To get this to work in the current CoreSight driver stack, you have
assigned the TPDM as a source type, and the TPDA as a link to ensure
that when a TPDM is started, all the components on the path to the
sink are activated.
This is fine.
If my assumptions above are all accurate I suggest the following improvements
For TPDA drop the device tree assignment of ATID and instead use the
coresight_get_system_trace_id() function you introduce in the 2nd
patch in this set.
For TPDM you have assigned a unique source sub-type
CORESIGHT_DEV_SUBTYPE_SOURCE_SYS.- this could become
CORESIGHT_DEV_SUBTYPE_SOURCE_DATA_ONLY. If the trace ID assigned to
this device is only to satisfy the unique ID requirement and is not
used elsewhere, then the sub type could become
CORESIGHT_DEV_SUBTYPE_SOURCE_DATA_ONLY. We can agree that this sub
type does not need a unique ID and acts as none ATB a source for
another component, The core code can be altered to drop the
requirement for this sub-type and trace ID can be dropped for this
component.
You should be aware that we are in the process of re-designed how
trace IDs are allocated. The current mechanism does not scale for
large multi-core systems (currently broken for any system > 46 cores),
and as you have discovered there is a need for additional allocation
of IDs. Also the ETE / TRBE combination does not need a trace ID. A
dynamic allocation system is being proposed.
Regards
Mike
On Wed, 9 Feb 2022 at 10:57, Mao Jinlong <quic_jinlmao@quicinc.com> wrote:
>
> This series adds support for the trace performance monitoring and
> diagnostics hardware (TPDM and TPDA). It is composed of two major
> elements.
> a) Changes for original coresight framework to support for TPDM and TPDA.
> b) Add driver code for TPDM and TPDA.
>
> Introduction of changes for original coresight framework
> Support TPDM as new coresight source.
> Since only STM and ETM are supported as coresight source originally.
> TPDM is a newly added coresight source. We need to change
> the original way of saving coresight path to support more types source
> for coresight driver.
> The following patch is to add support more coresight sources.
> Use IDR to maintain all the enabled sources' paths.
> coresight: Use bitmap to assign trace id to the sources
>
> Introduction of TPDM and TPDA
> TPDM - The trace performance monitoring and diagnostics monitor or TPDM in
> short serves as data collection component for various dataset types
> specified in the QPMDA(Qualcomm performance monitoring and diagnostics
> architecture) spec. The primary use case of the TPDM is to collect data
> from different data sources and send it to a TPDA for packetization,
> timestamping and funneling.
> Coresight: Add coresight TPDM source driver
> dt-bindings: arm: Adds CoreSight TPDM hardware definitions
> coresight-tpdm: Add DSB dataset support
> coresight-tpdm: Add integration test support
> docs: sysfs: coresight: Add sysfs ABI documentation for TPDM
>
> TPDA - The trace performance monitoring and diagnostics aggregator or
> TPDA in short serves as an arbitration and packetization engine for the
> performance monitoring and diagnostics network as specified in the QPMDA
> (Qualcomm performance monitoring and diagnostics architecture)
> specification. The primary use case of the TPDA is to provide
> packetization, funneling and timestamping of Monitor data as specified
> in the QPMDA specification.
> The following patch is to add driver for TPDA.
> Coresight: Add TPDA link driver
> dt-bindings: arm: Adds CoreSight TPDA hardware definitions
>
> The last patch of this series is a device tree modification, which add
> the TPDM and TPDA configuration to device tree for validating.
> ARM: dts: msm: Add coresight components for SM8250
>
> Once this series patches are applied properly, the tpdm and tpda nodes
> should be observed at the coresight path /sys/bus/coresight/devices
> e.g.
> /sys/bus/coresight/devices # ls -l | grep tpd
> tpda0 -> ../../../devices/platform/soc@0/6004000.tpda/tpda0
> tpdm0 -> ../../../devices/platform/soc@0/6c08000.mm.tpdm/tpdm0
>
> We can use the commands are similar to the below to validate TPDMs.
> Enable coresight sink first.
>
> echo 1 > /sys/bus/coresight/devices/tmc_etf0/enable_sink
> echo 1 > /sys/bus/coresight/devices/tpdm0/enable_source
> echo 1 > /sys/bus/coresight/devices/tpdm0/integration_test
> echo 2 > /sys/bus/coresight/devices/tpdm0/integration_test
> The test data will be collected in the coresight sink which is enabled.
> If rwp register of the sink is keeping updating when do
> integration_test (by cat tmc_etf0/mgmt/rwp), it means there is data
> generated from TPDM to sink.
>
> Changes from V2:
> 1. Use bitmap to assign the trace id. (Mathieu Poirier)
>
> Mao Jinlong (10):
> Use IDR to maintain all the enabled sources' paths.
> coresight: Use bitmap to assign trace id to the sources
> Coresight: Add coresight TPDM source driver
> dt-bindings: arm: Adds CoreSight TPDM hardware definitions
> coresight-tpdm: Add DSB dataset support
> coresight-tpdm: Add integration test support
> docs: sysfs: coresight: Add sysfs ABI documentation for TPDM
> Coresight: Add TPDA link driver
> dt-bindings: arm: Adds CoreSight TPDA hardware definitions
> ARM: dts: msm: Add coresight components for SM8250
>
> .../testing/sysfs-bus-coresight-devices-tpdm | 6 +
> .../bindings/arm/coresight-tpda.yaml | 129 ++++
> .../bindings/arm/coresight-tpdm.yaml | 81 ++
> .../devicetree/bindings/arm/coresight.txt | 7 +
> MAINTAINERS | 1 +
> .../arm64/boot/dts/qcom/sm8250-coresight.dtsi | 690 ++++++++++++++++++
> arch/arm64/boot/dts/qcom/sm8250.dtsi | 2 +
> drivers/hwtracing/coresight/Kconfig | 33 +
> drivers/hwtracing/coresight/Makefile | 2 +
> drivers/hwtracing/coresight/coresight-core.c | 127 ++--
> drivers/hwtracing/coresight/coresight-tpda.c | 193 +++++
> drivers/hwtracing/coresight/coresight-tpda.h | 32 +
> drivers/hwtracing/coresight/coresight-tpdm.c | 270 +++++++
> drivers/hwtracing/coresight/coresight-tpdm.h | 57 ++
> include/linux/coresight-pmu.h | 11 +
> include/linux/coresight.h | 1 +
> 16 files changed, 1592 insertions(+), 50 deletions(-)
> create mode 100644 Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm
> create mode 100644 Documentation/devicetree/bindings/arm/coresight-tpda.yaml
> create mode 100644 Documentation/devicetree/bindings/arm/coresight-tpdm.yaml
> create mode 100644 arch/arm64/boot/dts/qcom/sm8250-coresight.dtsi
> create mode 100644 drivers/hwtracing/coresight/coresight-tpda.c
> create mode 100644 drivers/hwtracing/coresight/coresight-tpda.h
> create mode 100644 drivers/hwtracing/coresight/coresight-tpdm.c
> create mode 100644 drivers/hwtracing/coresight/coresight-tpdm.h
>
> --
> 2.17.1
>
--
Mike Leach
Principal Engineer, ARM Ltd.
Manchester Design Centre. UK
^ permalink raw reply [flat|nested] 22+ messages in thread* Re: [PATCH v3 00/10] Coresight: Add support for TPDM and TPDA
2022-02-10 10:30 ` [PATCH v3 00/10] Coresight: Add support for TPDM and TPDA Mike Leach
@ 2022-02-11 4:17 ` Jinlong Mao
2022-02-17 9:16 ` Jinlong Mao
2022-02-17 15:30 ` Mike Leach
0 siblings, 2 replies; 22+ messages in thread
From: Jinlong Mao @ 2022-02-11 4:17 UTC (permalink / raw)
To: Mike Leach
Cc: Mathieu Poirier, Suzuki K Poulose, Alexander Shishkin, Leo Yan,
Greg Kroah-Hartman, coresight, linux-arm-kernel, linux-kernel,
Tingwei Zhang, Yuanfang Zhang, Tao Zhang, Trilok Soni, Hao Zhang,
linux-arm-msm
On 2/10/2022 6:30 PM, Mike Leach wrote:
> Hello Mao,
>
> I have looked through this set and have a few general questions.
>
> My understanding based on the information in the code is that the TPDM
> devices will always send data to the TPDA device, the TPDM is not
> capable of directly driving the ATB itself?
> The TPDA device will then packetize the inputs and output these to
> the ATB over the normal CoreSight architecture to a standard ETR / ETF
> for collection.
>
> Looking at the TPDM driver - it is assigned a trace ID but never
> actually uses it in the hardware. My assumption here is that this is
> used purely to satisfy the requirement that the CoreSight core has
> that all sources have a unique trace id?
>
> For the TPDA driver you assign an ATID as an attribute in device tree,
> and then program this into the devices control register.
>
> The trace IDs in ETM / ETE / STM, are programmed into the hardware and
> these values drive the ATID value on the trace bus. So assigning an
> ATID value to the TPDA driver through device tree will lead to clashes
> with the assignment of trace IDs in the other driver software.
>
> The topology here appears to me that you have multiple "data source"
> devices TPDM, supplying a TPDA - which is the real CoreSight "trace
> source" from the viewpoint of the trace bus and CoreSight
> infrastructure.
> To get this to work in the current CoreSight driver stack, you have
> assigned the TPDM as a source type, and the TPDA as a link to ensure
> that when a TPDM is started, all the components on the path to the
> sink are activated.
> This is fine.
>
> If my assumptions above are all accurate I suggest the following improvements
>
> For TPDA drop the device tree assignment of ATID and instead use the
> coresight_get_system_trace_id() function you introduce in the 2nd
> patch in this set.
>
> For TPDM you have assigned a unique source sub-type
> CORESIGHT_DEV_SUBTYPE_SOURCE_SYS.- this could become
> CORESIGHT_DEV_SUBTYPE_SOURCE_DATA_ONLY. If the trace ID assigned to
> this device is only to satisfy the unique ID requirement and is not
> used elsewhere, then the sub type could become
> CORESIGHT_DEV_SUBTYPE_SOURCE_DATA_ONLY. We can agree that this sub
> type does not need a unique ID and acts as none ATB a source for
> another component, The core code can be altered to drop the
> requirement for this sub-type and trace ID can be dropped for this
> component.
>
> You should be aware that we are in the process of re-designed how
> trace IDs are allocated. The current mechanism does not scale for
> large multi-core systems (currently broken for any system > 46 cores),
> and as you have discovered there is a need for additional allocation
> of IDs. Also the ETE / TRBE combination does not need a trace ID. A
> dynamic allocation system is being proposed.
>
> Regards
>
> Mike
Hi Mike,
Your assumptions above are all correct.
TPDMs connect to the same TPDA will share the atid of the TPDA.
We have a PC tool to parse the TPDM trace data. It needs the fixed atid
for each TPDA to identify the data.
So we configure the atid for TPDA in device tree with fixed ids.
I will discuss with internal tool team to see if TPDA's id can become
dynamic when parse the data.
Apart from the TPDA's atid, we also have some other sources with fixed
id in HW on our internal device.
Do you have any suggestion to how to allocate the IDs for the source
with fixed id in HW ?
Thanks
Jinlong Mao
>
>
> On Wed, 9 Feb 2022 at 10:57, Mao Jinlong <quic_jinlmao@quicinc.com> wrote:
>> This series adds support for the trace performance monitoring and
>> diagnostics hardware (TPDM and TPDA). It is composed of two major
>> elements.
>> a) Changes for original coresight framework to support for TPDM and TPDA.
>> b) Add driver code for TPDM and TPDA.
>>
>> Introduction of changes for original coresight framework
>> Support TPDM as new coresight source.
>> Since only STM and ETM are supported as coresight source originally.
>> TPDM is a newly added coresight source. We need to change
>> the original way of saving coresight path to support more types source
>> for coresight driver.
>> The following patch is to add support more coresight sources.
>> Use IDR to maintain all the enabled sources' paths.
>> coresight: Use bitmap to assign trace id to the sources
>>
>> Introduction of TPDM and TPDA
>> TPDM - The trace performance monitoring and diagnostics monitor or TPDM in
>> short serves as data collection component for various dataset types
>> specified in the QPMDA(Qualcomm performance monitoring and diagnostics
>> architecture) spec. The primary use case of the TPDM is to collect data
>> from different data sources and send it to a TPDA for packetization,
>> timestamping and funneling.
>> Coresight: Add coresight TPDM source driver
>> dt-bindings: arm: Adds CoreSight TPDM hardware definitions
>> coresight-tpdm: Add DSB dataset support
>> coresight-tpdm: Add integration test support
>> docs: sysfs: coresight: Add sysfs ABI documentation for TPDM
>>
>> TPDA - The trace performance monitoring and diagnostics aggregator or
>> TPDA in short serves as an arbitration and packetization engine for the
>> performance monitoring and diagnostics network as specified in the QPMDA
>> (Qualcomm performance monitoring and diagnostics architecture)
>> specification. The primary use case of the TPDA is to provide
>> packetization, funneling and timestamping of Monitor data as specified
>> in the QPMDA specification.
>> The following patch is to add driver for TPDA.
>> Coresight: Add TPDA link driver
>> dt-bindings: arm: Adds CoreSight TPDA hardware definitions
>>
>> The last patch of this series is a device tree modification, which add
>> the TPDM and TPDA configuration to device tree for validating.
>> ARM: dts: msm: Add coresight components for SM8250
>>
>> Once this series patches are applied properly, the tpdm and tpda nodes
>> should be observed at the coresight path /sys/bus/coresight/devices
>> e.g.
>> /sys/bus/coresight/devices # ls -l | grep tpd
>> tpda0 -> ../../../devices/platform/soc@0/6004000.tpda/tpda0
>> tpdm0 -> ../../../devices/platform/soc@0/6c08000.mm.tpdm/tpdm0
>>
>> We can use the commands are similar to the below to validate TPDMs.
>> Enable coresight sink first.
>>
>> echo 1 > /sys/bus/coresight/devices/tmc_etf0/enable_sink
>> echo 1 > /sys/bus/coresight/devices/tpdm0/enable_source
>> echo 1 > /sys/bus/coresight/devices/tpdm0/integration_test
>> echo 2 > /sys/bus/coresight/devices/tpdm0/integration_test
>> The test data will be collected in the coresight sink which is enabled.
>> If rwp register of the sink is keeping updating when do
>> integration_test (by cat tmc_etf0/mgmt/rwp), it means there is data
>> generated from TPDM to sink.
>>
>> Changes from V2:
>> 1. Use bitmap to assign the trace id. (Mathieu Poirier)
>>
>> Mao Jinlong (10):
>> Use IDR to maintain all the enabled sources' paths.
>> coresight: Use bitmap to assign trace id to the sources
>> Coresight: Add coresight TPDM source driver
>> dt-bindings: arm: Adds CoreSight TPDM hardware definitions
>> coresight-tpdm: Add DSB dataset support
>> coresight-tpdm: Add integration test support
>> docs: sysfs: coresight: Add sysfs ABI documentation for TPDM
>> Coresight: Add TPDA link driver
>> dt-bindings: arm: Adds CoreSight TPDA hardware definitions
>> ARM: dts: msm: Add coresight components for SM8250
>>
>> .../testing/sysfs-bus-coresight-devices-tpdm | 6 +
>> .../bindings/arm/coresight-tpda.yaml | 129 ++++
>> .../bindings/arm/coresight-tpdm.yaml | 81 ++
>> .../devicetree/bindings/arm/coresight.txt | 7 +
>> MAINTAINERS | 1 +
>> .../arm64/boot/dts/qcom/sm8250-coresight.dtsi | 690 ++++++++++++++++++
>> arch/arm64/boot/dts/qcom/sm8250.dtsi | 2 +
>> drivers/hwtracing/coresight/Kconfig | 33 +
>> drivers/hwtracing/coresight/Makefile | 2 +
>> drivers/hwtracing/coresight/coresight-core.c | 127 ++--
>> drivers/hwtracing/coresight/coresight-tpda.c | 193 +++++
>> drivers/hwtracing/coresight/coresight-tpda.h | 32 +
>> drivers/hwtracing/coresight/coresight-tpdm.c | 270 +++++++
>> drivers/hwtracing/coresight/coresight-tpdm.h | 57 ++
>> include/linux/coresight-pmu.h | 11 +
>> include/linux/coresight.h | 1 +
>> 16 files changed, 1592 insertions(+), 50 deletions(-)
>> create mode 100644 Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm
>> create mode 100644 Documentation/devicetree/bindings/arm/coresight-tpda.yaml
>> create mode 100644 Documentation/devicetree/bindings/arm/coresight-tpdm.yaml
>> create mode 100644 arch/arm64/boot/dts/qcom/sm8250-coresight.dtsi
>> create mode 100644 drivers/hwtracing/coresight/coresight-tpda.c
>> create mode 100644 drivers/hwtracing/coresight/coresight-tpda.h
>> create mode 100644 drivers/hwtracing/coresight/coresight-tpdm.c
>> create mode 100644 drivers/hwtracing/coresight/coresight-tpdm.h
>>
>> --
>> 2.17.1
>>
>
> --
> Mike Leach
> Principal Engineer, ARM Ltd.
> Manchester Design Centre. UK
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v3 00/10] Coresight: Add support for TPDM and TPDA
2022-02-11 4:17 ` Jinlong Mao
@ 2022-02-17 9:16 ` Jinlong Mao
2022-02-17 15:30 ` Mike Leach
1 sibling, 0 replies; 22+ messages in thread
From: Jinlong Mao @ 2022-02-17 9:16 UTC (permalink / raw)
To: Mike Leach
Cc: Mathieu Poirier, Suzuki K Poulose, Alexander Shishkin, Leo Yan,
Greg Kroah-Hartman, coresight, linux-arm-kernel, linux-kernel,
Tingwei Zhang, Yuanfang Zhang, Tao Zhang, Trilok Soni, Hao Zhang,
linux-arm-msm
On 2/11/2022 12:17 PM, Jinlong Mao wrote:
>
> On 2/10/2022 6:30 PM, Mike Leach wrote:
>> Hello Mao,
>>
>> I have looked through this set and have a few general questions.
>>
>> My understanding based on the information in the code is that the TPDM
>> devices will always send data to the TPDA device, the TPDM is not
>> capable of directly driving the ATB itself?
>> The TPDA device will then packetize the inputs and output these to
>> the ATB over the normal CoreSight architecture to a standard ETR / ETF
>> for collection.
>>
>> Looking at the TPDM driver - it is assigned a trace ID but never
>> actually uses it in the hardware. My assumption here is that this is
>> used purely to satisfy the requirement that the CoreSight core has
>> that all sources have a unique trace id?
>>
>> For the TPDA driver you assign an ATID as an attribute in device tree,
>> and then program this into the devices control register.
>>
>> The trace IDs in ETM / ETE / STM, are programmed into the hardware and
>> these values drive the ATID value on the trace bus. So assigning an
>> ATID value to the TPDA driver through device tree will lead to clashes
>> with the assignment of trace IDs in the other driver software.
>>
>> The topology here appears to me that you have multiple "data source"
>> devices TPDM, supplying a TPDA - which is the real CoreSight "trace
>> source" from the viewpoint of the trace bus and CoreSight
>> infrastructure.
>> To get this to work in the current CoreSight driver stack, you have
>> assigned the TPDM as a source type, and the TPDA as a link to ensure
>> that when a TPDM is started, all the components on the path to the
>> sink are activated.
>> This is fine.
>>
>> If my assumptions above are all accurate I suggest the following
>> improvements
>>
>> For TPDA drop the device tree assignment of ATID and instead use the
>> coresight_get_system_trace_id() function you introduce in the 2nd
>> patch in this set.
>>
>> For TPDM you have assigned a unique source sub-type
>> CORESIGHT_DEV_SUBTYPE_SOURCE_SYS.- this could become
>> CORESIGHT_DEV_SUBTYPE_SOURCE_DATA_ONLY. If the trace ID assigned to
>> this device is only to satisfy the unique ID requirement and is not
>> used elsewhere, then the sub type could become
>> CORESIGHT_DEV_SUBTYPE_SOURCE_DATA_ONLY. We can agree that this sub
>> type does not need a unique ID and acts as none ATB a source for
>> another component, The core code can be altered to drop the
>> requirement for this sub-type and trace ID can be dropped for this
>> component.
>>
>> You should be aware that we are in the process of re-designed how
>> trace IDs are allocated. The current mechanism does not scale for
>> large multi-core systems (currently broken for any system > 46 cores),
>> and as you have discovered there is a need for additional allocation
>> of IDs. Also the ETE / TRBE combination does not need a trace ID. A
>> dynamic allocation system is being proposed.
>>
>> Regards
>>
>> Mike
>
>
> Hi Mike,
>
> Your assumptions above are all correct.
> TPDMs connect to the same TPDA will share the atid of the TPDA.
> We have a PC tool to parse the TPDM trace data. It needs the fixed
> atid for each TPDA to identify the data.
> So we configure the atid for TPDA in device tree with fixed ids.
> I will discuss with internal tool team to see if TPDA's id can become
> dynamic when parse the data.
>
> Apart from the TPDA's atid, we also have some other sources with fixed
> id in HW on our internal device.
> Do you have any suggestion to how to allocate the IDs for the source
> with fixed id in HW ?
>
> Thanks
> Jinlong Mao
>
Hi Mike & Mathieu & Suzuki,
Could you please help to review the other patches while we are
discussing with internal tool team about the trace_id change ?
Thanks
Jinlong Mao
>
>>
>>
>> On Wed, 9 Feb 2022 at 10:57, Mao Jinlong <quic_jinlmao@quicinc.com>
>> wrote:
>>> This series adds support for the trace performance monitoring and
>>> diagnostics hardware (TPDM and TPDA). It is composed of two major
>>> elements.
>>> a) Changes for original coresight framework to support for TPDM and
>>> TPDA.
>>> b) Add driver code for TPDM and TPDA.
>>>
>>> Introduction of changes for original coresight framework
>>> Support TPDM as new coresight source.
>>> Since only STM and ETM are supported as coresight source originally.
>>> TPDM is a newly added coresight source. We need to change
>>> the original way of saving coresight path to support more types source
>>> for coresight driver.
>>> The following patch is to add support more coresight sources.
>>> Use IDR to maintain all the enabled sources' paths.
>>> coresight: Use bitmap to assign trace id to the sources
>>>
>>> Introduction of TPDM and TPDA
>>> TPDM - The trace performance monitoring and diagnostics monitor or
>>> TPDM in
>>> short serves as data collection component for various dataset types
>>> specified in the QPMDA(Qualcomm performance monitoring and diagnostics
>>> architecture) spec. The primary use case of the TPDM is to collect data
>>> from different data sources and send it to a TPDA for packetization,
>>> timestamping and funneling.
>>> Coresight: Add coresight TPDM source driver
>>> dt-bindings: arm: Adds CoreSight TPDM hardware definitions
>>> coresight-tpdm: Add DSB dataset support
>>> coresight-tpdm: Add integration test support
>>> docs: sysfs: coresight: Add sysfs ABI documentation for TPDM
>>>
>>> TPDA - The trace performance monitoring and diagnostics aggregator or
>>> TPDA in short serves as an arbitration and packetization engine for the
>>> performance monitoring and diagnostics network as specified in the
>>> QPMDA
>>> (Qualcomm performance monitoring and diagnostics architecture)
>>> specification. The primary use case of the TPDA is to provide
>>> packetization, funneling and timestamping of Monitor data as specified
>>> in the QPMDA specification.
>>> The following patch is to add driver for TPDA.
>>> Coresight: Add TPDA link driver
>>> dt-bindings: arm: Adds CoreSight TPDA hardware definitions
>>>
>>> The last patch of this series is a device tree modification, which add
>>> the TPDM and TPDA configuration to device tree for validating.
>>> ARM: dts: msm: Add coresight components for SM8250
>>>
>>> Once this series patches are applied properly, the tpdm and tpda nodes
>>> should be observed at the coresight path /sys/bus/coresight/devices
>>> e.g.
>>> /sys/bus/coresight/devices # ls -l | grep tpd
>>> tpda0 -> ../../../devices/platform/soc@0/6004000.tpda/tpda0
>>> tpdm0 -> ../../../devices/platform/soc@0/6c08000.mm.tpdm/tpdm0
>>>
>>> We can use the commands are similar to the below to validate TPDMs.
>>> Enable coresight sink first.
>>>
>>> echo 1 > /sys/bus/coresight/devices/tmc_etf0/enable_sink
>>> echo 1 > /sys/bus/coresight/devices/tpdm0/enable_source
>>> echo 1 > /sys/bus/coresight/devices/tpdm0/integration_test
>>> echo 2 > /sys/bus/coresight/devices/tpdm0/integration_test
>>> The test data will be collected in the coresight sink which is enabled.
>>> If rwp register of the sink is keeping updating when do
>>> integration_test (by cat tmc_etf0/mgmt/rwp), it means there is data
>>> generated from TPDM to sink.
>>>
>>> Changes from V2:
>>> 1. Use bitmap to assign the trace id. (Mathieu Poirier)
>>>
>>> Mao Jinlong (10):
>>> Use IDR to maintain all the enabled sources' paths.
>>> coresight: Use bitmap to assign trace id to the sources
>>> Coresight: Add coresight TPDM source driver
>>> dt-bindings: arm: Adds CoreSight TPDM hardware definitions
>>> coresight-tpdm: Add DSB dataset support
>>> coresight-tpdm: Add integration test support
>>> docs: sysfs: coresight: Add sysfs ABI documentation for TPDM
>>> Coresight: Add TPDA link driver
>>> dt-bindings: arm: Adds CoreSight TPDA hardware definitions
>>> ARM: dts: msm: Add coresight components for SM8250
>>>
>>> .../testing/sysfs-bus-coresight-devices-tpdm | 6 +
>>> .../bindings/arm/coresight-tpda.yaml | 129 ++++
>>> .../bindings/arm/coresight-tpdm.yaml | 81 ++
>>> .../devicetree/bindings/arm/coresight.txt | 7 +
>>> MAINTAINERS | 1 +
>>> .../arm64/boot/dts/qcom/sm8250-coresight.dtsi | 690
>>> ++++++++++++++++++
>>> arch/arm64/boot/dts/qcom/sm8250.dtsi | 2 +
>>> drivers/hwtracing/coresight/Kconfig | 33 +
>>> drivers/hwtracing/coresight/Makefile | 2 +
>>> drivers/hwtracing/coresight/coresight-core.c | 127 ++--
>>> drivers/hwtracing/coresight/coresight-tpda.c | 193 +++++
>>> drivers/hwtracing/coresight/coresight-tpda.h | 32 +
>>> drivers/hwtracing/coresight/coresight-tpdm.c | 270 +++++++
>>> drivers/hwtracing/coresight/coresight-tpdm.h | 57 ++
>>> include/linux/coresight-pmu.h | 11 +
>>> include/linux/coresight.h | 1 +
>>> 16 files changed, 1592 insertions(+), 50 deletions(-)
>>> create mode 100644
>>> Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm
>>> create mode 100644
>>> Documentation/devicetree/bindings/arm/coresight-tpda.yaml
>>> create mode 100644
>>> Documentation/devicetree/bindings/arm/coresight-tpdm.yaml
>>> create mode 100644 arch/arm64/boot/dts/qcom/sm8250-coresight.dtsi
>>> create mode 100644 drivers/hwtracing/coresight/coresight-tpda.c
>>> create mode 100644 drivers/hwtracing/coresight/coresight-tpda.h
>>> create mode 100644 drivers/hwtracing/coresight/coresight-tpdm.c
>>> create mode 100644 drivers/hwtracing/coresight/coresight-tpdm.h
>>>
>>> --
>>> 2.17.1
>>>
>>
>> --
>> Mike Leach
>> Principal Engineer, ARM Ltd.
>> Manchester Design Centre. UK
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v3 00/10] Coresight: Add support for TPDM and TPDA
2022-02-11 4:17 ` Jinlong Mao
2022-02-17 9:16 ` Jinlong Mao
@ 2022-02-17 15:30 ` Mike Leach
2022-02-28 2:49 ` Jinlong Mao
1 sibling, 1 reply; 22+ messages in thread
From: Mike Leach @ 2022-02-17 15:30 UTC (permalink / raw)
To: Jinlong Mao
Cc: Mathieu Poirier, Suzuki K Poulose, Alexander Shishkin, Leo Yan,
Greg Kroah-Hartman, coresight, linux-arm-kernel, linux-kernel,
Tingwei Zhang, Yuanfang Zhang, Tao Zhang, Trilok Soni, Hao Zhang,
linux-arm-msm
Hi,
On Fri, 11 Feb 2022 at 04:17, Jinlong Mao <quic_jinlmao@quicinc.com> wrote:
>
>
> On 2/10/2022 6:30 PM, Mike Leach wrote:
> > Hello Mao,
> >
> > I have looked through this set and have a few general questions.
> >
> > My understanding based on the information in the code is that the TPDM
> > devices will always send data to the TPDA device, the TPDM is not
> > capable of directly driving the ATB itself?
> > The TPDA device will then packetize the inputs and output these to
> > the ATB over the normal CoreSight architecture to a standard ETR / ETF
> > for collection.
> >
> > Looking at the TPDM driver - it is assigned a trace ID but never
> > actually uses it in the hardware. My assumption here is that this is
> > used purely to satisfy the requirement that the CoreSight core has
> > that all sources have a unique trace id?
> >
> > For the TPDA driver you assign an ATID as an attribute in device tree,
> > and then program this into the devices control register.
> >
> > The trace IDs in ETM / ETE / STM, are programmed into the hardware and
> > these values drive the ATID value on the trace bus. So assigning an
> > ATID value to the TPDA driver through device tree will lead to clashes
> > with the assignment of trace IDs in the other driver software.
> >
> > The topology here appears to me that you have multiple "data source"
> > devices TPDM, supplying a TPDA - which is the real CoreSight "trace
> > source" from the viewpoint of the trace bus and CoreSight
> > infrastructure.
> > To get this to work in the current CoreSight driver stack, you have
> > assigned the TPDM as a source type, and the TPDA as a link to ensure
> > that when a TPDM is started, all the components on the path to the
> > sink are activated.
> > This is fine.
> >
> > If my assumptions above are all accurate I suggest the following improvements
> >
> > For TPDA drop the device tree assignment of ATID and instead use the
> > coresight_get_system_trace_id() function you introduce in the 2nd
> > patch in this set.
> >
> > For TPDM you have assigned a unique source sub-type
> > CORESIGHT_DEV_SUBTYPE_SOURCE_SYS.- this could become
> > CORESIGHT_DEV_SUBTYPE_SOURCE_DATA_ONLY. If the trace ID assigned to
> > this device is only to satisfy the unique ID requirement and is not
> > used elsewhere, then the sub type could become
> > CORESIGHT_DEV_SUBTYPE_SOURCE_DATA_ONLY. We can agree that this sub
> > type does not need a unique ID and acts as none ATB a source for
> > another component, The core code can be altered to drop the
> > requirement for this sub-type and trace ID can be dropped for this
> > component.
> >
> > You should be aware that we are in the process of re-designed how
> > trace IDs are allocated. The current mechanism does not scale for
> > large multi-core systems (currently broken for any system > 46 cores),
> > and as you have discovered there is a need for additional allocation
> > of IDs. Also the ETE / TRBE combination does not need a trace ID. A
> > dynamic allocation system is being proposed.
> >
> > Regards
> >
> > Mike
>
>
> Hi Mike,
>
> Your assumptions above are all correct.
> TPDMs connect to the same TPDA will share the atid of the TPDA.
> We have a PC tool to parse the TPDM trace data. It needs the fixed atid
> for each TPDA to identify the data.
> So we configure the atid for TPDA in device tree with fixed ids.
> I will discuss with internal tool team to see if TPDA's id can become
> dynamic when parse the data.
>
I understand that it is essential to know the ID when extracting the
trace from a sink with a coresight frame fomatter.
However, tools such as perf, achieve this by saving the metadata for
the session. If you are programming the trace ID, then it should be
possible to read back the same register to get the required
information for your trace session.
If this is genuinely not possible for your system, then treat as a
fixed ID as I describe below.
> Apart from the TPDA's atid, we also have some other sources with fixed
> id in HW on our internal device.
> Do you have any suggestion to how to allocate the IDs for the source
> with fixed id in HW ?
>
>
Fixed IDs in hardware - assuming that these devices do write directly
onto the trace bus using the ATID, should be accommodated by reserving
the fixed ID in any scheme used to allocate IDs,
In your case this would be to set a bit at the correct area in the bitfield.
As mentioned we are working on an updated system to dynamically
allocate IDs for CoreSight sources - a reservation scheme for fixed ID
devices will be provided
.
Regards
Mike
>< Thanks
> Jinlong Mao
>
>
> >
> >
> > On Wed, 9 Feb 2022 at 10:57, Mao Jinlong <quic_jinlmao@quicinc.com> wrote:
> >> This series adds support for the trace performance monitoring and
> >> diagnostics hardware (TPDM and TPDA). It is composed of two major
> >> elements.
> >> a) Changes for original coresight framework to support for TPDM and TPDA.
> >> b) Add driver code for TPDM and TPDA.
> >>
> >> Introduction of changes for original coresight framework
> >> Support TPDM as new coresight source.
> >> Since only STM and ETM are supported as coresight source originally.
> >> TPDM is a newly added coresight source. We need to change
> >> the original way of saving coresight path to support more types source
> >> for coresight driver.
> >> The following patch is to add support more coresight sources.
> >> Use IDR to maintain all the enabled sources' paths.
> >> coresight: Use bitmap to assign trace id to the sources
> >>
> >> Introduction of TPDM and TPDA
> >> TPDM - The trace performance monitoring and diagnostics monitor or TPDM in
> >> short serves as data collection component for various dataset types
> >> specified in the QPMDA(Qualcomm performance monitoring and diagnostics
> >> architecture) spec. The primary use case of the TPDM is to collect data
> >> from different data sources and send it to a TPDA for packetization,
> >> timestamping and funneling.
> >> Coresight: Add coresight TPDM source driver
> >> dt-bindings: arm: Adds CoreSight TPDM hardware definitions
> >> coresight-tpdm: Add DSB dataset support
> >> coresight-tpdm: Add integration test support
> >> docs: sysfs: coresight: Add sysfs ABI documentation for TPDM
> >>
> >> TPDA - The trace performance monitoring and diagnostics aggregator or
> >> TPDA in short serves as an arbitration and packetization engine for the
> >> performance monitoring and diagnostics network as specified in the QPMDA
> >> (Qualcomm performance monitoring and diagnostics architecture)
> >> specification. The primary use case of the TPDA is to provide
> >> packetization, funneling and timestamping of Monitor data as specified
> >> in the QPMDA specification.
> >> The following patch is to add driver for TPDA.
> >> Coresight: Add TPDA link driver
> >> dt-bindings: arm: Adds CoreSight TPDA hardware definitions
> >>
> >> The last patch of this series is a device tree modification, which add
> >> the TPDM and TPDA configuration to device tree for validating.
> >> ARM: dts: msm: Add coresight components for SM8250
> >>
> >> Once this series patches are applied properly, the tpdm and tpda nodes
> >> should be observed at the coresight path /sys/bus/coresight/devices
> >> e.g.
> >> /sys/bus/coresight/devices # ls -l | grep tpd
> >> tpda0 -> ../../../devices/platform/soc@0/6004000.tpda/tpda0
> >> tpdm0 -> ../../../devices/platform/soc@0/6c08000.mm.tpdm/tpdm0
> >>
> >> We can use the commands are similar to the below to validate TPDMs.
> >> Enable coresight sink first.
> >>
> >> echo 1 > /sys/bus/coresight/devices/tmc_etf0/enable_sink
> >> echo 1 > /sys/bus/coresight/devices/tpdm0/enable_source
> >> echo 1 > /sys/bus/coresight/devices/tpdm0/integration_test
> >> echo 2 > /sys/bus/coresight/devices/tpdm0/integration_test
> >> The test data will be collected in the coresight sink which is enabled.
> >> If rwp register of the sink is keeping updating when do
> >> integration_test (by cat tmc_etf0/mgmt/rwp), it means there is data
> >> generated from TPDM to sink.
> >>
> >> Changes from V2:
> >> 1. Use bitmap to assign the trace id. (Mathieu Poirier)
> >>
> >> Mao Jinlong (10):
> >> Use IDR to maintain all the enabled sources' paths.
> >> coresight: Use bitmap to assign trace id to the sources
> >> Coresight: Add coresight TPDM source driver
> >> dt-bindings: arm: Adds CoreSight TPDM hardware definitions
> >> coresight-tpdm: Add DSB dataset support
> >> coresight-tpdm: Add integration test support
> >> docs: sysfs: coresight: Add sysfs ABI documentation for TPDM
> >> Coresight: Add TPDA link driver
> >> dt-bindings: arm: Adds CoreSight TPDA hardware definitions
> >> ARM: dts: msm: Add coresight components for SM8250
> >>
> >> .../testing/sysfs-bus-coresight-devices-tpdm | 6 +
> >> .../bindings/arm/coresight-tpda.yaml | 129 ++++
> >> .../bindings/arm/coresight-tpdm.yaml | 81 ++
> >> .../devicetree/bindings/arm/coresight.txt | 7 +
> >> MAINTAINERS | 1 +
> >> .../arm64/boot/dts/qcom/sm8250-coresight.dtsi | 690 ++++++++++++++++++
> >> arch/arm64/boot/dts/qcom/sm8250.dtsi | 2 +
> >> drivers/hwtracing/coresight/Kconfig | 33 +
> >> drivers/hwtracing/coresight/Makefile | 2 +
> >> drivers/hwtracing/coresight/coresight-core.c | 127 ++--
> >> drivers/hwtracing/coresight/coresight-tpda.c | 193 +++++
> >> drivers/hwtracing/coresight/coresight-tpda.h | 32 +
> >> drivers/hwtracing/coresight/coresight-tpdm.c | 270 +++++++
> >> drivers/hwtracing/coresight/coresight-tpdm.h | 57 ++
> >> include/linux/coresight-pmu.h | 11 +
> >> include/linux/coresight.h | 1 +
> >> 16 files changed, 1592 insertions(+), 50 deletions(-)
> >> create mode 100644 Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm
> >> create mode 100644 Documentation/devicetree/bindings/arm/coresight-tpda.yaml
> >> create mode 100644 Documentation/devicetree/bindings/arm/coresight-tpdm.yaml
> >> create mode 100644 arch/arm64/boot/dts/qcom/sm8250-coresight.dtsi
> >> create mode 100644 drivers/hwtracing/coresight/coresight-tpda.c
> >> create mode 100644 drivers/hwtracing/coresight/coresight-tpda.h
> >> create mode 100644 drivers/hwtracing/coresight/coresight-tpdm.c
> >> create mode 100644 drivers/hwtracing/coresight/coresight-tpdm.h
> >>
> >> --
> >> 2.17.1
> >>
> >
> > --
> > Mike Leach
> > Principal Engineer, ARM Ltd.
> > Manchester Design Centre. UK
--
Mike Leach
Principal Engineer, ARM Ltd.
Manchester Design Centre. UK
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v3 00/10] Coresight: Add support for TPDM and TPDA
2022-02-17 15:30 ` Mike Leach
@ 2022-02-28 2:49 ` Jinlong Mao
0 siblings, 0 replies; 22+ messages in thread
From: Jinlong Mao @ 2022-02-28 2:49 UTC (permalink / raw)
To: Mike Leach
Cc: Mathieu Poirier, Suzuki K Poulose, Alexander Shishkin, Leo Yan,
Greg Kroah-Hartman, coresight, linux-arm-kernel, linux-kernel,
Tingwei Zhang, Yuanfang Zhang, Tao Zhang, Trilok Soni, Hao Zhang,
linux-arm-msm
Good morning.
On 2/17/2022 11:30 PM, Mike Leach wrote:
> Hi,
>
>
> On Fri, 11 Feb 2022 at 04:17, Jinlong Mao <quic_jinlmao@quicinc.com> wrote:
>>
>> On 2/10/2022 6:30 PM, Mike Leach wrote:
>>> Hello Mao,
>>>
>>> I have looked through this set and have a few general questions.
>>>
>>> My understanding based on the information in the code is that the TPDM
>>> devices will always send data to the TPDA device, the TPDM is not
>>> capable of directly driving the ATB itself?
>>> The TPDA device will then packetize the inputs and output these to
>>> the ATB over the normal CoreSight architecture to a standard ETR / ETF
>>> for collection.
>>>
>>> Looking at the TPDM driver - it is assigned a trace ID but never
>>> actually uses it in the hardware. My assumption here is that this is
>>> used purely to satisfy the requirement that the CoreSight core has
>>> that all sources have a unique trace id?
>>>
>>> For the TPDA driver you assign an ATID as an attribute in device tree,
>>> and then program this into the devices control register.
>>>
>>> The trace IDs in ETM / ETE / STM, are programmed into the hardware and
>>> these values drive the ATID value on the trace bus. So assigning an
>>> ATID value to the TPDA driver through device tree will lead to clashes
>>> with the assignment of trace IDs in the other driver software.
>>>
>>> The topology here appears to me that you have multiple "data source"
>>> devices TPDM, supplying a TPDA - which is the real CoreSight "trace
>>> source" from the viewpoint of the trace bus and CoreSight
>>> infrastructure.
>>> To get this to work in the current CoreSight driver stack, you have
>>> assigned the TPDM as a source type, and the TPDA as a link to ensure
>>> that when a TPDM is started, all the components on the path to the
>>> sink are activated.
>>> This is fine.
>>>
>>> If my assumptions above are all accurate I suggest the following improvements
>>>
>>> For TPDA drop the device tree assignment of ATID and instead use the
>>> coresight_get_system_trace_id() function you introduce in the 2nd
>>> patch in this set.
>>>
>>> For TPDM you have assigned a unique source sub-type
>>> CORESIGHT_DEV_SUBTYPE_SOURCE_SYS.- this could become
>>> CORESIGHT_DEV_SUBTYPE_SOURCE_DATA_ONLY. If the trace ID assigned to
>>> this device is only to satisfy the unique ID requirement and is not
>>> used elsewhere, then the sub type could become
>>> CORESIGHT_DEV_SUBTYPE_SOURCE_DATA_ONLY. We can agree that this sub
>>> type does not need a unique ID and acts as none ATB a source for
>>> another component, The core code can be altered to drop the
>>> requirement for this sub-type and trace ID can be dropped for this
>>> component.
>>>
>>> You should be aware that we are in the process of re-designed how
>>> trace IDs are allocated. The current mechanism does not scale for
>>> large multi-core systems (currently broken for any system > 46 cores),
>>> and as you have discovered there is a need for additional allocation
>>> of IDs. Also the ETE / TRBE combination does not need a trace ID. A
>>> dynamic allocation system is being proposed.
>>>
>>> Regards
>>>
>>> Mike
>>
>> Hi Mike,
>>
>> Your assumptions above are all correct.
>> TPDMs connect to the same TPDA will share the atid of the TPDA.
>> We have a PC tool to parse the TPDM trace data. It needs the fixed atid
>> for each TPDA to identify the data.
>> So we configure the atid for TPDA in device tree with fixed ids.
>> I will discuss with internal tool team to see if TPDA's id can become
>> dynamic when parse the data.
>>
> I understand that it is essential to know the ID when extracting the
> trace from a sink with a coresight frame fomatter.
> However, tools such as perf, achieve this by saving the metadata for
> the session. If you are programming the trace ID, then it should be
> possible to read back the same register to get the required
> information for your trace session.
>
> If this is genuinely not possible for your system, then treat as a
> fixed ID as I describe below.
>
>> Apart from the TPDA's atid, we also have some other sources with fixed
>> id in HW on our internal device.
>> Do you have any suggestion to how to allocate the IDs for the source
>> with fixed id in HW ?
>>
>>
> Fixed IDs in hardware - assuming that these devices do write directly
> onto the trace bus using the ATID, should be accommodated by reserving
> the fixed ID in any scheme used to allocate IDs,
> In your case this would be to set a bit at the correct area in the bitfield.
>
> As mentioned we are working on an updated system to dynamically
> allocate IDs for CoreSight sources - a reservation scheme for fixed ID
> devices will be provided
> .
>
> Regards
>
> Mike
Thanks Mike for the code review these days.
Discussed internally, we will use dynamical allocation for TPDA Atid.
I will submit a new version for all your comments to the patches as of now.
Thanks
Jinlong Mao
>
> >< Thanks
>> Jinlong Mao
>>
>>
>>>
>>> On Wed, 9 Feb 2022 at 10:57, Mao Jinlong <quic_jinlmao@quicinc.com> wrote:
>>>> This series adds support for the trace performance monitoring and
>>>> diagnostics hardware (TPDM and TPDA). It is composed of two major
>>>> elements.
>>>> a) Changes for original coresight framework to support for TPDM and TPDA.
>>>> b) Add driver code for TPDM and TPDA.
>>>>
>>>> Introduction of changes for original coresight framework
>>>> Support TPDM as new coresight source.
>>>> Since only STM and ETM are supported as coresight source originally.
>>>> TPDM is a newly added coresight source. We need to change
>>>> the original way of saving coresight path to support more types source
>>>> for coresight driver.
>>>> The following patch is to add support more coresight sources.
>>>> Use IDR to maintain all the enabled sources' paths.
>>>> coresight: Use bitmap to assign trace id to the sources
>>>>
>>>> Introduction of TPDM and TPDA
>>>> TPDM - The trace performance monitoring and diagnostics monitor or TPDM in
>>>> short serves as data collection component for various dataset types
>>>> specified in the QPMDA(Qualcomm performance monitoring and diagnostics
>>>> architecture) spec. The primary use case of the TPDM is to collect data
>>>> from different data sources and send it to a TPDA for packetization,
>>>> timestamping and funneling.
>>>> Coresight: Add coresight TPDM source driver
>>>> dt-bindings: arm: Adds CoreSight TPDM hardware definitions
>>>> coresight-tpdm: Add DSB dataset support
>>>> coresight-tpdm: Add integration test support
>>>> docs: sysfs: coresight: Add sysfs ABI documentation for TPDM
>>>>
>>>> TPDA - The trace performance monitoring and diagnostics aggregator or
>>>> TPDA in short serves as an arbitration and packetization engine for the
>>>> performance monitoring and diagnostics network as specified in the QPMDA
>>>> (Qualcomm performance monitoring and diagnostics architecture)
>>>> specification. The primary use case of the TPDA is to provide
>>>> packetization, funneling and timestamping of Monitor data as specified
>>>> in the QPMDA specification.
>>>> The following patch is to add driver for TPDA.
>>>> Coresight: Add TPDA link driver
>>>> dt-bindings: arm: Adds CoreSight TPDA hardware definitions
>>>>
>>>> The last patch of this series is a device tree modification, which add
>>>> the TPDM and TPDA configuration to device tree for validating.
>>>> ARM: dts: msm: Add coresight components for SM8250
>>>>
>>>> Once this series patches are applied properly, the tpdm and tpda nodes
>>>> should be observed at the coresight path /sys/bus/coresight/devices
>>>> e.g.
>>>> /sys/bus/coresight/devices # ls -l | grep tpd
>>>> tpda0 -> ../../../devices/platform/soc@0/6004000.tpda/tpda0
>>>> tpdm0 -> ../../../devices/platform/soc@0/6c08000.mm.tpdm/tpdm0
>>>>
>>>> We can use the commands are similar to the below to validate TPDMs.
>>>> Enable coresight sink first.
>>>>
>>>> echo 1 > /sys/bus/coresight/devices/tmc_etf0/enable_sink
>>>> echo 1 > /sys/bus/coresight/devices/tpdm0/enable_source
>>>> echo 1 > /sys/bus/coresight/devices/tpdm0/integration_test
>>>> echo 2 > /sys/bus/coresight/devices/tpdm0/integration_test
>>>> The test data will be collected in the coresight sink which is enabled.
>>>> If rwp register of the sink is keeping updating when do
>>>> integration_test (by cat tmc_etf0/mgmt/rwp), it means there is data
>>>> generated from TPDM to sink.
>>>>
>>>> Changes from V2:
>>>> 1. Use bitmap to assign the trace id. (Mathieu Poirier)
>>>>
>>>> Mao Jinlong (10):
>>>> Use IDR to maintain all the enabled sources' paths.
>>>> coresight: Use bitmap to assign trace id to the sources
>>>> Coresight: Add coresight TPDM source driver
>>>> dt-bindings: arm: Adds CoreSight TPDM hardware definitions
>>>> coresight-tpdm: Add DSB dataset support
>>>> coresight-tpdm: Add integration test support
>>>> docs: sysfs: coresight: Add sysfs ABI documentation for TPDM
>>>> Coresight: Add TPDA link driver
>>>> dt-bindings: arm: Adds CoreSight TPDA hardware definitions
>>>> ARM: dts: msm: Add coresight components for SM8250
>>>>
>>>> .../testing/sysfs-bus-coresight-devices-tpdm | 6 +
>>>> .../bindings/arm/coresight-tpda.yaml | 129 ++++
>>>> .../bindings/arm/coresight-tpdm.yaml | 81 ++
>>>> .../devicetree/bindings/arm/coresight.txt | 7 +
>>>> MAINTAINERS | 1 +
>>>> .../arm64/boot/dts/qcom/sm8250-coresight.dtsi | 690 ++++++++++++++++++
>>>> arch/arm64/boot/dts/qcom/sm8250.dtsi | 2 +
>>>> drivers/hwtracing/coresight/Kconfig | 33 +
>>>> drivers/hwtracing/coresight/Makefile | 2 +
>>>> drivers/hwtracing/coresight/coresight-core.c | 127 ++--
>>>> drivers/hwtracing/coresight/coresight-tpda.c | 193 +++++
>>>> drivers/hwtracing/coresight/coresight-tpda.h | 32 +
>>>> drivers/hwtracing/coresight/coresight-tpdm.c | 270 +++++++
>>>> drivers/hwtracing/coresight/coresight-tpdm.h | 57 ++
>>>> include/linux/coresight-pmu.h | 11 +
>>>> include/linux/coresight.h | 1 +
>>>> 16 files changed, 1592 insertions(+), 50 deletions(-)
>>>> create mode 100644 Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm
>>>> create mode 100644 Documentation/devicetree/bindings/arm/coresight-tpda.yaml
>>>> create mode 100644 Documentation/devicetree/bindings/arm/coresight-tpdm.yaml
>>>> create mode 100644 arch/arm64/boot/dts/qcom/sm8250-coresight.dtsi
>>>> create mode 100644 drivers/hwtracing/coresight/coresight-tpda.c
>>>> create mode 100644 drivers/hwtracing/coresight/coresight-tpda.h
>>>> create mode 100644 drivers/hwtracing/coresight/coresight-tpdm.c
>>>> create mode 100644 drivers/hwtracing/coresight/coresight-tpdm.h
>>>>
>>>> --
>>>> 2.17.1
>>>>
>>> --
>>> Mike Leach
>>> Principal Engineer, ARM Ltd.
>>> Manchester Design Centre. UK
>
>
^ permalink raw reply [flat|nested] 22+ messages in thread