[PATCH] irqchip/gic-v4.1: Ensure accessing the correct RD when writing INVALLR

[PATCH] irqchip/gic-v4.1: Ensure accessing the correct RD when writing INVALLR

[Zenghui Yu]

The GICv4.1 spec tells us that it's CONSTRAINED UNPREDICTABLE to issue a
register-based invalidation operation for a vPEID not mapped to that RD,
or another RD within the same CommonLPIAff group.

To follow this rule, commit f3a059219bc7 ("irqchip/gic-v4.1: Ensure mutual
exclusion between vPE affinity change and RD access") tried to address the
race between the RD accesses and the vPE affinity change, but somehow
forgot to take GICR_INVALLR into account. Let's take the vpe_lock before
evaluating vpe->col_idx to fix it.

Signed-off-by: Zenghui Yu <yuzenghui@huawei.com>
---
 drivers/irqchip/irq-gic-v3-its.c | 10 +++++++---
 1 file changed, 7 insertions(+), 3 deletions(-)

diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c
index da44bfa48bc2..50a04cca8207 100644
--- a/drivers/irqchip/irq-gic-v3-its.c
+++ b/drivers/irqchip/irq-gic-v3-its.c
@@ -4087,18 +4087,22 @@ static void its_vpe_4_1_deschedule(struct its_vpe *vpe,
 static void its_vpe_4_1_invall(struct its_vpe *vpe)
 {
 	void __iomem *rdbase;
+	unsigned long flags;
 	u64 val;
+	int cpu;
 
 	val  = GICR_INVALLR_V;
 	val |= FIELD_PREP(GICR_INVALLR_VPEID, vpe->vpe_id);
 
 	/* Target the redistributor this vPE is currently known on */
-	raw_spin_lock(&gic_data_rdist_cpu(vpe->col_idx)->rd_lock);
-	rdbase = per_cpu_ptr(gic_rdists->rdist, vpe->col_idx)->rd_base;
+	cpu = vpe_to_cpuid_lock(vpe, &flags);
+	raw_spin_lock(&gic_data_rdist_cpu(cpu)->rd_lock);
+	rdbase = per_cpu_ptr(gic_rdists->rdist, cpu)->rd_base;
 	gic_write_lpir(val, rdbase + GICR_INVALLR);
 
 	wait_for_syncr(rdbase);
-	raw_spin_unlock(&gic_data_rdist_cpu(vpe->col_idx)->rd_lock);
+	raw_spin_unlock(&gic_data_rdist_cpu(cpu)->rd_lock);
+	vpe_to_cpuid_unlock(vpe, flags);
 }
 
 static int its_vpe_4_1_set_vcpu_affinity(struct irq_data *d, void *vcpu_info)
-- 
2.19.1

Re: [PATCH] irqchip/gic-v4.1: Ensure accessing the correct RD when writing INVALLR

[Marc Zyngier]

On Thu, 09 Jul 2020 14:49:59 +0100,
Zenghui Yu <yuzenghui@huawei.com> wrote:
> 
> The GICv4.1 spec tells us that it's CONSTRAINED UNPREDICTABLE to issue a
> register-based invalidation operation for a vPEID not mapped to that RD,
> or another RD within the same CommonLPIAff group.
> 
> To follow this rule, commit f3a059219bc7 ("irqchip/gic-v4.1: Ensure mutual
> exclusion between vPE affinity change and RD access") tried to address the
> race between the RD accesses and the vPE affinity change, but somehow
> forgot to take GICR_INVALLR into account. Let's take the vpe_lock before
> evaluating vpe->col_idx to fix it.
> 
> Signed-off-by: Zenghui Yu <yuzenghui@huawei.com>

Shouldn't this deserve a Fixes: tag?

Thanks,

	M.

> ---
>  drivers/irqchip/irq-gic-v3-its.c | 10 +++++++---
>  1 file changed, 7 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c
> index da44bfa48bc2..50a04cca8207 100644
> --- a/drivers/irqchip/irq-gic-v3-its.c
> +++ b/drivers/irqchip/irq-gic-v3-its.c
> @@ -4087,18 +4087,22 @@ static void its_vpe_4_1_deschedule(struct its_vpe *vpe,
>  static void its_vpe_4_1_invall(struct its_vpe *vpe)
>  {
>  	void __iomem *rdbase;
> +	unsigned long flags;
>  	u64 val;
> +	int cpu;
>  
>  	val  = GICR_INVALLR_V;
>  	val |= FIELD_PREP(GICR_INVALLR_VPEID, vpe->vpe_id);
>  
>  	/* Target the redistributor this vPE is currently known on */
> -	raw_spin_lock(&gic_data_rdist_cpu(vpe->col_idx)->rd_lock);
> -	rdbase = per_cpu_ptr(gic_rdists->rdist, vpe->col_idx)->rd_base;
> +	cpu = vpe_to_cpuid_lock(vpe, &flags);
> +	raw_spin_lock(&gic_data_rdist_cpu(cpu)->rd_lock);
> +	rdbase = per_cpu_ptr(gic_rdists->rdist, cpu)->rd_base;
>  	gic_write_lpir(val, rdbase + GICR_INVALLR);
>  
>  	wait_for_syncr(rdbase);
> -	raw_spin_unlock(&gic_data_rdist_cpu(vpe->col_idx)->rd_lock);
> +	raw_spin_unlock(&gic_data_rdist_cpu(cpu)->rd_lock);
> +	vpe_to_cpuid_unlock(vpe, flags);
>  }
>  
>  static int its_vpe_4_1_set_vcpu_affinity(struct irq_data *d, void *vcpu_info)
> -- 
> 2.19.1
> 
> 

-- 
Without deviation from the norm, progress is not possible.

Re: [PATCH] irqchip/gic-v4.1: Ensure accessing the correct RD when writing INVALLR

[Zenghui Yu]

Hi Marc,

On 2020/7/17 19:07, Marc Zyngier wrote:
> On Thu, 09 Jul 2020 14:49:59 +0100,
> Zenghui Yu <yuzenghui@huawei.com> wrote:
>>
>> The GICv4.1 spec tells us that it's CONSTRAINED UNPREDICTABLE to issue a
>> register-based invalidation operation for a vPEID not mapped to that RD,
>> or another RD within the same CommonLPIAff group.
>>
>> To follow this rule, commit f3a059219bc7 ("irqchip/gic-v4.1: Ensure mutual
>> exclusion between vPE affinity change and RD access") tried to address the
>> race between the RD accesses and the vPE affinity change, but somehow
>> forgot to take GICR_INVALLR into account. Let's take the vpe_lock before
>> evaluating vpe->col_idx to fix it.
>>
>> Signed-off-by: Zenghui Yu <yuzenghui@huawei.com>
> 
> Shouldn't this deserve a Fixes: tag?

Yes, I think a

Fixes: f3a059219bc7 ("irqchip/gic-v4.1: Ensure mutual exclusion between 
vPE affinity change and RD access")

should be enough. Should I resend a version with the tag added?


Thanks,
Zenghui

Re: [PATCH] irqchip/gic-v4.1: Ensure accessing the correct RD when writing INVALLR

[Marc Zyngier]

Hi Zenghui,

On 2020-07-20 03:27, Zenghui Yu wrote:
> Hi Marc,
> 
> On 2020/7/17 19:07, Marc Zyngier wrote:
>> On Thu, 09 Jul 2020 14:49:59 +0100,
>> Zenghui Yu <yuzenghui@huawei.com> wrote:
>>> 
>>> The GICv4.1 spec tells us that it's CONSTRAINED UNPREDICTABLE to 
>>> issue a
>>> register-based invalidation operation for a vPEID not mapped to that 
>>> RD,
>>> or another RD within the same CommonLPIAff group.
>>> 
>>> To follow this rule, commit f3a059219bc7 ("irqchip/gic-v4.1: Ensure 
>>> mutual
>>> exclusion between vPE affinity change and RD access") tried to 
>>> address the
>>> race between the RD accesses and the vPE affinity change, but somehow
>>> forgot to take GICR_INVALLR into account. Let's take the vpe_lock 
>>> before
>>> evaluating vpe->col_idx to fix it.
>>> 
>>> Signed-off-by: Zenghui Yu <yuzenghui@huawei.com>
>> 
>> Shouldn't this deserve a Fixes: tag?
> 
> Yes, I think a
> 
> Fixes: f3a059219bc7 ("irqchip/gic-v4.1: Ensure mutual exclusion
> between vPE affinity change and RD access")
> 
> should be enough. Should I resend a version with the tag added?

Yes, please, together with a Cc: stable@vger.kernel.org, as the
original patch is in 5.7 and I intend to take it via the 5.9
branch.

Thanks,

         M.
-- 
Jazz is not dead. It just smells funny...