From: Andy Lutomirski <luto@kernel.org>
To: "Chang S. Bae" <chang.seok.bae@intel.com>,
bp@suse.de, tglx@linutronix.de, mingo@kernel.org, x86@kernel.org
Cc: len.brown@intel.com, dave.hansen@intel.com, jing2.liu@intel.com,
ravi.v.shankar@intel.com, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v5 28/28] x86/fpu/amx: Clear the AMX state when appropriate
Date: Sun, 23 May 2021 20:13:38 -0700 [thread overview]
Message-ID: <1980c78b-d51b-c186-9179-f3c72692ad8a@kernel.org> (raw)
In-Reply-To: <20210523193259.26200-29-chang.seok.bae@intel.com>
On 5/23/21 12:32 PM, Chang S. Bae wrote:
> When AMX is enabled, and an AMX-task is saved, explicitly initialize the
> AMX state after the XSAVE.
>
> This assures that the kernel will only request idle states with clean AMX
> state. In the case of the C6 idle state, this allows the hardware to get to
> a deeper power saving condition.
>
> Signed-off-by: Chang S. Bae <chang.seok.bae@intel.com>
> Reviewed-by: Len Brown <len.brown@intel.com>
> Cc: x86@kernel.org
> Cc: linux-kernel@vger.kernel.org
> ---
> Changes from v4:
> * Added as a new patch. (Thomas Gleixner)
> ---
> arch/x86/include/asm/special_insns.h | 6 ++++++
> arch/x86/kernel/fpu/core.c | 8 ++++++++
> 2 files changed, 14 insertions(+)
>
> diff --git a/arch/x86/include/asm/special_insns.h b/arch/x86/include/asm/special_insns.h
> index 2acd6cb62328..f0ed063035eb 100644
> --- a/arch/x86/include/asm/special_insns.h
> +++ b/arch/x86/include/asm/special_insns.h
> @@ -306,6 +306,12 @@ static inline int enqcmds(void __iomem *dst, const void *src)
> return 0;
> }
>
> +static inline void tile_release(void)
> +{
> + /* Instruction opcode for TILERELEASE; supported in binutils >= 2.36. */
> + asm volatile(".byte 0xc4, 0xe2, 0x78, 0x49, 0xc0");
> +}
> +
> #endif /* __KERNEL__ */
>
> #endif /* _ASM_X86_SPECIAL_INSNS_H */
> diff --git a/arch/x86/kernel/fpu/core.c b/arch/x86/kernel/fpu/core.c
> index cccfeafe81e5..53a5869078b8 100644
> --- a/arch/x86/kernel/fpu/core.c
> +++ b/arch/x86/kernel/fpu/core.c
> @@ -106,6 +106,14 @@ int copy_fpregs_to_fpstate(struct fpu *fpu)
> */
> if (fpu->state->xsave.header.xfeatures & XFEATURE_MASK_AVX512)
> fpu->avx512_timestamp = jiffies;
> +
> + /*
> + * Since the current task's state is safely in the XSAVE buffer, TILERELEASE
> + * the TILE registers to guarantee that dirty state will not interfere with the
> + * hardware's ability to enter the core C6 idle state.
> + */
> + if (fpu->state_mask & XFEATURE_MASK_XTILE_DATA)
> + tile_release();
> return 1;
> }
>
>
This looks wrong -- you should also invalidate the state. And doing it
in the save path seems inefficient.
Can we do this just when going idle?
--Andy
next prev parent reply other threads:[~2021-05-24 3:13 UTC|newest]
Thread overview: 75+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-23 19:32 [PATCH v5 00/28] x86: Support Intel Advanced Matrix Extensions Chang S. Bae
2021-05-23 19:32 ` [PATCH v5 01/28] x86/fpu/xstate: Modify the initialization helper to handle both static and dynamic buffers Chang S. Bae
2021-05-23 19:32 ` [PATCH v5 02/28] x86/fpu/xstate: Modify state copy helpers " Chang S. Bae
2021-05-23 19:32 ` [PATCH v5 03/28] x86/fpu/xstate: Modify address finders " Chang S. Bae
2021-05-23 19:32 ` [PATCH v5 04/28] x86/fpu/xstate: Modify the context restore helper " Chang S. Bae
2021-05-23 19:32 ` [PATCH v5 05/28] x86/fpu/xstate: Add a new variable to indicate dynamic user states Chang S. Bae
2021-05-23 19:32 ` [PATCH v5 06/28] x86/fpu/xstate: Add new variables to indicate dynamic xstate buffer size Chang S. Bae
2021-05-23 19:32 ` [PATCH v5 07/28] x86/fpu/xstate: Calculate and remember dynamic xstate buffer sizes Chang S. Bae
2021-05-23 19:32 ` [PATCH v5 08/28] x86/fpu/xstate: Convert the struct fpu 'state' field to a pointer Chang S. Bae
2021-05-23 19:32 ` [PATCH v5 09/28] x86/fpu/xstate: Introduce helpers to manage the xstate buffer dynamically Chang S. Bae
2021-05-23 19:32 ` [PATCH v5 10/28] x86/fpu/xstate: Define the scope of the initial xstate data Chang S. Bae
2021-05-23 19:32 ` [PATCH v5 11/28] x86/fpu/xstate: Update the xstate save function to support dynamic states Chang S. Bae
2021-05-23 19:32 ` [PATCH v5 12/28] x86/fpu/xstate: Update the xstate buffer address finder " Chang S. Bae
2021-05-23 19:32 ` [PATCH v5 13/28] x86/fpu/xstate: Update the xstate context copy function " Chang S. Bae
2021-05-23 19:32 ` [PATCH v5 14/28] x86/fpu/xstate: Prevent unauthorised use of dynamic user state Chang S. Bae
2021-06-16 16:17 ` Dave Hansen
2021-06-16 16:27 ` Dave Hansen
2021-06-16 18:12 ` Andy Lutomirski
2021-06-16 18:47 ` Bae, Chang Seok
2021-06-16 19:01 ` Dave Hansen
2021-06-16 19:23 ` Bae, Chang Seok
2021-06-16 19:28 ` Dave Hansen
2021-06-16 19:37 ` Bae, Chang Seok
2021-06-28 10:11 ` Liu, Jing2
2021-06-29 17:43 ` Bae, Chang Seok
2021-06-29 17:54 ` Dave Hansen
2021-06-29 18:35 ` Bae, Chang Seok
2021-06-29 18:50 ` Dave Hansen
2021-06-29 19:13 ` Bae, Chang Seok
2021-06-29 19:26 ` Dave Hansen
2021-05-23 19:32 ` [PATCH v5 15/28] x86/arch_prctl: Create ARCH_GET_XSTATE/ARCH_PUT_XSTATE Chang S. Bae
2021-05-24 23:10 ` Len Brown
2021-05-25 17:27 ` Borislav Petkov
2021-05-25 17:33 ` Dave Hansen
2021-05-26 0:38 ` Len Brown
2021-05-27 11:14 ` second, sync-alloc syscall Borislav Petkov
2021-05-27 13:59 ` Len Brown
2021-05-27 19:35 ` Andy Lutomirski
2021-05-25 15:46 ` [PATCH v5 15/28] x86/arch_prctl: Create ARCH_GET_XSTATE/ARCH_PUT_XSTATE Dave Hansen
2021-05-23 19:32 ` [PATCH v5 16/28] x86/fpu/xstate: Support ptracer-induced xstate buffer expansion Chang S. Bae
2021-05-23 19:32 ` [PATCH v5 17/28] x86/fpu/xstate: Adjust the XSAVE feature table to address gaps in state component numbers Chang S. Bae
2021-05-23 19:32 ` [PATCH v5 18/28] x86/fpu/xstate: Disable xstate support if an inconsistent state is detected Chang S. Bae
2021-05-23 19:32 ` [PATCH v5 19/28] x86/cpufeatures/amx: Enumerate Advanced Matrix Extension (AMX) feature bits Chang S. Bae
2021-05-23 19:32 ` [PATCH v5 20/28] x86/fpu/amx: Define AMX state components and have it used for boot-time checks Chang S. Bae
2021-05-23 19:32 ` [PATCH v5 21/28] x86/fpu/amx: Initialize child's AMX state Chang S. Bae
2021-05-24 3:09 ` Andy Lutomirski
2021-05-24 17:37 ` Len Brown
2021-05-24 18:13 ` Andy Lutomirski
2021-05-24 18:21 ` Len Brown
2021-05-25 3:44 ` Andy Lutomirski
2021-05-23 19:32 ` [PATCH v5 22/28] x86/fpu/amx: Enable the AMX feature in 64-bit mode Chang S. Bae
2021-05-23 19:32 ` [PATCH v5 23/28] selftest/x86/amx: Test cases for the AMX state management Chang S. Bae
2021-05-23 19:32 ` [PATCH v5 24/28] x86/fpu/xstate: Use per-task xstate mask for saving xstate in signal frame Chang S. Bae
2021-05-24 3:15 ` Andy Lutomirski
2021-05-24 18:06 ` Len Brown
2021-05-25 4:47 ` Andy Lutomirski
2021-05-25 14:04 ` Len Brown
2021-05-23 19:32 ` [PATCH v5 25/28] x86/fpu/xstate: Skip writing zeros to signal frame for dynamic user states if in INIT-state Chang S. Bae
2021-05-24 3:25 ` Andy Lutomirski
2021-05-24 18:15 ` Len Brown
2021-05-24 18:29 ` Dave Hansen
2021-05-25 4:46 ` Andy Lutomirski
2021-05-23 19:32 ` [PATCH v5 26/28] selftest/x86/amx: Test case for AMX state copy optimization in signal delivery Chang S. Bae
2021-05-23 19:32 ` [PATCH v5 27/28] x86/insn/amx: Add TILERELEASE instruction to the opcode map Chang S. Bae
2021-05-23 19:32 ` [PATCH v5 28/28] x86/fpu/amx: Clear the AMX state when appropriate Chang S. Bae
2021-05-24 3:13 ` Andy Lutomirski [this message]
2021-05-24 14:10 ` Dave Hansen
2021-05-24 17:32 ` Len Brown
2021-05-24 17:39 ` Dave Hansen
2021-05-24 18:24 ` Len Brown
2021-05-27 11:56 ` Peter Zijlstra
2021-05-27 14:02 ` Len Brown
2021-05-24 14:06 ` Dave Hansen
2021-05-24 17:34 ` Len Brown
2021-05-24 21:11 ` [PATCH v5-fix " Chang S. Bae
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