[PATCH V4 0/4] Add Xilinx's ZynqMP AES-GCM driver support

[PATCH V4 0/4] Add Xilinx's ZynqMP AES-GCM driver support

[Kalyani Akula]

This patch set adds support for
- dt-binding docs for Xilinx ZynqMP AES driver
- Adds device tree node for ZynqMP AES driver
- Adds communication layer support for aes in zynqmp.c
- Adds Xilinx ZynqMP driver for AES Algorithm

V4 Changes :
- Addressed review comments.

V3 Changes :
- Added software fallback in cases where HW doesnt have  the capability to handle the request.
- Removed use of global variable for storing the driver data.
- Enabled CONFIG_CRYPTO_MANAGER_EXTRA_TESTS=y and executed all  the kernel selftests. Also covered tests with tcrypt module.

V2 Changes :
- Converted RFC PATCH to PATCH
- Removed ALG_SET_KEY_TYPE that was added to support keytype
  attribute. Taken using setkey interface.
- Removed deprecated BLKCIPHER in Kconfig
- Erased Key/IV from the buffer.
- Renamed zynqmp-aes driver to zynqmp-aes-gcm.
- Addressed few other review comments


Kalyani Akula (4):
  dt-bindings: crypto: Add bindings for ZynqMP AES driver
  ARM64: zynqmp: Add Xilinix AES node.
  firmware: xilinx: Add ZynqMP aes API for AES functionality
  crypto: Add Xilinx AES driver

 .../devicetree/bindings/crypto/xlnx,zynqmp-aes.txt |  12 +
 arch/arm64/boot/dts/xilinx/zynqmp.dtsi             |   5 +
 drivers/crypto/Kconfig                             |  11 +
 drivers/crypto/Makefile                            |   1 +
 drivers/crypto/xilinx/Makefile                     |   3 +
 drivers/crypto/xilinx/zynqmp-aes-gcm.c             | 469 +++++++++++++++++++++
 drivers/firmware/xilinx/zynqmp.c                   |  23 +
 include/linux/firmware/xlnx-zynqmp.h               |   2 +
 8 files changed, 526 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/crypto/xlnx,zynqmp-aes.txt
 create mode 100644 drivers/crypto/xilinx/Makefile
 create mode 100644 drivers/crypto/xilinx/zynqmp-aes-gcm.c

-- 
1.9.5

[PATCH V4 1/4] dt-bindings: crypto: Add bindings for ZynqMP AES driver

[Kalyani Akula]

Add documentation to describe Xilinx ZynqMP AES driver bindings.

Signed-off-by: Kalyani Akula <kalyani.akula@xilinx.com>
---
 Documentation/devicetree/bindings/crypto/xlnx,zynqmp-aes.txt | 12 ++++++++++++
 1 file changed, 12 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/crypto/xlnx,zynqmp-aes.txt

diff --git a/Documentation/devicetree/bindings/crypto/xlnx,zynqmp-aes.txt b/Documentation/devicetree/bindings/crypto/xlnx,zynqmp-aes.txt
new file mode 100644
index 0000000..226bfb9
--- /dev/null
+++ b/Documentation/devicetree/bindings/crypto/xlnx,zynqmp-aes.txt
@@ -0,0 +1,12 @@
+Xilinx ZynqMP AES hw acceleration support
+
+The ZynqMP PS-AES hw accelerator is used to encrypt/decrypt
+the given user data.
+
+Required properties:
+- compatible: should contain "xlnx,zynqmp-aes"
+
+Example:
+	zynqmp_aes {
+		compatible = "xlnx,zynqmp-aes";
+	};
-- 
1.9.5

[PATCH V4 2/4] ARM64: zynqmp: Add Xilinix AES node.

[Kalyani Akula]

This patch adds a AES DT node for Xilinx ZynqMP SoC.

Signed-off-by: Kalyani Akula <kalyani.akula@xilinx.com>
---
 arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
index 9aa6734..9a0b7f4 100644
--- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
+++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
@@ -626,4 +626,9 @@
 			timeout-sec = <10>;
 		};
 	};
+
+	xlnx_aes: zynqmp_aes {
+		compatible = "xlnx,zynqmp-aes";
+	};
+
 };
-- 
1.9.5

[PATCH V4 3/4] firmware: xilinx: Add ZynqMP aes API for AES functionality

[Kalyani Akula]

Add ZynqMP firmware AES API to perform encryption/decryption of given data.

Signed-off-by: Kalyani Akula <kalyani.akula@xilinx.com>
---
 drivers/firmware/xilinx/zynqmp.c     | 23 +++++++++++++++++++++++
 include/linux/firmware/xlnx-zynqmp.h |  2 ++
 2 files changed, 25 insertions(+)

diff --git a/drivers/firmware/xilinx/zynqmp.c b/drivers/firmware/xilinx/zynqmp.c
index fd3d837..7ddf38e 100644
--- a/drivers/firmware/xilinx/zynqmp.c
+++ b/drivers/firmware/xilinx/zynqmp.c
@@ -664,6 +664,28 @@ static int zynqmp_pm_set_requirement(const u32 node, const u32 capabilities,
 				   qos, ack, NULL);
 }
 
+/**
+ * zynqmp_pm_aes - Access AES hardware to encrypt/decrypt the data using
+ * AES-GCM core.
+ * @address:	Address of the AesParams structure.
+ * @out:	Returned output value
+ *
+ * Return:	Returns status, either success or error code.
+ */
+static int zynqmp_pm_aes_engine(const u64 address, u32 *out)
+{
+	u32 ret_payload[PAYLOAD_ARG_CNT];
+	int ret;
+
+	if (!out)
+		return -EINVAL;
+
+	ret = zynqmp_pm_invoke_fn(PM_SECURE_AES, upper_32_bits(address),
+				  lower_32_bits(address),
+				  0, 0, ret_payload);
+	*out = ret_payload[1];
+	return ret;
+}
 static const struct zynqmp_eemi_ops eemi_ops = {
 	.get_api_version = zynqmp_pm_get_api_version,
 	.get_chipid = zynqmp_pm_get_chipid,
@@ -687,6 +709,7 @@ static int zynqmp_pm_set_requirement(const u32 node, const u32 capabilities,
 	.set_requirement = zynqmp_pm_set_requirement,
 	.fpga_load = zynqmp_pm_fpga_load,
 	.fpga_get_status = zynqmp_pm_fpga_get_status,
+	.aes = zynqmp_pm_aes_engine,
 };
 
 /**
diff --git a/include/linux/firmware/xlnx-zynqmp.h b/include/linux/firmware/xlnx-zynqmp.h
index 778abbb..508edd7 100644
--- a/include/linux/firmware/xlnx-zynqmp.h
+++ b/include/linux/firmware/xlnx-zynqmp.h
@@ -77,6 +77,7 @@ enum pm_api_id {
 	PM_CLOCK_GETRATE,
 	PM_CLOCK_SETPARENT,
 	PM_CLOCK_GETPARENT,
+	PM_SECURE_AES = 47,
 };
 
 /* PMU-FW return status codes */
@@ -294,6 +295,7 @@ struct zynqmp_eemi_ops {
 			       const u32 capabilities,
 			       const u32 qos,
 			       const enum zynqmp_pm_request_ack ack);
+	int (*aes)(const u64 address, u32 *out);
 };
 
 int zynqmp_pm_invoke_fn(u32 pm_api_id, u32 arg0, u32 arg1,
-- 
1.9.5

[PATCH V4 4/4] crypto: Add Xilinx AES driver

[Kalyani Akula]

This patch adds AES driver support for the Xilinx ZynqMP SoC.

Signed-off-by: Kalyani Akula <kalyani.akula@xilinx.com>
---
 drivers/crypto/Kconfig                 |  11 +
 drivers/crypto/Makefile                |   1 +
 drivers/crypto/xilinx/Makefile         |   3 +
 drivers/crypto/xilinx/zynqmp-aes-gcm.c | 469 +++++++++++++++++++++++++++++++++
 4 files changed, 484 insertions(+)
 create mode 100644 drivers/crypto/xilinx/Makefile
 create mode 100644 drivers/crypto/xilinx/zynqmp-aes-gcm.c

diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig
index 1fb622f..8e7d3a9 100644
--- a/drivers/crypto/Kconfig
+++ b/drivers/crypto/Kconfig
@@ -696,6 +696,17 @@ config CRYPTO_DEV_ROCKCHIP
 	help
 	  This driver interfaces with the hardware crypto accelerator.
 	  Supporting cbc/ecb chainmode, and aes/des/des3_ede cipher mode.
+config CRYPTO_DEV_ZYNQMP_AES
+	tristate "Support for Xilinx ZynqMP AES hw accelerator"
+	depends on ARCH_ZYNQMP || COMPILE_TEST
+	select CRYPTO_AES
+	select CRYPTO_ENGINE
+	select CRYPTO_AEAD
+	help
+	  Xilinx ZynqMP has AES-GCM engine used for symmetric key
+	  encryption and decryption. This driver interfaces with AES hw
+	  accelerator. Select this if you want to use the ZynqMP module
+	  for AES algorithms.
 
 config CRYPTO_DEV_MEDIATEK
 	tristate "MediaTek's EIP97 Cryptographic Engine driver"
diff --git a/drivers/crypto/Makefile b/drivers/crypto/Makefile
index afc4753..50184377 100644
--- a/drivers/crypto/Makefile
+++ b/drivers/crypto/Makefile
@@ -47,4 +47,5 @@ obj-$(CONFIG_CRYPTO_DEV_VMX) += vmx/
 obj-$(CONFIG_CRYPTO_DEV_BCM_SPU) += bcm/
 obj-$(CONFIG_CRYPTO_DEV_SAFEXCEL) += inside-secure/
 obj-$(CONFIG_CRYPTO_DEV_ARTPEC6) += axis/
+obj-$(CONFIG_CRYPTO_DEV_ZYNQMP_AES) += xilinx/
 obj-y += hisilicon/
diff --git a/drivers/crypto/xilinx/Makefile b/drivers/crypto/xilinx/Makefile
new file mode 100644
index 0000000..16bdda7
--- /dev/null
+++ b/drivers/crypto/xilinx/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0-only
+obj-$(CONFIG_CRYPTO_DEV_ZYNQMP_AES) += zynqmp-aes-gcm.o
+
diff --git a/drivers/crypto/xilinx/zynqmp-aes-gcm.c b/drivers/crypto/xilinx/zynqmp-aes-gcm.c
new file mode 100644
index 0000000..534105b
--- /dev/null
+++ b/drivers/crypto/xilinx/zynqmp-aes-gcm.c
@@ -0,0 +1,469 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Xilinx ZynqMP AES Driver.
+ * Copyright (c) 2019 Xilinx Inc.
+ */
+
+#include <crypto/aes.h>
+#include <crypto/engine.h>
+#include <crypto/gcm.h>
+#include <crypto/internal/aead.h>
+#include <crypto/scatterwalk.h>
+
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+
+#include <linux/firmware/xlnx-zynqmp.h>
+
+#define DRIVER_NAME		"zynqmp-aes"
+#define ZYNQMP_DMA_BIT_MASK	32U
+
+#define ZYNQMP_AES_KEY_SIZE		AES_KEYSIZE_256
+#define ZYNQMP_AES_AUTH_SIZE		16U
+#define ZYNQMP_KEY_SRC_SEL_KEY_LEN	1U
+#define ZYNQMP_AES_BLK_SIZE		1U
+#define ZYNQMP_AES_MIN_INPUT_BLK_SIZE	4U
+#define ZYNQMP_AES_WORD_LEN		4U
+
+#define ZYNQMP_AES_GCM_TAG_MISMATCH_ERR		0x01
+#define ZYNQMP_AES_WRONG_KEY_SRC_ERR		0x13
+#define ZYNQMP_AES_PUF_NOT_PROGRAMMED		0xE300
+
+enum zynqmp_aead_op {
+	ZYNQMP_AES_DECRYPT = 0,
+	ZYNQMP_AES_ENCRYPT
+};
+
+enum zynqmp_aead_keysrc {
+	ZYNQMP_AES_KUP_KEY = 0,
+	ZYNQMP_AES_DEV_KEY,
+	ZYNQMP_AES_PUF_KEY
+};
+
+struct zynqmp_aead_drv_ctx {
+	union {
+		struct aead_alg aead;
+	} alg;
+	struct device *dev;
+	struct crypto_engine *engine;
+	const struct zynqmp_eemi_ops *eemi_ops;
+};
+
+struct zynqmp_aead_hw_req {
+	u64 src;
+	u64 iv;
+	u64 key;
+	u64 dst;
+	u64 size;
+	u64 op;
+	u64 keysrc;
+};
+
+struct zynqmp_aead_tfm_ctx {
+	struct crypto_engine_ctx engine_ctx;
+	struct device *dev;
+	u8 key[ZYNQMP_AES_KEY_SIZE];
+	u8 *iv;
+	u32 keylen;
+	u32 authsize;
+	enum zynqmp_aead_keysrc keysrc;
+	struct crypto_aead *fbk_cipher;
+};
+
+struct zynqmp_aead_req_ctx {
+	enum zynqmp_aead_op op;
+};
+
+static int zynqmp_aes_aead_cipher(struct aead_request *req)
+{
+	struct crypto_aead *aead = crypto_aead_reqtfm(req);
+	struct zynqmp_aead_tfm_ctx *tfm_ctx = crypto_aead_ctx(aead);
+	struct zynqmp_aead_req_ctx *rq_ctx = aead_request_ctx(req);
+	struct device *dev = tfm_ctx->dev;
+	struct aead_alg *alg = crypto_aead_alg(aead);
+	struct zynqmp_aead_drv_ctx *drv_ctx;
+	struct zynqmp_aead_hw_req *hwreq;
+	dma_addr_t dma_addr_data, dma_addr_hw_req;
+	unsigned int data_size;
+	unsigned int status;
+	size_t dma_size;
+	char *kbuf;
+	int err;
+
+	drv_ctx = container_of(alg, struct zynqmp_aead_drv_ctx, alg.aead);
+
+	if (!drv_ctx->eemi_ops->aes)
+		return -ENOTSUPP;
+
+	if (tfm_ctx->keysrc == ZYNQMP_AES_KUP_KEY)
+		dma_size = req->cryptlen + ZYNQMP_AES_KEY_SIZE
+			   + GCM_AES_IV_SIZE;
+	else
+		dma_size = req->cryptlen + GCM_AES_IV_SIZE;
+
+	kbuf = dma_alloc_coherent(dev, dma_size, &dma_addr_data, GFP_KERNEL);
+	if (!kbuf)
+		return -ENOMEM;
+
+	hwreq = dma_alloc_coherent(dev, sizeof(struct zynqmp_aead_hw_req),
+				   &dma_addr_hw_req, GFP_KERNEL);
+	if (!hwreq) {
+		dma_free_coherent(dev, dma_size, kbuf, dma_addr_data);
+		return -ENOMEM;
+	}
+
+	data_size = req->cryptlen;
+	scatterwalk_map_and_copy(kbuf, req->src, 0, req->cryptlen, 0);
+	memcpy(kbuf + data_size, req->iv, GCM_AES_IV_SIZE);
+
+	hwreq->src = dma_addr_data;
+	hwreq->dst = dma_addr_data;
+	hwreq->iv = hwreq->src + data_size;
+	hwreq->keysrc = tfm_ctx->keysrc;
+	hwreq->op = rq_ctx->op;
+
+	if (hwreq->op == ZYNQMP_AES_ENCRYPT)
+		hwreq->size = data_size;
+	else
+		hwreq->size = data_size - ZYNQMP_AES_AUTH_SIZE;
+
+	if (hwreq->keysrc == ZYNQMP_AES_KUP_KEY) {
+		memcpy(kbuf + data_size + GCM_AES_IV_SIZE,
+		       tfm_ctx->key, ZYNQMP_AES_KEY_SIZE);
+
+		hwreq->key = hwreq->src + data_size + GCM_AES_IV_SIZE;
+	} else {
+		hwreq->key = 0;
+	}
+
+	drv_ctx->eemi_ops->aes(dma_addr_hw_req, &status);
+
+	if (status) {
+		switch (status) {
+		case ZYNQMP_AES_GCM_TAG_MISMATCH_ERR:
+			dev_err(dev, "ERROR: Gcm Tag mismatch\n");
+			break;
+		case ZYNQMP_AES_WRONG_KEY_SRC_ERR:
+			dev_err(dev, "ERROR: Wrong KeySrc, enable secure mode\n");
+			break;
+		case ZYNQMP_AES_PUF_NOT_PROGRAMMED:
+			dev_err(dev, "ERROR: PUF is not registered\n");
+			break;
+		default:
+			dev_err(dev, "ERROR: Unknown error\n");
+			break;
+		}
+		err = -status;
+	} else {
+		if (hwreq->op == ZYNQMP_AES_ENCRYPT)
+			data_size = data_size + ZYNQMP_AES_AUTH_SIZE;
+		else
+			data_size = data_size - ZYNQMP_AES_AUTH_SIZE;
+
+		sg_copy_from_buffer(req->dst, sg_nents(req->dst),
+				    kbuf, data_size);
+		err = 0;
+	}
+
+	if (kbuf) {
+		memzero_explicit(kbuf, dma_size);
+		dma_free_coherent(dev, dma_size, kbuf, dma_addr_data);
+	}
+	if (hwreq) {
+		memzero_explicit(hwreq, sizeof(struct zynqmp_aead_hw_req));
+		dma_free_coherent(dev, sizeof(struct zynqmp_aead_hw_req),
+				  hwreq, dma_addr_hw_req);
+	}
+	return err;
+}
+
+static int zynqmp_fallback_check(struct zynqmp_aead_tfm_ctx *tfm_ctx,
+				 struct aead_request *req)
+{
+	int need_fallback = 0;
+	struct zynqmp_aead_req_ctx *rq_ctx = aead_request_ctx(req);
+
+	if (tfm_ctx->authsize != ZYNQMP_AES_AUTH_SIZE)
+		need_fallback = 1;
+
+	if (tfm_ctx->keysrc == ZYNQMP_AES_KUP_KEY &&
+	    tfm_ctx->keylen != ZYNQMP_AES_KEY_SIZE) {
+		need_fallback = 1;
+	}
+	if (req->assoclen != 0 ||
+	    req->cryptlen < ZYNQMP_AES_MIN_INPUT_BLK_SIZE) {
+		need_fallback = 1;
+	}
+	if ((req->cryptlen % ZYNQMP_AES_WORD_LEN) != 0)
+		need_fallback = 1;
+
+	if (rq_ctx->op == ZYNQMP_AES_DECRYPT &&
+	    req->cryptlen <= ZYNQMP_AES_AUTH_SIZE) {
+		need_fallback = 1;
+	}
+	return need_fallback;
+}
+
+static int zynqmp_handle_aes_req(struct crypto_engine *engine,
+				 void *req)
+{
+	struct aead_request *areq =
+				container_of(req, struct aead_request, base);
+	struct crypto_aead *aead = crypto_aead_reqtfm(req);
+	struct zynqmp_aead_tfm_ctx *tfm_ctx = crypto_aead_ctx(aead);
+	struct zynqmp_aead_req_ctx *rq_ctx = aead_request_ctx(areq);
+	struct aead_request *subreq = aead_request_ctx(req);
+	int need_fallback;
+	int err;
+
+	need_fallback = zynqmp_fallback_check(tfm_ctx, areq);
+
+	if (need_fallback) {
+		aead_request_set_tfm(subreq, tfm_ctx->fbk_cipher);
+
+		aead_request_set_callback(subreq, areq->base.flags,
+					  NULL, NULL);
+		aead_request_set_crypt(subreq, areq->src, areq->dst,
+				       areq->cryptlen, areq->iv);
+		aead_request_set_ad(subreq, areq->assoclen);
+		if (rq_ctx->op == ZYNQMP_AES_ENCRYPT)
+			err = crypto_aead_encrypt(subreq);
+		else
+			err = crypto_aead_decrypt(subreq);
+	} else {
+		err = zynqmp_aes_aead_cipher(areq);
+	}
+
+	crypto_finalize_aead_request(engine, areq, err);
+	return 0;
+}
+
+static int zynqmp_aes_aead_setkey(struct crypto_aead *aead, const u8 *key,
+				  unsigned int keylen)
+{
+	struct crypto_tfm *tfm = crypto_aead_tfm(aead);
+	struct zynqmp_aead_tfm_ctx *tfm_ctx =
+			(struct zynqmp_aead_tfm_ctx *)crypto_tfm_ctx(tfm);
+	unsigned char keysrc;
+	int err;
+
+	if (keylen == ZYNQMP_KEY_SRC_SEL_KEY_LEN) {
+		keysrc = *key;
+		if (keysrc == ZYNQMP_AES_KUP_KEY ||
+		    keysrc == ZYNQMP_AES_DEV_KEY ||
+		    keysrc == ZYNQMP_AES_PUF_KEY) {
+			tfm_ctx->keysrc = (enum zynqmp_aead_keysrc)keysrc;
+		} else {
+			tfm_ctx->keylen = keylen;
+		}
+	} else {
+		tfm_ctx->keylen = keylen;
+		if (keylen == ZYNQMP_AES_KEY_SIZE) {
+			tfm_ctx->keysrc = ZYNQMP_AES_KUP_KEY;
+			memcpy(tfm_ctx->key, key, keylen);
+		}
+	}
+
+	tfm_ctx->fbk_cipher->base.crt_flags &= ~CRYPTO_TFM_REQ_MASK;
+	tfm_ctx->fbk_cipher->base.crt_flags |= (aead->base.crt_flags &
+					CRYPTO_TFM_REQ_MASK);
+
+	err = crypto_aead_setkey(tfm_ctx->fbk_cipher, key, keylen);
+	if (err) {
+		aead->base.crt_flags &= ~CRYPTO_TFM_RES_MASK;
+		aead->base.crt_flags |=
+				(tfm_ctx->fbk_cipher->base.crt_flags &
+				 CRYPTO_TFM_RES_MASK);
+	}
+
+	return err;
+}
+
+static int zynqmp_aes_aead_setauthsize(struct crypto_aead *aead,
+				       unsigned int authsize)
+{
+	struct crypto_tfm *tfm = crypto_aead_tfm(aead);
+	struct zynqmp_aead_tfm_ctx *tfm_ctx =
+			(struct zynqmp_aead_tfm_ctx *)crypto_tfm_ctx(tfm);
+
+	tfm_ctx->authsize = authsize;
+	return crypto_aead_setauthsize(tfm_ctx->fbk_cipher, authsize);
+}
+
+static int zynqmp_aes_aead_encrypt(struct aead_request *req)
+{
+	struct zynqmp_aead_drv_ctx *drv_ctx;
+	struct crypto_aead *aead = crypto_aead_reqtfm(req);
+	struct aead_alg *alg = crypto_aead_alg(aead);
+	struct zynqmp_aead_req_ctx *rq_ctx = aead_request_ctx(req);
+
+	rq_ctx->op = ZYNQMP_AES_ENCRYPT;
+	drv_ctx = container_of(alg, struct zynqmp_aead_drv_ctx, alg.aead);
+
+	return crypto_transfer_aead_request_to_engine(drv_ctx->engine, req);
+}
+
+static int zynqmp_aes_aead_decrypt(struct aead_request *req)
+{
+	struct zynqmp_aead_drv_ctx *drv_ctx;
+	struct crypto_aead *aead = crypto_aead_reqtfm(req);
+	struct aead_alg *alg = crypto_aead_alg(aead);
+	struct zynqmp_aead_req_ctx *rq_ctx = aead_request_ctx(req);
+
+	rq_ctx->op = ZYNQMP_AES_DECRYPT;
+	drv_ctx = container_of(alg, struct zynqmp_aead_drv_ctx, alg.aead);
+
+	return crypto_transfer_aead_request_to_engine(drv_ctx->engine, req);
+}
+
+static int zynqmp_aes_aead_init(struct crypto_aead *aead)
+{
+	struct crypto_tfm *tfm = crypto_aead_tfm(aead);
+	struct zynqmp_aead_tfm_ctx *tfm_ctx =
+		(struct zynqmp_aead_tfm_ctx *)crypto_tfm_ctx(tfm);
+	struct zynqmp_aead_drv_ctx *drv_ctx;
+	struct aead_alg *alg = crypto_aead_alg(aead);
+
+	drv_ctx = container_of(alg, struct zynqmp_aead_drv_ctx, alg.aead);
+	tfm_ctx->dev = drv_ctx->dev;
+
+	tfm_ctx->engine_ctx.op.do_one_request = zynqmp_handle_aes_req;
+	tfm_ctx->engine_ctx.op.prepare_request = NULL;
+	tfm_ctx->engine_ctx.op.unprepare_request = NULL;
+
+	tfm_ctx->fbk_cipher = crypto_alloc_aead(drv_ctx->alg.aead.base.cra_name,
+						0,
+						CRYPTO_ALG_NEED_FALLBACK);
+
+	if (IS_ERR(tfm_ctx->fbk_cipher)) {
+		pr_err("%s() Error: failed to allocate fallback for %s\n",
+		       __func__, drv_ctx->alg.aead.base.cra_name);
+		return PTR_ERR(tfm_ctx->fbk_cipher);
+	}
+
+	crypto_aead_set_reqsize(aead,
+				max(sizeof(struct zynqmp_aead_req_ctx),
+				    sizeof(struct aead_request) +
+				    crypto_aead_reqsize(tfm_ctx->fbk_cipher)));
+	return 0;
+}
+
+static void zynqmp_aes_aead_exit(struct crypto_aead *aead)
+{
+	struct crypto_tfm *tfm = crypto_aead_tfm(aead);
+	struct zynqmp_aead_tfm_ctx *tfm_ctx =
+			(struct zynqmp_aead_tfm_ctx *)crypto_tfm_ctx(tfm);
+
+	if (tfm_ctx->fbk_cipher) {
+		crypto_free_aead(tfm_ctx->fbk_cipher);
+		tfm_ctx->fbk_cipher = NULL;
+	}
+	memzero_explicit(tfm_ctx, sizeof(struct zynqmp_aead_tfm_ctx));
+}
+
+static struct zynqmp_aead_drv_ctx aes_drv_ctx = {
+	.alg.aead = {
+		.setkey		= zynqmp_aes_aead_setkey,
+		.setauthsize	= zynqmp_aes_aead_setauthsize,
+		.encrypt	= zynqmp_aes_aead_encrypt,
+		.decrypt	= zynqmp_aes_aead_decrypt,
+		.init		= zynqmp_aes_aead_init,
+		.exit		= zynqmp_aes_aead_exit,
+		.ivsize		= GCM_AES_IV_SIZE,
+		.maxauthsize	= ZYNQMP_AES_AUTH_SIZE,
+		.base = {
+		.cra_name		= "gcm(aes)",
+		.cra_driver_name	= "xilinx-zynqmp-aes-gcm",
+		.cra_priority		= 200,
+		.cra_flags		= CRYPTO_ALG_TYPE_AEAD |
+					  CRYPTO_ALG_ASYNC |
+					  CRYPTO_ALG_KERN_DRIVER_ONLY |
+					  CRYPTO_ALG_NEED_FALLBACK,
+		.cra_blocksize		= ZYNQMP_AES_BLK_SIZE,
+		.cra_ctxsize		= sizeof(struct zynqmp_aead_tfm_ctx),
+		.cra_module		= THIS_MODULE,
+		}
+	}
+};
+
+static int zynqmp_aes_aead_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	int err = -1;
+
+	if (!pdev->dev.of_node)
+		return -ENODEV;
+
+	/* ZynqMp AES driver supports only one instance */
+	if (!aes_drv_ctx.dev)
+		aes_drv_ctx.dev = dev;
+
+	aes_drv_ctx.eemi_ops = zynqmp_pm_get_eemi_ops();
+	if (IS_ERR(aes_drv_ctx.eemi_ops)) {
+		dev_err(dev, "Failed to get ZynqMP EEMI interface\n");
+		return PTR_ERR(aes_drv_ctx.eemi_ops);
+	}
+
+	err = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(ZYNQMP_DMA_BIT_MASK));
+	if (err < 0) {
+		dev_err(dev, "No usable DMA configuration\n");
+		return err;
+	}
+
+	aes_drv_ctx.engine = crypto_engine_alloc_init(dev, 1);
+	if (!aes_drv_ctx.engine) {
+		dev_err(dev, "Cannot alloc AES engine\n");
+		err = -ENOMEM;
+		goto err_engine;
+	}
+
+	err = crypto_engine_start(aes_drv_ctx.engine);
+	if (err) {
+		dev_err(dev, "Cannot start AES engine\n");
+		goto err_engine;
+	}
+
+	err = crypto_register_aead(&aes_drv_ctx.alg.aead);
+	if (err < 0) {
+		dev_err(dev, "Failed to register AEAD alg.\n");
+		goto err_aead;
+	}
+	return 0;
+
+err_aead:
+	crypto_unregister_aead(&aes_drv_ctx.alg.aead);
+
+err_engine:
+	if (aes_drv_ctx.engine)
+		crypto_engine_exit(aes_drv_ctx.engine);
+
+	return err;
+}
+
+static int zynqmp_aes_aead_remove(struct platform_device *pdev)
+{
+	crypto_engine_exit(aes_drv_ctx.engine);
+	crypto_unregister_aead(&aes_drv_ctx.alg.aead);
+	return 0;
+}
+
+static const struct of_device_id zynqmp_aes_dt_ids[] = {
+	{ .compatible = "xlnx,zynqmp-aes" },
+	{ /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, zynqmp_aes_dt_ids);
+
+static struct platform_driver zynqmp_aes_driver = {
+	.probe	= zynqmp_aes_aead_probe,
+	.remove = zynqmp_aes_aead_remove,
+	.driver = {
+		.name		= DRIVER_NAME,
+		.of_match_table = zynqmp_aes_dt_ids,
+	},
+};
+
+module_platform_driver(zynqmp_aes_driver);
+
+MODULE_LICENSE("GPL");
+
-- 
1.9.5

RE: [PATCH V4 0/4] Add Xilinx's ZynqMP AES-GCM driver support

[Kalyani Akula]

Hi Herbert,

Any review comments on below patch set.

Regards,
Kalyani

> -----Original Message-----
> From: Kalyani Akula <kalyani.akula@xilinx.com>
> Sent: Wednesday, November 20, 2019 1:14 PM
> To: linux-crypto@vger.kernel.org; linux-kernel@vger.kernel.org
> Cc: git <git@xilinx.com>; Harsh Jain <harshj@xilinx.com>; Sarat Chand
> Savitala <saratcha@xilinx.com>; Mohan Marutirao Dhanawade
> <mohand@xilinx.com>; Kalyani Akula <kalyania@xilinx.com>; Kalyani Akula
> <kalyania@xilinx.com>
> Subject: [PATCH V4 0/4] Add Xilinx's ZynqMP AES-GCM driver support
> 
> This patch set adds support for
> - dt-binding docs for Xilinx ZynqMP AES driver
> - Adds device tree node for ZynqMP AES driver
> - Adds communication layer support for aes in zynqmp.c
> - Adds Xilinx ZynqMP driver for AES Algorithm
> 
> V4 Changes :
> - Addressed review comments.
> 
> V3 Changes :
> - Added software fallback in cases where HW doesnt have  the capability to
> handle the request.
> - Removed use of global variable for storing the driver data.
> - Enabled CONFIG_CRYPTO_MANAGER_EXTRA_TESTS=y and executed all
> the kernel selftests. Also covered tests with tcrypt module.
> 
> V2 Changes :
> - Converted RFC PATCH to PATCH
> - Removed ALG_SET_KEY_TYPE that was added to support keytype
>   attribute. Taken using setkey interface.
> - Removed deprecated BLKCIPHER in Kconfig
> - Erased Key/IV from the buffer.
> - Renamed zynqmp-aes driver to zynqmp-aes-gcm.
> - Addressed few other review comments
> 
> 
> Kalyani Akula (4):
>   dt-bindings: crypto: Add bindings for ZynqMP AES driver
>   ARM64: zynqmp: Add Xilinix AES node.
>   firmware: xilinx: Add ZynqMP aes API for AES functionality
>   crypto: Add Xilinx AES driver
> 
>  .../devicetree/bindings/crypto/xlnx,zynqmp-aes.txt |  12 +
>  arch/arm64/boot/dts/xilinx/zynqmp.dtsi             |   5 +
>  drivers/crypto/Kconfig                             |  11 +
>  drivers/crypto/Makefile                            |   1 +
>  drivers/crypto/xilinx/Makefile                     |   3 +
>  drivers/crypto/xilinx/zynqmp-aes-gcm.c             | 469
> +++++++++++++++++++++
>  drivers/firmware/xilinx/zynqmp.c                   |  23 +
>  include/linux/firmware/xlnx-zynqmp.h               |   2 +
>  8 files changed, 526 insertions(+)
>  create mode 100644
> Documentation/devicetree/bindings/crypto/xlnx,zynqmp-aes.txt
>  create mode 100644 drivers/crypto/xilinx/Makefile  create mode 100644
> drivers/crypto/xilinx/zynqmp-aes-gcm.c
> 
> --
> 1.9.5

Re: [PATCH V4 0/4] Add Xilinx's ZynqMP AES-GCM driver support

[Herbert Xu]

On Mon, Jan 20, 2020 at 06:59:22AM +0000, Kalyani Akula wrote:
> Hi Herbert,
> 
> Any review comments on below patch set.

Please resubmit your patch series once you have acks for the
non-crypto bits ready.  Please also state how you want it to
be merged, i.e., whether only the crypto patch is meant  for
the crypto tree or whether it needs to go in as a whole.

Thanks,
-- 
Email: Herbert Xu <herbert@gondor.apana.org.au>
Home Page: http://gondor.apana.org.au/~herbert/
PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt

Re: [PATCH V4 1/4] dt-bindings: crypto: Add bindings for ZynqMP AES driver

[Michal Simek]

On 20. 11. 19 8:43, Kalyani Akula wrote:
> Add documentation to describe Xilinx ZynqMP AES driver bindings.
> 
> Signed-off-by: Kalyani Akula <kalyani.akula@xilinx.com>
> ---
>  Documentation/devicetree/bindings/crypto/xlnx,zynqmp-aes.txt | 12 ++++++++++++
>  1 file changed, 12 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/crypto/xlnx,zynqmp-aes.txt
> 
> diff --git a/Documentation/devicetree/bindings/crypto/xlnx,zynqmp-aes.txt b/Documentation/devicetree/bindings/crypto/xlnx,zynqmp-aes.txt
> new file mode 100644
> index 0000000..226bfb9
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/crypto/xlnx,zynqmp-aes.txt
> @@ -0,0 +1,12 @@
> +Xilinx ZynqMP AES hw acceleration support
> +
> +The ZynqMP PS-AES hw accelerator is used to encrypt/decrypt
> +the given user data.
> +
> +Required properties:
> +- compatible: should contain "xlnx,zynqmp-aes"
> +
> +Example:
> +	zynqmp_aes {
> +		compatible = "xlnx,zynqmp-aes";
> +	};
> 

Ok. This should be converted to yaml and it should be placed to
zynqmp_firmware node as is done for clk, pcap, nvmem, power, reset and
genpd.

Thanks,
Michal

Re: [PATCH V4 2/4] ARM64: zynqmp: Add Xilinix AES node.

[Michal Simek]

On 20. 11. 19 8:44, Kalyani Akula wrote:
> This patch adds a AES DT node for Xilinx ZynqMP SoC.
> 
> Signed-off-by: Kalyani Akula <kalyani.akula@xilinx.com>
> ---
>  arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 5 +++++
>  1 file changed, 5 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
> index 9aa6734..9a0b7f4 100644
> --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
> +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
> @@ -626,4 +626,9 @@
>  			timeout-sec = <10>;
>  		};
>  	};
> +
> +	xlnx_aes: zynqmp_aes {

Should zynqmp-aes based on spec.

> +		compatible = "xlnx,zynqmp-aes";
> +	};
> +
>  };
> 

as 1/4. Incorrect location. And I would send it as the last patch in
this series.

Thanks,
Michal

Re: [PATCH V4 3/4] firmware: xilinx: Add ZynqMP aes API for AES functionality

[Michal Simek]

On 20. 11. 19 8:44, Kalyani Akula wrote:
> Add ZynqMP firmware AES API to perform encryption/decryption of given data.
> 
> Signed-off-by: Kalyani Akula <kalyani.akula@xilinx.com>
> ---
>  drivers/firmware/xilinx/zynqmp.c     | 23 +++++++++++++++++++++++
>  include/linux/firmware/xlnx-zynqmp.h |  2 ++
>  2 files changed, 25 insertions(+)
> 
> diff --git a/drivers/firmware/xilinx/zynqmp.c b/drivers/firmware/xilinx/zynqmp.c
> index fd3d837..7ddf38e 100644
> --- a/drivers/firmware/xilinx/zynqmp.c
> +++ b/drivers/firmware/xilinx/zynqmp.c
> @@ -664,6 +664,28 @@ static int zynqmp_pm_set_requirement(const u32 node, const u32 capabilities,
>  				   qos, ack, NULL);
>  }
>  
> +/**
> + * zynqmp_pm_aes - Access AES hardware to encrypt/decrypt the data using
> + * AES-GCM core.
> + * @address:	Address of the AesParams structure.
> + * @out:	Returned output value
> + *
> + * Return:	Returns status, either success or error code.
> + */
> +static int zynqmp_pm_aes_engine(const u64 address, u32 *out)
> +{
> +	u32 ret_payload[PAYLOAD_ARG_CNT];
> +	int ret;
> +
> +	if (!out)
> +		return -EINVAL;
> +
> +	ret = zynqmp_pm_invoke_fn(PM_SECURE_AES, upper_32_bits(address),
> +				  lower_32_bits(address),
> +				  0, 0, ret_payload);
> +	*out = ret_payload[1];

newline here please.

> +	return ret;
> +}


newline here please.

>  static const struct zynqmp_eemi_ops eemi_ops = {
>  	.get_api_version = zynqmp_pm_get_api_version,
>  	.get_chipid = zynqmp_pm_get_chipid,
> @@ -687,6 +709,7 @@ static int zynqmp_pm_set_requirement(const u32 node, const u32 capabilities,
>  	.set_requirement = zynqmp_pm_set_requirement,
>  	.fpga_load = zynqmp_pm_fpga_load,
>  	.fpga_get_status = zynqmp_pm_fpga_get_status,
> +	.aes = zynqmp_pm_aes_engine,
>  };
>  
>  /**
> diff --git a/include/linux/firmware/xlnx-zynqmp.h b/include/linux/firmware/xlnx-zynqmp.h
> index 778abbb..508edd7 100644
> --- a/include/linux/firmware/xlnx-zynqmp.h
> +++ b/include/linux/firmware/xlnx-zynqmp.h
> @@ -77,6 +77,7 @@ enum pm_api_id {
>  	PM_CLOCK_GETRATE,
>  	PM_CLOCK_SETPARENT,
>  	PM_CLOCK_GETPARENT,
> +	PM_SECURE_AES = 47,
>  };
>  
>  /* PMU-FW return status codes */
> @@ -294,6 +295,7 @@ struct zynqmp_eemi_ops {
>  			       const u32 capabilities,
>  			       const u32 qos,
>  			       const enum zynqmp_pm_request_ack ack);
> +	int (*aes)(const u64 address, u32 *out);
>  };
>  
>  int zynqmp_pm_invoke_fn(u32 pm_api_id, u32 arg0, u32 arg1,
> 

Thanks,
Michal

Re: [PATCH V4 4/4] crypto: Add Xilinx AES driver

[Michal Simek]

On 20. 11. 19 8:44, Kalyani Akula wrote:
> This patch adds AES driver support for the Xilinx ZynqMP SoC.
> 
> Signed-off-by: Kalyani Akula <kalyani.akula@xilinx.com>
> ---
>  drivers/crypto/Kconfig                 |  11 +
>  drivers/crypto/Makefile                |   1 +
>  drivers/crypto/xilinx/Makefile         |   3 +
>  drivers/crypto/xilinx/zynqmp-aes-gcm.c | 469 +++++++++++++++++++++++++++++++++
>  4 files changed, 484 insertions(+)
>  create mode 100644 drivers/crypto/xilinx/Makefile
>  create mode 100644 drivers/crypto/xilinx/zynqmp-aes-gcm.c
> 
> diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig
> index 1fb622f..8e7d3a9 100644
> --- a/drivers/crypto/Kconfig
> +++ b/drivers/crypto/Kconfig
> @@ -696,6 +696,17 @@ config CRYPTO_DEV_ROCKCHIP
>  	help
>  	  This driver interfaces with the hardware crypto accelerator.
>  	  Supporting cbc/ecb chainmode, and aes/des/des3_ede cipher mode.

Here should be newline.

> +config CRYPTO_DEV_ZYNQMP_AES
> +	tristate "Support for Xilinx ZynqMP AES hw accelerator"
> +	depends on ARCH_ZYNQMP || COMPILE_TEST

depends on ZYNQMP_FIRMWARE || COMPILE_TEST
is better here because you can use it only on Versal.


> +	select CRYPTO_AES
> +	select CRYPTO_ENGINE
> +	select CRYPTO_AEAD
> +	help
> +	  Xilinx ZynqMP has AES-GCM engine used for symmetric key
> +	  encryption and decryption. This driver interfaces with AES hw
> +	  accelerator. Select this if you want to use the ZynqMP module
> +	  for AES algorithms.
>  
>  config CRYPTO_DEV_MEDIATEK
>  	tristate "MediaTek's EIP97 Cryptographic Engine driver"
> diff --git a/drivers/crypto/Makefile b/drivers/crypto/Makefile
> index afc4753..50184377 100644
> --- a/drivers/crypto/Makefile
> +++ b/drivers/crypto/Makefile
> @@ -47,4 +47,5 @@ obj-$(CONFIG_CRYPTO_DEV_VMX) += vmx/
>  obj-$(CONFIG_CRYPTO_DEV_BCM_SPU) += bcm/
>  obj-$(CONFIG_CRYPTO_DEV_SAFEXCEL) += inside-secure/
>  obj-$(CONFIG_CRYPTO_DEV_ARTPEC6) += axis/
> +obj-$(CONFIG_CRYPTO_DEV_ZYNQMP_AES) += xilinx/
>  obj-y += hisilicon/
> diff --git a/drivers/crypto/xilinx/Makefile b/drivers/crypto/xilinx/Makefile
> new file mode 100644
> index 0000000..16bdda7
> --- /dev/null
> +++ b/drivers/crypto/xilinx/Makefile
> @@ -0,0 +1,3 @@
> +# SPDX-License-Identifier: GPL-2.0-only
> +obj-$(CONFIG_CRYPTO_DEV_ZYNQMP_AES) += zynqmp-aes-gcm.o
> +

This looks like additional newline.

> diff --git a/drivers/crypto/xilinx/zynqmp-aes-gcm.c b/drivers/crypto/xilinx/zynqmp-aes-gcm.c
> new file mode 100644
> index 0000000..534105b
> --- /dev/null
> +++ b/drivers/crypto/xilinx/zynqmp-aes-gcm.c
> @@ -0,0 +1,469 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Xilinx ZynqMP AES Driver.
> + * Copyright (c) 2019 Xilinx Inc.
> + */
> +
> +#include <crypto/aes.h>
> +#include <crypto/engine.h>
> +#include <crypto/gcm.h>
> +#include <crypto/internal/aead.h>
> +#include <crypto/scatterwalk.h>
> +
> +#include <linux/module.h>
> +#include <linux/of_device.h>
> +#include <linux/platform_device.h>
> +
> +#include <linux/firmware/xlnx-zynqmp.h>
> +
> +#define DRIVER_NAME		"zynqmp-aes"

nite: Use only once - that's why you can just use directly.

> +#define ZYNQMP_DMA_BIT_MASK	32U
> +
> +#define ZYNQMP_AES_KEY_SIZE		AES_KEYSIZE_256
> +#define ZYNQMP_AES_AUTH_SIZE		16U
> +#define ZYNQMP_KEY_SRC_SEL_KEY_LEN	1U
> +#define ZYNQMP_AES_BLK_SIZE		1U
> +#define ZYNQMP_AES_MIN_INPUT_BLK_SIZE	4U
> +#define ZYNQMP_AES_WORD_LEN		4U
> +
> +#define ZYNQMP_AES_GCM_TAG_MISMATCH_ERR		0x01
> +#define ZYNQMP_AES_WRONG_KEY_SRC_ERR		0x13
> +#define ZYNQMP_AES_PUF_NOT_PROGRAMMED		0xE300
> +
> +enum zynqmp_aead_op {
> +	ZYNQMP_AES_DECRYPT = 0,
> +	ZYNQMP_AES_ENCRYPT
> +};
> +
> +enum zynqmp_aead_keysrc {
> +	ZYNQMP_AES_KUP_KEY = 0,
> +	ZYNQMP_AES_DEV_KEY,
> +	ZYNQMP_AES_PUF_KEY
> +};
> +
> +struct zynqmp_aead_drv_ctx {
> +	union {
> +		struct aead_alg aead;
> +	} alg;
> +	struct device *dev;
> +	struct crypto_engine *engine;
> +	const struct zynqmp_eemi_ops *eemi_ops;
> +};
> +
> +struct zynqmp_aead_hw_req {
> +	u64 src;
> +	u64 iv;
> +	u64 key;
> +	u64 dst;
> +	u64 size;
> +	u64 op;
> +	u64 keysrc;
> +};
> +
> +struct zynqmp_aead_tfm_ctx {
> +	struct crypto_engine_ctx engine_ctx;
> +	struct device *dev;
> +	u8 key[ZYNQMP_AES_KEY_SIZE];
> +	u8 *iv;
> +	u32 keylen;
> +	u32 authsize;
> +	enum zynqmp_aead_keysrc keysrc;
> +	struct crypto_aead *fbk_cipher;
> +};
> +
> +struct zynqmp_aead_req_ctx {
> +	enum zynqmp_aead_op op;
> +};
> +
> +static int zynqmp_aes_aead_cipher(struct aead_request *req)
> +{
> +	struct crypto_aead *aead = crypto_aead_reqtfm(req);
> +	struct zynqmp_aead_tfm_ctx *tfm_ctx = crypto_aead_ctx(aead);
> +	struct zynqmp_aead_req_ctx *rq_ctx = aead_request_ctx(req);
> +	struct device *dev = tfm_ctx->dev;
> +	struct aead_alg *alg = crypto_aead_alg(aead);
> +	struct zynqmp_aead_drv_ctx *drv_ctx;
> +	struct zynqmp_aead_hw_req *hwreq;
> +	dma_addr_t dma_addr_data, dma_addr_hw_req;
> +	unsigned int data_size;
> +	unsigned int status;
> +	size_t dma_size;
> +	char *kbuf;
> +	int err;
> +
> +	drv_ctx = container_of(alg, struct zynqmp_aead_drv_ctx, alg.aead);
> +
> +	if (!drv_ctx->eemi_ops->aes)
> +		return -ENOTSUPP;
> +
> +	if (tfm_ctx->keysrc == ZYNQMP_AES_KUP_KEY)
> +		dma_size = req->cryptlen + ZYNQMP_AES_KEY_SIZE
> +			   + GCM_AES_IV_SIZE;
> +	else
> +		dma_size = req->cryptlen + GCM_AES_IV_SIZE;
> +
> +	kbuf = dma_alloc_coherent(dev, dma_size, &dma_addr_data, GFP_KERNEL);
> +	if (!kbuf)
> +		return -ENOMEM;
> +
> +	hwreq = dma_alloc_coherent(dev, sizeof(struct zynqmp_aead_hw_req),
> +				   &dma_addr_hw_req, GFP_KERNEL);
> +	if (!hwreq) {
> +		dma_free_coherent(dev, dma_size, kbuf, dma_addr_data);
> +		return -ENOMEM;
> +	}
> +
> +	data_size = req->cryptlen;
> +	scatterwalk_map_and_copy(kbuf, req->src, 0, req->cryptlen, 0);
> +	memcpy(kbuf + data_size, req->iv, GCM_AES_IV_SIZE);
> +
> +	hwreq->src = dma_addr_data;
> +	hwreq->dst = dma_addr_data;
> +	hwreq->iv = hwreq->src + data_size;
> +	hwreq->keysrc = tfm_ctx->keysrc;
> +	hwreq->op = rq_ctx->op;
> +
> +	if (hwreq->op == ZYNQMP_AES_ENCRYPT)
> +		hwreq->size = data_size;
> +	else
> +		hwreq->size = data_size - ZYNQMP_AES_AUTH_SIZE;
> +
> +	if (hwreq->keysrc == ZYNQMP_AES_KUP_KEY) {
> +		memcpy(kbuf + data_size + GCM_AES_IV_SIZE,
> +		       tfm_ctx->key, ZYNQMP_AES_KEY_SIZE);
> +
> +		hwreq->key = hwreq->src + data_size + GCM_AES_IV_SIZE;
> +	} else {
> +		hwreq->key = 0;
> +	}
> +
> +	drv_ctx->eemi_ops->aes(dma_addr_hw_req, &status);
> +
> +	if (status) {
> +		switch (status) {
> +		case ZYNQMP_AES_GCM_TAG_MISMATCH_ERR:
> +			dev_err(dev, "ERROR: Gcm Tag mismatch\n");
> +			break;
> +		case ZYNQMP_AES_WRONG_KEY_SRC_ERR:
> +			dev_err(dev, "ERROR: Wrong KeySrc, enable secure mode\n");
> +			break;
> +		case ZYNQMP_AES_PUF_NOT_PROGRAMMED:
> +			dev_err(dev, "ERROR: PUF is not registered\n");
> +			break;
> +		default:
> +			dev_err(dev, "ERROR: Unknown error\n");
> +			break;
> +		}
> +		err = -status;
> +	} else {
> +		if (hwreq->op == ZYNQMP_AES_ENCRYPT)
> +			data_size = data_size + ZYNQMP_AES_AUTH_SIZE;
> +		else
> +			data_size = data_size - ZYNQMP_AES_AUTH_SIZE;
> +
> +		sg_copy_from_buffer(req->dst, sg_nents(req->dst),
> +				    kbuf, data_size);
> +		err = 0;
> +	}
> +
> +	if (kbuf) {
> +		memzero_explicit(kbuf, dma_size);
> +		dma_free_coherent(dev, dma_size, kbuf, dma_addr_data);
> +	}
> +	if (hwreq) {
> +		memzero_explicit(hwreq, sizeof(struct zynqmp_aead_hw_req));
> +		dma_free_coherent(dev, sizeof(struct zynqmp_aead_hw_req),
> +				  hwreq, dma_addr_hw_req);
> +	}
> +	return err;
> +}
> +
> +static int zynqmp_fallback_check(struct zynqmp_aead_tfm_ctx *tfm_ctx,
> +				 struct aead_request *req)
> +{
> +	int need_fallback = 0;
> +	struct zynqmp_aead_req_ctx *rq_ctx = aead_request_ctx(req);
> +
> +	if (tfm_ctx->authsize != ZYNQMP_AES_AUTH_SIZE)
> +		need_fallback = 1;
> +
> +	if (tfm_ctx->keysrc == ZYNQMP_AES_KUP_KEY &&
> +	    tfm_ctx->keylen != ZYNQMP_AES_KEY_SIZE) {
> +		need_fallback = 1;
> +	}
> +	if (req->assoclen != 0 ||
> +	    req->cryptlen < ZYNQMP_AES_MIN_INPUT_BLK_SIZE) {
> +		need_fallback = 1;
> +	}
> +	if ((req->cryptlen % ZYNQMP_AES_WORD_LEN) != 0)
> +		need_fallback = 1;
> +
> +	if (rq_ctx->op == ZYNQMP_AES_DECRYPT &&
> +	    req->cryptlen <= ZYNQMP_AES_AUTH_SIZE) {
> +		need_fallback = 1;
> +	}
> +	return need_fallback;
> +}
> +
> +static int zynqmp_handle_aes_req(struct crypto_engine *engine,
> +				 void *req)
> +{
> +	struct aead_request *areq =
> +				container_of(req, struct aead_request, base);
> +	struct crypto_aead *aead = crypto_aead_reqtfm(req);
> +	struct zynqmp_aead_tfm_ctx *tfm_ctx = crypto_aead_ctx(aead);
> +	struct zynqmp_aead_req_ctx *rq_ctx = aead_request_ctx(areq);
> +	struct aead_request *subreq = aead_request_ctx(req);
> +	int need_fallback;
> +	int err;
> +
> +	need_fallback = zynqmp_fallback_check(tfm_ctx, areq);
> +
> +	if (need_fallback) {
> +		aead_request_set_tfm(subreq, tfm_ctx->fbk_cipher);
> +
> +		aead_request_set_callback(subreq, areq->base.flags,
> +					  NULL, NULL);
> +		aead_request_set_crypt(subreq, areq->src, areq->dst,
> +				       areq->cryptlen, areq->iv);
> +		aead_request_set_ad(subreq, areq->assoclen);
> +		if (rq_ctx->op == ZYNQMP_AES_ENCRYPT)
> +			err = crypto_aead_encrypt(subreq);
> +		else
> +			err = crypto_aead_decrypt(subreq);
> +	} else {
> +		err = zynqmp_aes_aead_cipher(areq);
> +	}
> +
> +	crypto_finalize_aead_request(engine, areq, err);
> +	return 0;
> +}
> +
> +static int zynqmp_aes_aead_setkey(struct crypto_aead *aead, const u8 *key,
> +				  unsigned int keylen)
> +{
> +	struct crypto_tfm *tfm = crypto_aead_tfm(aead);
> +	struct zynqmp_aead_tfm_ctx *tfm_ctx =
> +			(struct zynqmp_aead_tfm_ctx *)crypto_tfm_ctx(tfm);
> +	unsigned char keysrc;
> +	int err;
> +
> +	if (keylen == ZYNQMP_KEY_SRC_SEL_KEY_LEN) {
> +		keysrc = *key;
> +		if (keysrc == ZYNQMP_AES_KUP_KEY ||
> +		    keysrc == ZYNQMP_AES_DEV_KEY ||
> +		    keysrc == ZYNQMP_AES_PUF_KEY) {
> +			tfm_ctx->keysrc = (enum zynqmp_aead_keysrc)keysrc;
> +		} else {
> +			tfm_ctx->keylen = keylen;
> +		}
> +	} else {
> +		tfm_ctx->keylen = keylen;
> +		if (keylen == ZYNQMP_AES_KEY_SIZE) {
> +			tfm_ctx->keysrc = ZYNQMP_AES_KUP_KEY;
> +			memcpy(tfm_ctx->key, key, keylen);
> +		}
> +	}
> +
> +	tfm_ctx->fbk_cipher->base.crt_flags &= ~CRYPTO_TFM_REQ_MASK;
> +	tfm_ctx->fbk_cipher->base.crt_flags |= (aead->base.crt_flags &
> +					CRYPTO_TFM_REQ_MASK);
> +
> +	err = crypto_aead_setkey(tfm_ctx->fbk_cipher, key, keylen);
> +	if (err) {
> +		aead->base.crt_flags &= ~CRYPTO_TFM_RES_MASK;
> +		aead->base.crt_flags |=
> +				(tfm_ctx->fbk_cipher->base.crt_flags &
> +				 CRYPTO_TFM_RES_MASK);
> +	}
> +
> +	return err;
> +}
> +
> +static int zynqmp_aes_aead_setauthsize(struct crypto_aead *aead,
> +				       unsigned int authsize)
> +{
> +	struct crypto_tfm *tfm = crypto_aead_tfm(aead);
> +	struct zynqmp_aead_tfm_ctx *tfm_ctx =
> +			(struct zynqmp_aead_tfm_ctx *)crypto_tfm_ctx(tfm);
> +
> +	tfm_ctx->authsize = authsize;
> +	return crypto_aead_setauthsize(tfm_ctx->fbk_cipher, authsize);
> +}
> +
> +static int zynqmp_aes_aead_encrypt(struct aead_request *req)
> +{
> +	struct zynqmp_aead_drv_ctx *drv_ctx;
> +	struct crypto_aead *aead = crypto_aead_reqtfm(req);
> +	struct aead_alg *alg = crypto_aead_alg(aead);
> +	struct zynqmp_aead_req_ctx *rq_ctx = aead_request_ctx(req);
> +
> +	rq_ctx->op = ZYNQMP_AES_ENCRYPT;
> +	drv_ctx = container_of(alg, struct zynqmp_aead_drv_ctx, alg.aead);
> +
> +	return crypto_transfer_aead_request_to_engine(drv_ctx->engine, req);
> +}
> +
> +static int zynqmp_aes_aead_decrypt(struct aead_request *req)
> +{
> +	struct zynqmp_aead_drv_ctx *drv_ctx;
> +	struct crypto_aead *aead = crypto_aead_reqtfm(req);
> +	struct aead_alg *alg = crypto_aead_alg(aead);
> +	struct zynqmp_aead_req_ctx *rq_ctx = aead_request_ctx(req);
> +
> +	rq_ctx->op = ZYNQMP_AES_DECRYPT;
> +	drv_ctx = container_of(alg, struct zynqmp_aead_drv_ctx, alg.aead);
> +
> +	return crypto_transfer_aead_request_to_engine(drv_ctx->engine, req);
> +}
> +
> +static int zynqmp_aes_aead_init(struct crypto_aead *aead)
> +{
> +	struct crypto_tfm *tfm = crypto_aead_tfm(aead);
> +	struct zynqmp_aead_tfm_ctx *tfm_ctx =
> +		(struct zynqmp_aead_tfm_ctx *)crypto_tfm_ctx(tfm);
> +	struct zynqmp_aead_drv_ctx *drv_ctx;
> +	struct aead_alg *alg = crypto_aead_alg(aead);
> +
> +	drv_ctx = container_of(alg, struct zynqmp_aead_drv_ctx, alg.aead);
> +	tfm_ctx->dev = drv_ctx->dev;
> +
> +	tfm_ctx->engine_ctx.op.do_one_request = zynqmp_handle_aes_req;
> +	tfm_ctx->engine_ctx.op.prepare_request = NULL;
> +	tfm_ctx->engine_ctx.op.unprepare_request = NULL;
> +
> +	tfm_ctx->fbk_cipher = crypto_alloc_aead(drv_ctx->alg.aead.base.cra_name,
> +						0,
> +						CRYPTO_ALG_NEED_FALLBACK);
> +
> +	if (IS_ERR(tfm_ctx->fbk_cipher)) {
> +		pr_err("%s() Error: failed to allocate fallback for %s\n",
> +		       __func__, drv_ctx->alg.aead.base.cra_name);
> +		return PTR_ERR(tfm_ctx->fbk_cipher);
> +	}
> +
> +	crypto_aead_set_reqsize(aead,
> +				max(sizeof(struct zynqmp_aead_req_ctx),
> +				    sizeof(struct aead_request) +
> +				    crypto_aead_reqsize(tfm_ctx->fbk_cipher)));
> +	return 0;
> +}
> +
> +static void zynqmp_aes_aead_exit(struct crypto_aead *aead)
> +{
> +	struct crypto_tfm *tfm = crypto_aead_tfm(aead);
> +	struct zynqmp_aead_tfm_ctx *tfm_ctx =
> +			(struct zynqmp_aead_tfm_ctx *)crypto_tfm_ctx(tfm);
> +
> +	if (tfm_ctx->fbk_cipher) {
> +		crypto_free_aead(tfm_ctx->fbk_cipher);
> +		tfm_ctx->fbk_cipher = NULL;
> +	}
> +	memzero_explicit(tfm_ctx, sizeof(struct zynqmp_aead_tfm_ctx));
> +}
> +
> +static struct zynqmp_aead_drv_ctx aes_drv_ctx = {
> +	.alg.aead = {
> +		.setkey		= zynqmp_aes_aead_setkey,
> +		.setauthsize	= zynqmp_aes_aead_setauthsize,
> +		.encrypt	= zynqmp_aes_aead_encrypt,
> +		.decrypt	= zynqmp_aes_aead_decrypt,
> +		.init		= zynqmp_aes_aead_init,
> +		.exit		= zynqmp_aes_aead_exit,
> +		.ivsize		= GCM_AES_IV_SIZE,
> +		.maxauthsize	= ZYNQMP_AES_AUTH_SIZE,
> +		.base = {
> +		.cra_name		= "gcm(aes)",
> +		.cra_driver_name	= "xilinx-zynqmp-aes-gcm",
> +		.cra_priority		= 200,
> +		.cra_flags		= CRYPTO_ALG_TYPE_AEAD |
> +					  CRYPTO_ALG_ASYNC |
> +					  CRYPTO_ALG_KERN_DRIVER_ONLY |
> +					  CRYPTO_ALG_NEED_FALLBACK,
> +		.cra_blocksize		= ZYNQMP_AES_BLK_SIZE,
> +		.cra_ctxsize		= sizeof(struct zynqmp_aead_tfm_ctx),
> +		.cra_module		= THIS_MODULE,
> +		}
> +	}
> +};
> +
> +static int zynqmp_aes_aead_probe(struct platform_device *pdev)
> +{
> +	struct device *dev = &pdev->dev;
> +	int err = -1;
> +
> +	if (!pdev->dev.of_node)
> +		return -ENODEV;

I would remove this.

> +
> +	/* ZynqMp AES driver supports only one instance */

ZynqMP

> +	if (!aes_drv_ctx.dev)
> +		aes_drv_ctx.dev = dev;
> +
> +	aes_drv_ctx.eemi_ops = zynqmp_pm_get_eemi_ops();
> +	if (IS_ERR(aes_drv_ctx.eemi_ops)) {
> +		dev_err(dev, "Failed to get ZynqMP EEMI interface\n");
> +		return PTR_ERR(aes_drv_ctx.eemi_ops);
> +	}
> +
> +	err = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(ZYNQMP_DMA_BIT_MASK));
> +	if (err < 0) {
> +		dev_err(dev, "No usable DMA configuration\n");
> +		return err;
> +	}
> +
> +	aes_drv_ctx.engine = crypto_engine_alloc_init(dev, 1);
> +	if (!aes_drv_ctx.engine) {
> +		dev_err(dev, "Cannot alloc AES engine\n");
> +		err = -ENOMEM;
> +		goto err_engine;
> +	}
> +
> +	err = crypto_engine_start(aes_drv_ctx.engine);
> +	if (err) {
> +		dev_err(dev, "Cannot start AES engine\n");
> +		goto err_engine;
> +	}
> +
> +	err = crypto_register_aead(&aes_drv_ctx.alg.aead);
> +	if (err < 0) {
> +		dev_err(dev, "Failed to register AEAD alg.\n");
> +		goto err_aead;
> +	}
> +	return 0;
> +
> +err_aead:
> +	crypto_unregister_aead(&aes_drv_ctx.alg.aead);
> +
> +err_engine:
> +	if (aes_drv_ctx.engine)
> +		crypto_engine_exit(aes_drv_ctx.engine);
> +
> +	return err;
> +}
> +
> +static int zynqmp_aes_aead_remove(struct platform_device *pdev)
> +{
> +	crypto_engine_exit(aes_drv_ctx.engine);
> +	crypto_unregister_aead(&aes_drv_ctx.alg.aead);

newline here.

> +	return 0;
> +}
> +
> +static const struct of_device_id zynqmp_aes_dt_ids[] = {
> +	{ .compatible = "xlnx,zynqmp-aes" },
> +	{ /* sentinel */ }
> +};
> +MODULE_DEVICE_TABLE(of, zynqmp_aes_dt_ids);
> +
> +static struct platform_driver zynqmp_aes_driver = {
> +	.probe	= zynqmp_aes_aead_probe,
> +	.remove = zynqmp_aes_aead_remove,
> +	.driver = {
> +		.name		= DRIVER_NAME,
> +		.of_match_table = zynqmp_aes_dt_ids,
> +	},
> +};
> +
> +module_platform_driver(zynqmp_aes_driver);
> +
> +MODULE_LICENSE("GPL");
> +

Remove this newline at the end.


Thanks,
Michal

Re: [PATCH V4 0/4] Add Xilinx's ZynqMP AES-GCM driver support

[Michal Simek]

Hi Herbert,

On 20. 01. 20 8:55, Herbert Xu wrote:
> On Mon, Jan 20, 2020 at 06:59:22AM +0000, Kalyani Akula wrote:
>> Hi Herbert,
>>
>> Any review comments on below patch set.
> 
> Please resubmit your patch series once you have acks for the
> non-crypto bits ready.  Please also state how you want it to
> be merged, i.e., whether only the crypto patch is meant  for
> the crypto tree or whether it needs to go in as a whole.

All these drivers which requires firmware interface extension can be
added via your tree or I can take them via arm-soc tree with your ack.

It is really up to you. I am happy to just ack patches out of crypto and
feel free to take them via your tree.
Or please let me know when you are done with review and I will take them.

Kalyani: Please fix that stuff I have reported and we are waiting for v5.

Thanks,
Michal

Re: [PATCH V4 0/4] Add Xilinx's ZynqMP AES-GCM driver support

[Herbert Xu]

On Tue, Jan 21, 2020 at 10:26:07AM +0100, Michal Simek wrote:
>
> All these drivers which requires firmware interface extension can be
> added via your tree or I can take them via arm-soc tree with your ack.
> 
> It is really up to you. I am happy to just ack patches out of crypto and
> feel free to take them via your tree.
> Or please let me know when you are done with review and I will take them.

Thanks Michal. If you could ack them once they've been resubmitted
then I can just take them via the cryptodev tree.

Thanks,
-- 
Email: Herbert Xu <herbert@gondor.apana.org.au>
Home Page: http://gondor.apana.org.au/~herbert/
PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt

Re: [PATCH V4 0/4] Add Xilinx's ZynqMP AES-GCM driver support

[Michal Simek]

On 22. 01. 20 6:51, Herbert Xu wrote:
> On Tue, Jan 21, 2020 at 10:26:07AM +0100, Michal Simek wrote:
>>
>> All these drivers which requires firmware interface extension can be
>> added via your tree or I can take them via arm-soc tree with your ack.
>>
>> It is really up to you. I am happy to just ack patches out of crypto and
>> feel free to take them via your tree.
>> Or please let me know when you are done with review and I will take them.
> 
> Thanks Michal. If you could ack them once they've been resubmitted
> then I can just take them via the cryptodev tree.

Great.
Michal