From: Atish Patra <atish.patra@wdc.com>
To: Christoph Hellwig <hch@lst.de>
Cc: "tglx@linutronix.de" <tglx@linutronix.de>,
"palmer@sifive.com" <palmer@sifive.com>,
"jason@lakedaemon.net" <jason@lakedaemon.net>,
"marc.zyngier@arm.com" <marc.zyngier@arm.com>,
"robh+dt@kernel.org" <robh+dt@kernel.org>,
"mark.rutland@arm.com" <mark.rutland@arm.com>,
"anup@brainfault.org" <anup@brainfault.org>,
"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
"aou@eecs.berkeley.edu" <aou@eecs.berkeley.edu>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"linux-riscv@lists.infradead.org"
<linux-riscv@lists.infradead.org>,
"shorne@gmail.com" <shorne@gmail.com>
Subject: Re: [PATCH 7/9] irqchip: add a RISC-V PLIC driver
Date: Wed, 1 Aug 2018 18:09:42 -0700 [thread overview]
Message-ID: <1b380e3c-e137-ebe9-4528-852062d2192e@wdc.com> (raw)
In-Reply-To: <20180801121656.GA25806@lst.de>
On 8/1/18 5:12 AM, Christoph Hellwig wrote:
> On Tue, Jul 31, 2018 at 05:38:01PM -0700, Atish Patra wrote:
>> crash details are at
>> https://paste.debian.net/1036078/
>
> Is this running without kallsyms? It seems to lack useful symbols
> and a backtrace unfortunately.
>
Yes. I checked the config. All KALLSYMS options and STACKTRACE are enabled
CONFIG_KALLSYMS=y
CONFIG_KALLSYMS_ALL=y
CONFIG_KALLSYMS_BASE_RELATIVE=y
CONFIG_STACKTRACE_SUPPORT=y
CONFIG_STACKTRACE=y
Not sure if I missed something.
Regards,
Atish
next prev parent reply other threads:[~2018-08-02 1:09 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-07-26 14:37 RFC: simplified RISC-V interrupt and clocksource handling Christoph Hellwig
2018-07-26 14:37 ` [PATCH 1/9] RISC-V: remove timer leftovers Christoph Hellwig
2018-07-26 14:37 ` [PATCH 2/9] RISC-V: simplify software interrupt / IPI code Christoph Hellwig
2018-07-26 14:37 ` [PATCH 3/9] RISC-V: remove INTERRUPT_CAUSE_* defines from asm/irq.h Christoph Hellwig
2018-07-26 14:37 ` [PATCH 4/9] RISC-V: add a definition for the SIE SEIE bit Christoph Hellwig
2018-07-26 14:37 ` [PATCH 5/9] RISC-V: implement low-level interrupt handling Christoph Hellwig
2018-08-02 9:48 ` Thomas Gleixner
2018-08-02 9:59 ` Christoph Hellwig
2018-07-26 14:37 ` [PATCH 6/9] RISC-V: Support per-hart timebase-frequency Christoph Hellwig
2018-07-26 14:37 ` [PATCH 7/9] irqchip: add a RISC-V PLIC driver Christoph Hellwig
2018-07-28 0:04 ` Atish Patra
2018-07-30 15:51 ` Anup Patel
2018-07-31 3:21 ` Atish Patra
2018-07-31 16:57 ` Christoph Hellwig
2018-08-01 0:38 ` Atish Patra
2018-08-01 7:14 ` Christoph Hellwig
2018-08-01 12:16 ` Christoph Hellwig
2018-08-02 1:09 ` Atish Patra [this message]
2018-08-02 9:53 ` Christoph Hellwig
2018-08-01 14:18 ` Christoph Hellwig
2018-08-02 1:02 ` Atish Patra
2018-08-02 9:50 ` Christoph Hellwig
2018-07-31 16:37 ` Christoph Hellwig
2018-08-02 10:04 ` Thomas Gleixner
2018-08-02 11:51 ` Christoph Hellwig
2018-07-26 14:37 ` [PATCH 8/9] dt-bindings: interrupt-controller: RISC-V PLIC documentation Christoph Hellwig
2018-08-02 7:24 ` Nikolay Borisov
2018-08-02 9:52 ` Christoph Hellwig
2018-07-26 14:37 ` [PATCH 9/9] clocksource: new RISC-V SBI timer driver Christoph Hellwig
2018-07-26 18:51 ` Atish Patra
2018-07-27 14:41 ` Christoph Hellwig
2018-07-27 17:44 ` Atish Patra
2018-07-28 21:12 ` kbuild test robot
2018-07-28 21:16 ` kbuild test robot
2018-07-26 23:38 ` RFC: simplified RISC-V interrupt and clocksource handling Atish Patra
2018-07-27 14:44 ` Christoph Hellwig
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