From: Thomas Gleixner <tglx@linutronix.de>
To: Christoph Hellwig <hch@lst.de>
Cc: palmer@sifive.com, jason@lakedaemon.net, marc.zyngier@arm.com,
robh+dt@kernel.org, mark.rutland@arm.com, anup@brainfault.org,
atish.patra@wdc.com, devicetree@vger.kernel.org,
aou@eecs.berkeley.edu, linux-kernel@vger.kernel.org,
linux-riscv@lists.infradead.org, shorne@gmail.com
Subject: Re: [PATCH 7/9] irqchip: add a RISC-V PLIC driver
Date: Thu, 2 Aug 2018 12:04:04 +0200 (CEST) [thread overview]
Message-ID: <alpine.DEB.2.21.1808021149470.2037@nanos.tec.linutronix.de> (raw)
In-Reply-To: <20180726143723.16585-8-hch@lst.de>
On Thu, 26 Jul 2018, Christoph Hellwig wrote:
> This patch adds a driver for the Platform Level Interrupt Controller (PLIC)
See Documentation/process/submitting-patches.rst and search for 'This patch'
> +static inline void __iomem *plic_hart_offset(int ctxid)
> +{
> + return plic_regs + CONTEXT_BASE + ctxid * CONTEXT_PER_HART;
> +}
> +
> +/*
> + * Protect mask operations on the registers given that we can't assume that
> + * atomic memory operations work on them.
> + */
> +static DEFINE_SPINLOCK(plic_toggle_lock);
RAW_SPINLOCK please.
> +
> +static inline void plic_toggle(int ctxid, int hwirq, int enable)
> +{
> + u32 __iomem *reg = plic_regs + ENABLE_BASE + ctxid * ENABLE_PER_HART;
> + u32 hwirq_mask = 1 << (hwirq % 32);
> +
> + spin_lock(&plic_toggle_lock);
> + if (enable)
> + writel(readl(reg) | hwirq_mask, reg);
> + else
> + writel(readl(reg) & ~hwirq_mask, reg);
> + spin_unlock(&plic_toggle_lock);
> +}
> +
> +static inline void plic_irq_toggle(struct irq_data *d, int enable)
> +{
> + int cpu;
> +
> + writel(enable, plic_regs + PRIORITY_BASE + d->hwirq * PRIORITY_PER_ID);
> + for_each_present_cpu(cpu)
> + plic_toggle(cpu, d->hwirq, enable);
I suggest to make that:
for_each_cpu(cpu, irq_data_get_affinity_mask(d))
plic_toggle(cpu, d->hwirq, enable);
That gives you immediately support for interrupt affinity. And then it's
trivial to do the actual irq_chip::irq_set_affinity() magic as well.
> +/*
> + * Handling an interrupt is a two-step process: first you claim the interrupt
> + * by reading the claim register, then you complete the interrupt by writing
> + * that source ID back to the same claim register. This automatically enables
> + * and disables the interrupt, so there's nothing else to do.
> + */
> +static void plic_handle_irq(struct pt_regs *regs)
> +{
> + void __iomem *claim =
> + plic_hart_offset(smp_processor_id()) + CONTEXT_CLAIM;
Either ignore the 80 char thing or just move the assignment into the code
section please. That line break is horrible to read.
> + irq_hw_number_t hwirq;
> +
Other than that this looks halfways sane.
Thanks,
tglx
next prev parent reply other threads:[~2018-08-02 10:04 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-07-26 14:37 RFC: simplified RISC-V interrupt and clocksource handling Christoph Hellwig
2018-07-26 14:37 ` [PATCH 1/9] RISC-V: remove timer leftovers Christoph Hellwig
2018-07-26 14:37 ` [PATCH 2/9] RISC-V: simplify software interrupt / IPI code Christoph Hellwig
2018-07-26 14:37 ` [PATCH 3/9] RISC-V: remove INTERRUPT_CAUSE_* defines from asm/irq.h Christoph Hellwig
2018-07-26 14:37 ` [PATCH 4/9] RISC-V: add a definition for the SIE SEIE bit Christoph Hellwig
2018-07-26 14:37 ` [PATCH 5/9] RISC-V: implement low-level interrupt handling Christoph Hellwig
2018-08-02 9:48 ` Thomas Gleixner
2018-08-02 9:59 ` Christoph Hellwig
2018-07-26 14:37 ` [PATCH 6/9] RISC-V: Support per-hart timebase-frequency Christoph Hellwig
2018-07-26 14:37 ` [PATCH 7/9] irqchip: add a RISC-V PLIC driver Christoph Hellwig
2018-07-28 0:04 ` Atish Patra
2018-07-30 15:51 ` Anup Patel
2018-07-31 3:21 ` Atish Patra
2018-07-31 16:57 ` Christoph Hellwig
2018-08-01 0:38 ` Atish Patra
2018-08-01 7:14 ` Christoph Hellwig
2018-08-01 12:16 ` Christoph Hellwig
2018-08-02 1:09 ` Atish Patra
2018-08-02 9:53 ` Christoph Hellwig
2018-08-01 14:18 ` Christoph Hellwig
2018-08-02 1:02 ` Atish Patra
2018-08-02 9:50 ` Christoph Hellwig
2018-07-31 16:37 ` Christoph Hellwig
2018-08-02 10:04 ` Thomas Gleixner [this message]
2018-08-02 11:51 ` Christoph Hellwig
2018-07-26 14:37 ` [PATCH 8/9] dt-bindings: interrupt-controller: RISC-V PLIC documentation Christoph Hellwig
2018-08-02 7:24 ` Nikolay Borisov
2018-08-02 9:52 ` Christoph Hellwig
2018-07-26 14:37 ` [PATCH 9/9] clocksource: new RISC-V SBI timer driver Christoph Hellwig
2018-07-26 18:51 ` Atish Patra
2018-07-27 14:41 ` Christoph Hellwig
2018-07-27 17:44 ` Atish Patra
2018-07-28 21:12 ` kbuild test robot
2018-07-28 21:16 ` kbuild test robot
2018-07-26 23:38 ` RFC: simplified RISC-V interrupt and clocksource handling Atish Patra
2018-07-27 14:44 ` Christoph Hellwig
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