[PATCH v3 0/4] Add Basic SoC support for MT7622

[PATCH v3 0/4] Add Basic SoC support for MT7622

[sean.wang]

From: Sean Wang <sean.wang@mediatek.com>

Changes since v2:
- merge back required basic clock nodes into the .dtsi file
- update the property of interrupts in timer nodes with 2 CPUs

Changes since v1:
- update SPDX-License-Identifier
- remove next-level-cache property since cache geometry detection was removed since 4.12

This patch set adds basic SoC support for MediaTek MT7622
SoC based on 4.12-rc1.

Sean Wang (3):
  dt-bindings: mediatek: add bindings for MediaTek MT7622 SoC
  arm64: dts: mt7622: add basic nodes to the mt7622.dtsi file
  arm64: dts: mt7622: add dts file for MT7622 reference board variant 1

 Documentation/devicetree/bindings/arm/mediatek.txt |   4 +
 .../interrupt-controller/mediatek,sysirq.txt       |   3 +-
 .../devicetree/bindings/serial/mtk-uart.txt        |   1 +
 arch/arm64/boot/dts/mediatek/Makefile              |   1 +
 arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts       |  27 ++++++
 arch/arm64/boot/dts/mediatek/mt7622.dtsi           | 103 +++++++++++++++++++++
 6 files changed, 138 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
 create mode 100644 arch/arm64/boot/dts/mediatek/mt7622.dtsi

-- 
1.9.1

[PATCH v3 1/3] dt-bindings: mediatek: add bindings for MediaTek MT7622 SoC

[sean.wang]

From: Sean Wang <sean.wang@mediatek.com>

This adds dt-binding documentation for MediaTek MT7622 SoC
which currently only includes basic items such as ARM CPU,
MediaTek SYSIRQ and UART.

Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
---
 Documentation/devicetree/bindings/arm/mediatek.txt                    | 4 ++++
 .../devicetree/bindings/interrupt-controller/mediatek,sysirq.txt      | 3 ++-
 Documentation/devicetree/bindings/serial/mtk-uart.txt                 | 1 +
 3 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/arm/mediatek.txt b/Documentation/devicetree/bindings/arm/mediatek.txt
index c860b24..fc68570 100644
--- a/Documentation/devicetree/bindings/arm/mediatek.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek.txt
@@ -12,6 +12,7 @@ compatible: Must contain one of
    "mediatek,mt6592"
    "mediatek,mt6755"
    "mediatek,mt6795"
+   "mediatek,mt7622"
    "mediatek,mt7623"
    "mediatek,mt8127"
    "mediatek,mt8135"
@@ -38,6 +39,9 @@ Supported boards:
 - Evaluation board for MT6795(Helio X10):
     Required root node properties:
       - compatible = "mediatek,mt6795-evb", "mediatek,mt6795";
+- Reference board variant 1 for MT7622:
+    Required root node properties:
+      - compatible = "mediatek,mt7622-rfb1", "mediatek,mt7622";
 - Evaluation board for MT7623:
     Required root node properties:
       - compatible = "mediatek,mt7623-evb", "mediatek,mt7623";
diff --git a/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt b/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt
index a89c03b..eda1183 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt
+++ b/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt
@@ -1,4 +1,4 @@
-+Mediatek 65xx/67xx/81xx sysirq
++Mediatek MT65xx/MT67xx/MT762x/MT81xx sysirq
 
 Mediatek SOCs sysirq support controllable irq inverter for each GIC SPI
 interrupt.
@@ -15,6 +15,7 @@ Required properties:
 	"mediatek,mt6582-sysirq"
 	"mediatek,mt6580-sysirq"
 	"mediatek,mt6577-sysirq"
+	"mediatek,mt7622-sysirq"
 	"mediatek,mt2701-sysirq"
 - interrupt-controller : Identifies the node as an interrupt controller
 - #interrupt-cells : Use the same format as specified by GIC in arm,gic.txt.
diff --git a/Documentation/devicetree/bindings/serial/mtk-uart.txt b/Documentation/devicetree/bindings/serial/mtk-uart.txt
index 0015c72..daa1eef 100644
--- a/Documentation/devicetree/bindings/serial/mtk-uart.txt
+++ b/Documentation/devicetree/bindings/serial/mtk-uart.txt
@@ -8,6 +8,7 @@ Required properties:
   * "mediatek,mt6589-uart" for MT6589 compatible UARTS
   * "mediatek,mt6755-uart" for MT6755 compatible UARTS
   * "mediatek,mt6795-uart" for MT6795 compatible UARTS
+  * "mediatek,mt7622-uart" for MT7622 compatible UARTS
   * "mediatek,mt7623-uart" for MT7623 compatible UARTS
   * "mediatek,mt8127-uart" for MT8127 compatible UARTS
   * "mediatek,mt8135-uart" for MT8135 compatible UARTS
-- 
1.9.1

[PATCH v3 2/3] arm64: dts: mt7622: add basic nodes to the mt7622.dtsi file

[sean.wang]

From: Sean Wang <sean.wang@mediatek.com>

add basic nodes into the mt7622.dtsi for the system
bring-up which includes ARM CPU, GIC, timer, MediaTek
UART, SYSIRQ and one reserved memory region for ATF.

Signed-off-by: Sean Wang <sean.wang@mediatek.com>
---
 arch/arm64/boot/dts/mediatek/mt7622.dtsi | 103 +++++++++++++++++++++++++++++++
 1 file changed, 103 insertions(+)
 create mode 100644 arch/arm64/boot/dts/mediatek/mt7622.dtsi

diff --git a/arch/arm64/boot/dts/mediatek/mt7622.dtsi b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
new file mode 100644
index 0000000..2031b73
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
@@ -0,0 +1,103 @@
+/*
+ * Copyright (c) 2017 MediaTek Inc.
+ * Author: Ming Huang <ming.huang@mediatek.com>
+ *	   Sean Wang <sean.wang@mediatek.com>
+ *
+ * SPDX-License-Identifier: (GPL-2.0 OR MIT)
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+	compatible = "mediatek,mt7622";
+	interrupt-parent = <&sysirq>;
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	cpus {
+		#address-cells = <2>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53", "arm,armv8";
+			reg = <0x0 0x0>;
+			enable-method = "psci";
+			clock-frequency = <1300000000>;
+		};
+
+		cpu1: cpu@1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53", "arm,armv8";
+			reg = <0x0 0x1>;
+			enable-method = "psci";
+			clock-frequency = <1300000000>;
+		};
+	};
+
+	uart_clk: dummy26m {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <25000000>;
+	};
+
+	psci {
+		compatible  = "arm,psci-0.2";
+		method      = "smc";
+	};
+
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		/* 192 KiB reserved for ARM Trusted Firmware (BL31) */
+		secmon_reserved: secmon@43000000 {
+			reg = <0 0x43000000 0 0x30000>;
+			no-map;
+		};
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
+			      IRQ_TYPE_LEVEL_HIGH)>,
+			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
+			      IRQ_TYPE_LEVEL_HIGH)>,
+			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) |
+			      IRQ_TYPE_LEVEL_HIGH)>,
+			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
+			      IRQ_TYPE_LEVEL_HIGH)>;
+	};
+
+	sysirq: interrupt-controller@10200620 {
+		compatible = "mediatek,mt7622-sysirq",
+			     "mediatek,mt6577-sysirq";
+		interrupt-controller;
+		#interrupt-cells = <3>;
+		interrupt-parent = <&gic>;
+		reg = <0 0x10200620 0 0x20>;
+	};
+
+	gic: interrupt-controller@10300000 {
+		compatible = "arm,gic-400";
+		interrupt-controller;
+		#interrupt-cells = <3>;
+		interrupt-parent = <&gic>;
+		reg = <0 0x10310000 0 0x1000>,
+		      <0 0x10320000 0 0x1000>,
+		      <0 0x10340000 0 0x2000>,
+		      <0 0x10360000 0 0x2000>;
+	};
+
+	uart0: serial@11002000 {
+		compatible = "mediatek,mt7622-uart",
+			     "mediatek,mt6577-uart";
+		reg = <0 0x11002000 0 0x400>;
+		interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
+		clocks = <&uart_clk>;
+		status = "disabled";
+	};
+};
-- 
1.9.1

[PATCH v3 3/3] arm64: dts: mt7622: add dts file for MT7622 reference board variant 1

[sean.wang]

From: Sean Wang <sean.wang@mediatek.com>

Add the support for the MT7622 reference board variant 1 from
MediaTek.

Signed-off-by: Sean Wang <sean.wang@mediatek.com>
---
 arch/arm64/boot/dts/mediatek/Makefile        |  1 +
 arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts | 27 +++++++++++++++++++++++++++
 2 files changed, 28 insertions(+)
 create mode 100644 arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts

diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile
index 9fbfd32..e71456a2 100644
--- a/arch/arm64/boot/dts/mediatek/Makefile
+++ b/arch/arm64/boot/dts/mediatek/Makefile
@@ -1,5 +1,6 @@
 dtb-$(CONFIG_ARCH_MEDIATEK) += mt6755-evb.dtb
 dtb-$(CONFIG_ARCH_MEDIATEK) += mt6795-evb.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-rfb1.dtb
 dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-evb.dtb
 
 always		:= $(dtb-y)
diff --git a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
new file mode 100644
index 0000000..c08309d
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
@@ -0,0 +1,27 @@
+/*
+ * Copyright (c) 2017 MediaTek Inc.
+ * Author: Ming Huang <ming.huang@mediatek.com>
+ *	   Sean Wang <sean.wang@mediatek.com>
+ *
+ * SPDX-License-Identifier: (GPL-2.0 OR MIT)
+ */
+
+/dts-v1/;
+#include "mt7622.dtsi"
+
+/ {
+	model = "MediaTek MT7622 RFB1 board";
+	compatible = "mediatek,mt7622-rfb1", "mediatek,mt7622";
+
+	chosen {
+		bootargs = "console=ttyS0,115200n1";
+	};
+
+	memory {
+		reg = <0 0x40000000 0 0x3F000000>;
+	};
+};
+
+&uart0 {
+	status = "okay";
+};
-- 
1.9.1

Re: [PATCH v3 1/3] dt-bindings: mediatek: add bindings for MediaTek MT7622 SoC

[Rob Herring]

On Thu, Jun 01, 2017 at 01:28:59AM +0800, sean.wang@mediatek.com wrote:
> From: Sean Wang <sean.wang@mediatek.com>
> 
> This adds dt-binding documentation for MediaTek MT7622 SoC
> which currently only includes basic items such as ARM CPU,
> MediaTek SYSIRQ and UART.
> 
> Signed-off-by: Sean Wang <sean.wang@mediatek.com>
> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
> ---
>  Documentation/devicetree/bindings/arm/mediatek.txt                    | 4 ++++
>  .../devicetree/bindings/interrupt-controller/mediatek,sysirq.txt      | 3 ++-
>  Documentation/devicetree/bindings/serial/mtk-uart.txt                 | 1 +
>  3 files changed, 7 insertions(+), 1 deletion(-)

Acked-by: Rob Herring <robh@kernel.org>

Re: [PATCH v3 2/3] arm64: dts: mt7622: add basic nodes to the mt7622.dtsi file

[Matthias Brugger]

On 31/05/17 19:29, sean.wang@mediatek.com wrote:
> From: Sean Wang <sean.wang@mediatek.com>
> 
> add basic nodes into the mt7622.dtsi for the system
> bring-up which includes ARM CPU, GIC, timer, MediaTek
> UART, SYSIRQ and one reserved memory region for ATF.
> 
> Signed-off-by: Sean Wang <sean.wang@mediatek.com>
> ---
>   arch/arm64/boot/dts/mediatek/mt7622.dtsi | 103 +++++++++++++++++++++++++++++++
>   1 file changed, 103 insertions(+)
>   create mode 100644 arch/arm64/boot/dts/mediatek/mt7622.dtsi
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt7622.dtsi b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
> new file mode 100644
> index 0000000..2031b73
> --- /dev/null
> +++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
> @@ -0,0 +1,103 @@
> +/*
> + * Copyright (c) 2017 MediaTek Inc.
> + * Author: Ming Huang <ming.huang@mediatek.com>
> + *	   Sean Wang <sean.wang@mediatek.com>
> + *
> + * SPDX-License-Identifier: (GPL-2.0 OR MIT)
> + */
> +
> +#include <dt-bindings/interrupt-controller/irq.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +/ {
> +	compatible = "mediatek,mt7622";
> +	interrupt-parent = <&sysirq>;
> +	#address-cells = <2>;
> +	#size-cells = <2>;
> +
> +	cpus {
> +		#address-cells = <2>;
> +		#size-cells = <0>;
> +
> +		cpu0: cpu@0 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a53", "arm,armv8";
> +			reg = <0x0 0x0>;
> +			enable-method = "psci";
> +			clock-frequency = <1300000000>;
> +		};
> +
> +		cpu1: cpu@1 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a53", "arm,armv8";
> +			reg = <0x0 0x1>;
> +			enable-method = "psci";
> +			clock-frequency = <1300000000>;
> +		};
> +	};
> +
> +	uart_clk: dummy26m {
> +		compatible = "fixed-clock";
> +		#clock-cells = <0>;
> +		clock-frequency = <25000000>;
> +	};
> +
> +	psci {
> +		compatible  = "arm,psci-0.2";
> +		method      = "smc";
> +	};
> +
> +	reserved-memory {
> +		#address-cells = <2>;
> +		#size-cells = <2>;
> +		ranges;
> +
> +		/* 192 KiB reserved for ARM Trusted Firmware (BL31) */
> +		secmon_reserved: secmon@43000000 {
> +			reg = <0 0x43000000 0 0x30000>;
> +			no-map;
> +		};
> +	};
> +
> +	timer {
> +		compatible = "arm,armv8-timer";
> +		interrupt-parent = <&gic>;
> +		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
> +			      IRQ_TYPE_LEVEL_HIGH)>,
> +			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
> +			      IRQ_TYPE_LEVEL_HIGH)>,
> +			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) |
> +			      IRQ_TYPE_LEVEL_HIGH)>,
> +			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
> +			      IRQ_TYPE_LEVEL_HIGH)>;
> +	};
> +
> +	sysirq: interrupt-controller@10200620 {
> +		compatible = "mediatek,mt7622-sysirq",
> +			     "mediatek,mt6577-sysirq";
> +		interrupt-controller;
> +		#interrupt-cells = <3>;
> +		interrupt-parent = <&gic>;
> +		reg = <0 0x10200620 0 0x20>;
> +	};
> +
> +	gic: interrupt-controller@10300000 {
> +		compatible = "arm,gic-400";
> +		interrupt-controller;
> +		#interrupt-cells = <3>;
> +		interrupt-parent = <&gic>;
> +		reg = <0 0x10310000 0 0x1000>,
> +		      <0 0x10320000 0 0x1000>,
> +		      <0 0x10340000 0 0x2000>,
> +		      <0 0x10360000 0 0x2000>;
> +	};
> +
> +	uart0: serial@11002000 {
> +		compatible = "mediatek,mt7622-uart",
> +			     "mediatek,mt6577-uart";
> +		reg = <0 0x11002000 0 0x400>;
> +		interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
> +		clocks = <&uart_clk>;

mt6577-uart has two clocks. Please fix this.
I would appreciate if you could rebase on the mediatek for-next branch 
(especially for 3/3), which will make it easier for me to take this.

Regards,
Matthias

Re: [PATCH v3 1/3] dt-bindings: mediatek: add bindings for MediaTek MT7622 SoC

[Matthias Brugger]

On 07/06/17 23:30, Rob Herring wrote:
> On Thu, Jun 01, 2017 at 01:28:59AM +0800, sean.wang@mediatek.com wrote:
>> From: Sean Wang <sean.wang@mediatek.com>
>>
>> This adds dt-binding documentation for MediaTek MT7622 SoC
>> which currently only includes basic items such as ARM CPU,
>> MediaTek SYSIRQ and UART.
>>
>> Signed-off-by: Sean Wang <sean.wang@mediatek.com>
>> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
>> ---
>>   Documentation/devicetree/bindings/arm/mediatek.txt                    | 4 ++++
>>   .../devicetree/bindings/interrupt-controller/mediatek,sysirq.txt      | 3 ++-
>>   Documentation/devicetree/bindings/serial/mtk-uart.txt                 | 1 +
>>   3 files changed, 7 insertions(+), 1 deletion(-)
> 
> Acked-by: Rob Herring <robh@kernel.org>
> 

Pushed this one to v4.12-next/dts64

Thanks,
Matthias

Re: [PATCH v3 2/3] arm64: dts: mt7622: add basic nodes to the mt7622.dtsi file

[Sean Wang]

On Thu, 2017-06-08 at 15:52 +0200, Matthias Brugger wrote:
> 
> On 31/05/17 19:29, sean.wang@mediatek.com wrote:
> > From: Sean Wang <sean.wang@mediatek.com>
> > 
> > add basic nodes into the mt7622.dtsi for the system
> > bring-up which includes ARM CPU, GIC, timer, MediaTek
> > UART, SYSIRQ and one reserved memory region for ATF.
> > 
> > Signed-off-by: Sean Wang <sean.wang@mediatek.com>
> > ---
> >   arch/arm64/boot/dts/mediatek/mt7622.dtsi | 103 +++++++++++++++++++++++++++++++
> >   1 file changed, 103 insertions(+)
> >   create mode 100644 arch/arm64/boot/dts/mediatek/mt7622.dtsi
> > 
> > diff --git a/arch/arm64/boot/dts/mediatek/mt7622.dtsi b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
> > new file mode 100644
> > index 0000000..2031b73
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
> > @@ -0,0 +1,103 @@
> > +/*
> > + * Copyright (c) 2017 MediaTek Inc.
> > + * Author: Ming Huang <ming.huang@mediatek.com>
> > + *	   Sean Wang <sean.wang@mediatek.com>
> > + *
> > + * SPDX-License-Identifier: (GPL-2.0 OR MIT)
> > + */
> > +
> > +#include <dt-bindings/interrupt-controller/irq.h>
> > +#include <dt-bindings/interrupt-controller/arm-gic.h>
> > +
> > +/ {
> > +	compatible = "mediatek,mt7622";
> > +	interrupt-parent = <&sysirq>;
> > +	#address-cells = <2>;
> > +	#size-cells = <2>;
> > +
> > +	cpus {
> > +		#address-cells = <2>;
> > +		#size-cells = <0>;
> > +
> > +		cpu0: cpu@0 {
> > +			device_type = "cpu";
> > +			compatible = "arm,cortex-a53", "arm,armv8";
> > +			reg = <0x0 0x0>;
> > +			enable-method = "psci";
> > +			clock-frequency = <1300000000>;
> > +		};
> > +
> > +		cpu1: cpu@1 {
> > +			device_type = "cpu";
> > +			compatible = "arm,cortex-a53", "arm,armv8";
> > +			reg = <0x0 0x1>;
> > +			enable-method = "psci";
> > +			clock-frequency = <1300000000>;
> > +		};
> > +	};
> > +
> > +	uart_clk: dummy26m {
> > +		compatible = "fixed-clock";
> > +		#clock-cells = <0>;
> > +		clock-frequency = <25000000>;
> > +	};
> > +
> > +	psci {
> > +		compatible  = "arm,psci-0.2";
> > +		method      = "smc";
> > +	};
> > +
> > +	reserved-memory {
> > +		#address-cells = <2>;
> > +		#size-cells = <2>;
> > +		ranges;
> > +
> > +		/* 192 KiB reserved for ARM Trusted Firmware (BL31) */
> > +		secmon_reserved: secmon@43000000 {
> > +			reg = <0 0x43000000 0 0x30000>;
> > +			no-map;
> > +		};
> > +	};
> > +
> > +	timer {
> > +		compatible = "arm,armv8-timer";
> > +		interrupt-parent = <&gic>;
> > +		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
> > +			      IRQ_TYPE_LEVEL_HIGH)>,
> > +			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
> > +			      IRQ_TYPE_LEVEL_HIGH)>,
> > +			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) |
> > +			      IRQ_TYPE_LEVEL_HIGH)>,
> > +			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
> > +			      IRQ_TYPE_LEVEL_HIGH)>;
> > +	};
> > +
> > +	sysirq: interrupt-controller@10200620 {
> > +		compatible = "mediatek,mt7622-sysirq",
> > +			     "mediatek,mt6577-sysirq";
> > +		interrupt-controller;
> > +		#interrupt-cells = <3>;
> > +		interrupt-parent = <&gic>;
> > +		reg = <0 0x10200620 0 0x20>;
> > +	};
> > +
> > +	gic: interrupt-controller@10300000 {
> > +		compatible = "arm,gic-400";
> > +		interrupt-controller;
> > +		#interrupt-cells = <3>;
> > +		interrupt-parent = <&gic>;
> > +		reg = <0 0x10310000 0 0x1000>,
> > +		      <0 0x10320000 0 0x1000>,
> > +		      <0 0x10340000 0 0x2000>,
> > +		      <0 0x10360000 0 0x2000>;
> > +	};
> > +
> > +	uart0: serial@11002000 {
> > +		compatible = "mediatek,mt7622-uart",
> > +			     "mediatek,mt6577-uart";
> > +		reg = <0 0x11002000 0 0x400>;
> > +		interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
> > +		clocks = <&uart_clk>;
> 
> mt6577-uart has two clocks. Please fix this.

Those two real clocks which UART requires will be updated once the
MT7622 clock driver and the relevant binding header are all ready.
So currently the UART is using dummy clock node instead.

Is it allowed? 


> I would appreciate if you could rebase on the mediatek for-next branch 
> (especially for 3/3), which will make it easier for me to take this.
> 

O.K. I will rebase on your tree

	Sean

> Regards,
> Matthias

Re: [PATCH v3 2/3] arm64: dts: mt7622: add basic nodes to the mt7622.dtsi file

[Matthias Brugger]

On 08/06/17 18:07, Sean Wang wrote:
> On Thu, 2017-06-08 at 15:52 +0200, Matthias Brugger wrote:
>>
>> On 31/05/17 19:29, sean.wang@mediatek.com wrote:
>>> From: Sean Wang <sean.wang@mediatek.com>
>>>
>>> add basic nodes into the mt7622.dtsi for the system
>>> bring-up which includes ARM CPU, GIC, timer, MediaTek
>>> UART, SYSIRQ and one reserved memory region for ATF.
>>>
>>> Signed-off-by: Sean Wang <sean.wang@mediatek.com>
>>> ---
>>>    arch/arm64/boot/dts/mediatek/mt7622.dtsi | 103 +++++++++++++++++++++++++++++++
>>>    1 file changed, 103 insertions(+)
>>>    create mode 100644 arch/arm64/boot/dts/mediatek/mt7622.dtsi
>>>
>>> diff --git a/arch/arm64/boot/dts/mediatek/mt7622.dtsi b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
>>> new file mode 100644
>>> index 0000000..2031b73
>>> --- /dev/null
>>> +++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
>>> @@ -0,0 +1,103 @@
>>> +/*
>>> + * Copyright (c) 2017 MediaTek Inc.
>>> + * Author: Ming Huang <ming.huang@mediatek.com>
>>> + *	   Sean Wang <sean.wang@mediatek.com>
>>> + *
>>> + * SPDX-License-Identifier: (GPL-2.0 OR MIT)
>>> + */
>>> +
>>> +#include <dt-bindings/interrupt-controller/irq.h>
>>> +#include <dt-bindings/interrupt-controller/arm-gic.h>
>>> +
>>> +/ {
>>> +	compatible = "mediatek,mt7622";
>>> +	interrupt-parent = <&sysirq>;
>>> +	#address-cells = <2>;
>>> +	#size-cells = <2>;
>>> +
>>> +	cpus {
>>> +		#address-cells = <2>;
>>> +		#size-cells = <0>;
>>> +
>>> +		cpu0: cpu@0 {
>>> +			device_type = "cpu";
>>> +			compatible = "arm,cortex-a53", "arm,armv8";
>>> +			reg = <0x0 0x0>;
>>> +			enable-method = "psci";
>>> +			clock-frequency = <1300000000>;
>>> +		};
>>> +
>>> +		cpu1: cpu@1 {
>>> +			device_type = "cpu";
>>> +			compatible = "arm,cortex-a53", "arm,armv8";
>>> +			reg = <0x0 0x1>;
>>> +			enable-method = "psci";
>>> +			clock-frequency = <1300000000>;
>>> +		};
>>> +	};
>>> +
>>> +	uart_clk: dummy26m {
>>> +		compatible = "fixed-clock";
>>> +		#clock-cells = <0>;
>>> +		clock-frequency = <25000000>;
>>> +	};
>>> +
>>> +	psci {
>>> +		compatible  = "arm,psci-0.2";
>>> +		method      = "smc";
>>> +	};
>>> +
>>> +	reserved-memory {
>>> +		#address-cells = <2>;
>>> +		#size-cells = <2>;
>>> +		ranges;
>>> +
>>> +		/* 192 KiB reserved for ARM Trusted Firmware (BL31) */
>>> +		secmon_reserved: secmon@43000000 {
>>> +			reg = <0 0x43000000 0 0x30000>;
>>> +			no-map;
>>> +		};
>>> +	};
>>> +
>>> +	timer {
>>> +		compatible = "arm,armv8-timer";
>>> +		interrupt-parent = <&gic>;
>>> +		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
>>> +			      IRQ_TYPE_LEVEL_HIGH)>,
>>> +			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
>>> +			      IRQ_TYPE_LEVEL_HIGH)>,
>>> +			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) |
>>> +			      IRQ_TYPE_LEVEL_HIGH)>,
>>> +			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
>>> +			      IRQ_TYPE_LEVEL_HIGH)>;
>>> +	};
>>> +
>>> +	sysirq: interrupt-controller@10200620 {
>>> +		compatible = "mediatek,mt7622-sysirq",
>>> +			     "mediatek,mt6577-sysirq";
>>> +		interrupt-controller;
>>> +		#interrupt-cells = <3>;
>>> +		interrupt-parent = <&gic>;
>>> +		reg = <0 0x10200620 0 0x20>;
>>> +	};
>>> +
>>> +	gic: interrupt-controller@10300000 {
>>> +		compatible = "arm,gic-400";
>>> +		interrupt-controller;
>>> +		#interrupt-cells = <3>;
>>> +		interrupt-parent = <&gic>;
>>> +		reg = <0 0x10310000 0 0x1000>,
>>> +		      <0 0x10320000 0 0x1000>,
>>> +		      <0 0x10340000 0 0x2000>,
>>> +		      <0 0x10360000 0 0x2000>;
>>> +	};
>>> +
>>> +	uart0: serial@11002000 {
>>> +		compatible = "mediatek,mt7622-uart",
>>> +			     "mediatek,mt6577-uart";
>>> +		reg = <0 0x11002000 0 0x400>;
>>> +		interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
>>> +		clocks = <&uart_clk>;
>>
>> mt6577-uart has two clocks. Please fix this.
> 
> Those two real clocks which UART requires will be updated once the
> MT7622 clock driver and the relevant binding header are all ready.
> So currently the UART is using dummy clock node instead.
> 
> Is it allowed?
> 

Yes, no problem with dummy clocks at this point in time, but please 
stick to the binding.

Regards,
Matthias

> 
>> I would appreciate if you could rebase on the mediatek for-next branch
>> (especially for 3/3), which will make it easier for me to take this.
>>
> 
> O.K. I will rebase on your tree
> 
> 	Sean
> 
>> Regards,
>> Matthias
> 
>