From: "Jin, Yao" <yao.jin@linux.intel.com>
To: peterz@infradead.org
Cc: mingo@redhat.com, oleg@redhat.com, acme@kernel.org,
jolsa@kernel.org, Linux-kernel@vger.kernel.org,
ak@linux.intel.com, kan.liang@intel.com, yao.jin@intel.com,
alexander.shishkin@linux.intel.com, mark.rutland@arm.com
Subject: Re: [PATCH v1 2/2] perf/core: Fake regs for leaked kernel samples
Date: Fri, 7 Aug 2020 14:24:30 +0800 [thread overview]
Message-ID: <1d03d443-b187-bc1f-2601-a54037a64eff@linux.intel.com> (raw)
In-Reply-To: <20200806110046.GF35926@hirez.programming.kicks-ass.net>
Hi Peter,
On 8/6/2020 7:00 PM, peterz@infradead.org wrote:
> On Thu, Aug 06, 2020 at 11:18:27AM +0200, peterz@infradead.org wrote:
>
>> Suppose we have nested virt:
>>
>> L0-hv
>> |
>> G0/L1-hv
>> |
>> G1
>>
>> And we're running in G0, then:
>>
>> - 'exclude_hv' would exclude L0 events
>> - 'exclude_host' would ... exclude L1-hv events?
>> - 'exclude_guest' would ... exclude G1 events?
>
> So in arch/x86/events/intel/core.c we have:
>
> static inline void intel_set_masks(struct perf_event *event, int idx)
> {
> struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
>
> if (event->attr.exclude_host)
> __set_bit(idx, (unsigned long *)&cpuc->intel_ctrl_guest_mask);
> if (event->attr.exclude_guest)
> __set_bit(idx, (unsigned long *)&cpuc->intel_ctrl_host_mask);
> if (event_is_checkpointed(event))
> __set_bit(idx, (unsigned long *)&cpuc->intel_cp_status);
> }
>
exclude_host is now set by guest (pmc_reprogram_counter, arch/x86/kvm/pmu.c). When enabling the
event, we can check exclude_host to know if it's a guest.
Otherwise we may need more flags in event->attr to indicate the status.
> which is, afaict, just plain wrong. Should that not be something like:
>
> if (!event->attr.exclude_host)
> __set_bit(idx, (unsigned long *)&cpuc->intel_ctrl_host_mask);
> if (!event->attr.exclude_guest)
> __set_bit(idx, (unsigned long *)&cpuc->intel_ctrl_guest_mask);
>
>
How can we know it's guest or host even if exclude_host is set in guest?
Thanks
Jin Yao
> Also, ARM64 seems to also implement this stuff, Mark, do you have any
> insight on how all this is 'supposed' to work?
>
next prev parent reply other threads:[~2020-08-07 6:24 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-31 2:56 [PATCH v1 1/2] Missing instruction_pointer_set() instances Jin Yao
2020-07-31 2:56 ` [PATCH v1 2/2] perf/core: Fake regs for leaked kernel samples Jin Yao
2020-08-04 11:49 ` peterz
2020-08-05 2:15 ` Jin, Yao
2020-08-05 12:44 ` peterz
2020-08-05 12:57 ` peterz
2020-08-06 2:26 ` Jin, Yao
2020-08-06 9:18 ` peterz
2020-08-06 9:24 ` peterz
2020-08-07 5:32 ` Jin, Yao
2020-08-06 11:00 ` peterz
2020-08-07 6:24 ` Jin, Yao [this message]
2020-08-07 9:02 ` peterz
2020-08-10 2:03 ` Jin, Yao
2020-08-07 5:23 ` Jin, Yao
2020-08-11 7:50 ` Jin, Yao
2020-08-11 7:59 ` Peter Zijlstra
2020-08-11 8:31 ` Jin, Yao
2020-08-11 8:45 ` Peter Zijlstra
2020-08-12 3:52 ` Jin, Yao
2020-08-12 7:25 ` Like Xu
2020-08-04 11:31 ` [PATCH v1 1/2] Missing instruction_pointer_set() instances peterz
2020-08-05 0:26 ` Jin, Yao
2020-08-04 21:31 ` Max Filippov
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