From: Pu Wen <puwen@hygon.cn>
To: tglx@linutronix.de, mingo@redhat.com, hpa@zytor.com,
x86@kernel.org, thomas.lendacky@amd.com, bp@alien8.de,
pbonzini@redhat.com, helgaas@kernel.org
Cc: linux-kernel@vger.kernel.org, linux-arch@vger.kernel.org,
linux-pci@vger.kernel.org, Pu Wen <puwen@hygon.cn>
Subject: [PATCH v4 07/16] x86/pci: add Hygon PCI vendor and northbridge support
Date: Mon, 20 Aug 2018 00:10:50 +0800 [thread overview]
Message-ID: <1d82940cdf78f1318ccf4d30eb768039511bc9ee.1534599097.git.puwen@hygon.cn> (raw)
In-Reply-To: <cover.1534599097.git.puwen@hygon.cn>
As Hygon register its PCI Vendor ID as a new one "0x1d94", so add a new
definition PCI_VENDOR_ID_HYGON in include/linux/pci_ids.h.
Also Hygon PCI Device ID(0x1450/0x1463/0x1464) for Host bridge is added
to amd_nb.c. And it need to define new arrays for Hygon:
hygon_root_ids[], hygon_nb_misc_ids[], hygon_nb_link_ids[].
To enable Hygon north bridge support, add new variable root_ids, and
assign its value based on whether CPU vendor is AMD or Hygon. Modify
the CONFIG_AMD_NB to depends on either AMD or Hygon.
Add Hygon support in amd_postcore_init(), early_root_info_init().
Acked-by: Bjorn Helgaas <bhelgaas@google.com> # pci_ids.h
Signed-off-by: Pu Wen <puwen@hygon.cn>
---
arch/x86/Kconfig | 2 +-
arch/x86/kernel/amd_nb.c | 51 ++++++++++++++++++++++++++++++++++++++++++------
arch/x86/pci/amd_bus.c | 6 ++++--
include/linux/pci_ids.h | 2 ++
4 files changed, 52 insertions(+), 9 deletions(-)
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 6b8065d..34d05cd 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -2823,7 +2823,7 @@ endif # X86_32
config AMD_NB
def_bool y
- depends on CPU_SUP_AMD && PCI
+ depends on (CPU_SUP_AMD || CPU_SUP_HYGON) && PCI
source "drivers/pcmcia/Kconfig"
diff --git a/arch/x86/kernel/amd_nb.c b/arch/x86/kernel/amd_nb.c
index b481b95..d9867b2 100644
--- a/arch/x86/kernel/amd_nb.c
+++ b/arch/x86/kernel/amd_nb.c
@@ -20,6 +20,10 @@
#define PCI_DEVICE_ID_AMD_17H_M10H_DF_F3 0x15eb
#define PCI_DEVICE_ID_AMD_17H_M10H_DF_F4 0x15ec
+#define PCI_DEVICE_ID_HYGON_18H_ROOT 0x1450
+#define PCI_DEVICE_ID_HYGON_18H_DF_F3 0x1463
+#define PCI_DEVICE_ID_HYGON_18H_DF_F4 0x1464
+
/* Protect the PCI config register pairs used for SMN and DF indirect access. */
static DEFINE_MUTEX(smn_mutex);
@@ -61,6 +65,21 @@ static const struct pci_device_id amd_nb_link_ids[] = {
{}
};
+static const struct pci_device_id hygon_root_ids[] = {
+ { PCI_DEVICE(PCI_VENDOR_ID_HYGON, PCI_DEVICE_ID_HYGON_18H_ROOT) },
+ {}
+};
+
+const struct pci_device_id hygon_nb_misc_ids[] = {
+ { PCI_DEVICE(PCI_VENDOR_ID_HYGON, PCI_DEVICE_ID_HYGON_18H_DF_F3) },
+ {}
+};
+
+static const struct pci_device_id hygon_nb_link_ids[] = {
+ { PCI_DEVICE(PCI_VENDOR_ID_HYGON, PCI_DEVICE_ID_HYGON_18H_DF_F4) },
+ {}
+};
+
const struct amd_nb_bus_dev_range amd_nb_bus_dev_ranges[] __initconst = {
{ 0x00, 0x18, 0x20 },
{ 0xff, 0x00, 0x20 },
@@ -197,12 +216,25 @@ int amd_cache_northbridges(void)
u16 i = 0;
struct amd_northbridge *nb;
struct pci_dev *root, *misc, *link;
+ const struct pci_device_id *root_ids = NULL;
+ const struct pci_device_id *misc_ids = NULL;
+ const struct pci_device_id *link_ids = NULL;
+
+ if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) {
+ root_ids = amd_root_ids;
+ misc_ids = amd_nb_misc_ids;
+ link_ids = amd_nb_link_ids;
+ } else if (boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) {
+ root_ids = hygon_root_ids;
+ misc_ids = hygon_nb_misc_ids;
+ link_ids = hygon_nb_link_ids;
+ }
if (amd_northbridges.num)
return 0;
misc = NULL;
- while ((misc = next_northbridge(misc, amd_nb_misc_ids)) != NULL)
+ while ((misc = next_northbridge(misc, misc_ids)) != NULL)
i++;
if (!i)
@@ -218,11 +250,11 @@ int amd_cache_northbridges(void)
link = misc = root = NULL;
for (i = 0; i != amd_northbridges.num; i++) {
node_to_amd_nb(i)->root = root =
- next_northbridge(root, amd_root_ids);
+ next_northbridge(root, root_ids);
node_to_amd_nb(i)->misc = misc =
- next_northbridge(misc, amd_nb_misc_ids);
+ next_northbridge(misc, misc_ids);
node_to_amd_nb(i)->link = link =
- next_northbridge(link, amd_nb_link_ids);
+ next_northbridge(link, link_ids);
}
if (amd_gart_present())
@@ -263,9 +295,15 @@ bool __init early_is_amd_nb(u32 device)
{
const struct pci_device_id *id;
u32 vendor = device & 0xffff;
+ const struct pci_device_id *misc_ids = NULL;
+
+ if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
+ misc_ids = amd_nb_misc_ids;
+ else if (boot_cpu_data.x86_vendor == X86_VENDOR_HYGON)
+ misc_ids = hygon_nb_misc_ids;
device >>= 16;
- for (id = amd_nb_misc_ids; id->vendor; id++)
+ for (id = misc_ids; id->vendor; id++)
if (vendor == id->vendor && device == id->device)
return true;
return false;
@@ -277,7 +315,8 @@ struct resource *amd_get_mmconfig_range(struct resource *res)
u64 base, msr;
unsigned int segn_busn_bits;
- if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD)
+ if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD &&
+ boot_cpu_data.x86_vendor != X86_VENDOR_HYGON)
return NULL;
/* assume all cpus from fam10h have mmconfig */
diff --git a/arch/x86/pci/amd_bus.c b/arch/x86/pci/amd_bus.c
index 649bdde..bfa50e6 100644
--- a/arch/x86/pci/amd_bus.c
+++ b/arch/x86/pci/amd_bus.c
@@ -93,7 +93,8 @@ static int __init early_root_info_init(void)
vendor = id & 0xffff;
device = (id>>16) & 0xffff;
- if (vendor != PCI_VENDOR_ID_AMD)
+ if (vendor != PCI_VENDOR_ID_AMD &&
+ vendor != PCI_VENDOR_ID_HYGON)
continue;
if (hb_probes[i].device == device) {
@@ -390,7 +391,8 @@ static int __init pci_io_ecs_init(void)
static int __init amd_postcore_init(void)
{
- if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD)
+ if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD &&
+ boot_cpu_data.x86_vendor != X86_VENDOR_HYGON)
return 0;
early_root_info_init();
diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
index 2950223..87883cf 100644
--- a/include/linux/pci_ids.h
+++ b/include/linux/pci_ids.h
@@ -2559,6 +2559,8 @@
#define PCI_VENDOR_ID_AMAZON 0x1d0f
+#define PCI_VENDOR_ID_HYGON 0x1d94
+
#define PCI_VENDOR_ID_TEKRAM 0x1de1
#define PCI_DEVICE_ID_TEKRAM_DC290 0xdc29
--
2.7.4
next prev parent reply other threads:[~2018-08-19 16:11 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-08-19 16:07 [PATCH v4 00/16] Add support for Hygon Dhyana Family 18h processor Pu Wen
2018-08-19 16:08 ` [PATCH v4 01/16] x86/cpu: create Dhyana init file and register new cpu_dev to system Pu Wen
2018-08-19 16:09 ` [PATCH v4 02/16] x86/cache: get cache size/leaves and setup cache cpumap for Dhyana Pu Wen
2018-08-19 16:09 ` [PATCH v4 03/16] x86/mtrr: get MTRR number and support TOP_MEM2 Pu Wen
2018-08-19 16:09 ` [PATCH v4 04/16] x86/smpboot: smp init nodelay and no flush caches before sleep Pu Wen
2018-08-19 16:10 ` [PATCH v4 05/16] x86/pmu: enable Hygon support to PMU infrastructure Pu Wen
2018-08-19 16:10 ` [PATCH v4 06/16] x86/nops: init ideal_nops for Hygon Pu Wen
2018-08-19 16:10 ` Pu Wen [this message]
2018-08-19 16:11 ` [PATCH v4 08/16] x86/apic: add modern APIC support " Pu Wen
2018-08-19 16:12 ` [PATCH v4 09/16] x86/bugs: add lfence mitigation to spectre v2 and no meltdown " Pu Wen
2018-08-19 16:12 ` [PATCH v4 10/16] x86/mce: enable Hygon support to MCE infrastructure Pu Wen
2018-08-19 16:13 ` [PATCH v4 11/16] x86/kvm: enable Hygon support to KVM infrastructure Pu Wen
2018-08-19 16:13 ` [PATCH v4 12/16] x86/xen: enable Hygon support to Xen Pu Wen
2018-08-21 1:43 ` [Xen-devel] " Boris Ostrovsky
2018-08-19 16:14 ` [PATCH v4 13/16] driver/acpi: enable Hygon support to ACPI driver Pu Wen
2018-08-19 16:14 ` [PATCH v4 14/16] driver/cpufreq: enable Hygon support to cpufreq driver Pu Wen
2018-08-19 16:14 ` [PATCH v4 15/16] driver/edac: enable Hygon support to AMD64 EDAC driver Pu Wen
2018-08-21 8:13 ` Borislav Petkov
2018-08-21 11:04 ` Pu Wen
2018-08-21 11:20 ` Borislav Petkov
2018-08-21 11:26 ` Paolo Bonzini
2018-08-21 13:04 ` Borislav Petkov
2018-08-21 18:07 ` Pavel Machek
2018-08-22 13:18 ` Pu Wen
2018-08-22 13:07 ` Pu Wen
2018-08-23 8:27 ` Borislav Petkov
2018-08-19 16:15 ` [PATCH v4 16/16] tools/cpupower: enable Hygon support to cpupower tool Pu Wen
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