linux-kernel.vger.kernel.org archive mirror
 help / color / mirror / Atom feed
From: Pu Wen <puwen@hygon.cn>
To: tglx@linutronix.de, mingo@redhat.com, hpa@zytor.com,
	x86@kernel.org, thomas.lendacky@amd.com, bp@alien8.de,
	pbonzini@redhat.com
Cc: linux-kernel@vger.kernel.org, linux-arch@vger.kernel.org,
	Pu Wen <puwen@hygon.cn>
Subject: [PATCH v4 03/16] x86/mtrr: get MTRR number and support TOP_MEM2
Date: Mon, 20 Aug 2018 00:09:24 +0800	[thread overview]
Message-ID: <fdf6f5b1ccd3d9c537a6f59e8a7b10a289ade2d6.1534599097.git.puwen@hygon.cn> (raw)
In-Reply-To: <cover.1534599097.git.puwen@hygon.cn>

Hygon CPU have a special magic MSR way to force WB for memory >4GB,
and also support TOP_MEM2. Therefore, it is necessary to add Hygon
support in amd_special_default_mtrr().

The MtrrFixDramModEn bit on Hygon platform should also be set to 1
during BIOS initialization of the fixed MTRRs, then cleared to 0 for
operation.

The number of variable MTRRs for Hygon is 2 as AMD's.

Signed-off-by: Pu Wen <puwen@hygon.cn>
---
 arch/x86/kernel/cpu/mtrr/cleanup.c | 3 ++-
 arch/x86/kernel/cpu/mtrr/generic.c | 5 +++--
 arch/x86/kernel/cpu/mtrr/mtrr.c    | 2 +-
 3 files changed, 6 insertions(+), 4 deletions(-)

diff --git a/arch/x86/kernel/cpu/mtrr/cleanup.c b/arch/x86/kernel/cpu/mtrr/cleanup.c
index 765afd5..3668c5d 100644
--- a/arch/x86/kernel/cpu/mtrr/cleanup.c
+++ b/arch/x86/kernel/cpu/mtrr/cleanup.c
@@ -831,7 +831,8 @@ int __init amd_special_default_mtrr(void)
 {
 	u32 l, h;
 
-	if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD)
+	if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD &&
+	    boot_cpu_data.x86_vendor != X86_VENDOR_HYGON)
 		return 0;
 	if (boot_cpu_data.x86 < 0xf)
 		return 0;
diff --git a/arch/x86/kernel/cpu/mtrr/generic.c b/arch/x86/kernel/cpu/mtrr/generic.c
index e12ee86..77c3eaa 100644
--- a/arch/x86/kernel/cpu/mtrr/generic.c
+++ b/arch/x86/kernel/cpu/mtrr/generic.c
@@ -49,8 +49,9 @@ static inline void k8_check_syscfg_dram_mod_en(void)
 {
 	u32 lo, hi;
 
-	if (!((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) &&
-	      (boot_cpu_data.x86 >= 0x0f)))
+	if (!((boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
+	       boot_cpu_data.x86 >= 0x0f) ||
+	       boot_cpu_data.x86_vendor == X86_VENDOR_HYGON))
 		return;
 
 	rdmsr(MSR_K8_SYSCFG, lo, hi);
diff --git a/arch/x86/kernel/cpu/mtrr/mtrr.c b/arch/x86/kernel/cpu/mtrr/mtrr.c
index 9a19c80..507039c 100644
--- a/arch/x86/kernel/cpu/mtrr/mtrr.c
+++ b/arch/x86/kernel/cpu/mtrr/mtrr.c
@@ -127,7 +127,7 @@ static void __init set_num_var_ranges(void)
 
 	if (use_intel())
 		rdmsr(MSR_MTRRcap, config, dummy);
-	else if (is_cpu(AMD))
+	else if (is_cpu(AMD) || is_cpu(HYGON))
 		config = 2;
 	else if (is_cpu(CYRIX) || is_cpu(CENTAUR))
 		config = 8;
-- 
2.7.4


  parent reply	other threads:[~2018-08-19 16:09 UTC|newest]

Thread overview: 27+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-08-19 16:07 [PATCH v4 00/16] Add support for Hygon Dhyana Family 18h processor Pu Wen
2018-08-19 16:08 ` [PATCH v4 01/16] x86/cpu: create Dhyana init file and register new cpu_dev to system Pu Wen
2018-08-19 16:09 ` [PATCH v4 02/16] x86/cache: get cache size/leaves and setup cache cpumap for Dhyana Pu Wen
2018-08-19 16:09 ` Pu Wen [this message]
2018-08-19 16:09 ` [PATCH v4 04/16] x86/smpboot: smp init nodelay and no flush caches before sleep Pu Wen
2018-08-19 16:10 ` [PATCH v4 05/16] x86/pmu: enable Hygon support to PMU infrastructure Pu Wen
2018-08-19 16:10 ` [PATCH v4 06/16] x86/nops: init ideal_nops for Hygon Pu Wen
2018-08-19 16:10 ` [PATCH v4 07/16] x86/pci: add Hygon PCI vendor and northbridge support Pu Wen
2018-08-19 16:11 ` [PATCH v4 08/16] x86/apic: add modern APIC support for Hygon Pu Wen
2018-08-19 16:12 ` [PATCH v4 09/16] x86/bugs: add lfence mitigation to spectre v2 and no meltdown " Pu Wen
2018-08-19 16:12 ` [PATCH v4 10/16] x86/mce: enable Hygon support to MCE infrastructure Pu Wen
2018-08-19 16:13 ` [PATCH v4 11/16] x86/kvm: enable Hygon support to KVM infrastructure Pu Wen
2018-08-19 16:13 ` [PATCH v4 12/16] x86/xen: enable Hygon support to Xen Pu Wen
2018-08-21  1:43   ` [Xen-devel] " Boris Ostrovsky
2018-08-19 16:14 ` [PATCH v4 13/16] driver/acpi: enable Hygon support to ACPI driver Pu Wen
2018-08-19 16:14 ` [PATCH v4 14/16] driver/cpufreq: enable Hygon support to cpufreq driver Pu Wen
2018-08-19 16:14 ` [PATCH v4 15/16] driver/edac: enable Hygon support to AMD64 EDAC driver Pu Wen
2018-08-21  8:13   ` Borislav Petkov
2018-08-21 11:04     ` Pu Wen
2018-08-21 11:20       ` Borislav Petkov
2018-08-21 11:26         ` Paolo Bonzini
2018-08-21 13:04           ` Borislav Petkov
2018-08-21 18:07             ` Pavel Machek
2018-08-22 13:18               ` Pu Wen
2018-08-22 13:07             ` Pu Wen
2018-08-23  8:27               ` Borislav Petkov
2018-08-19 16:15 ` [PATCH v4 16/16] tools/cpupower: enable Hygon support to cpupower tool Pu Wen

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=fdf6f5b1ccd3d9c537a6f59e8a7b10a289ade2d6.1534599097.git.puwen@hygon.cn \
    --to=puwen@hygon.cn \
    --cc=bp@alien8.de \
    --cc=hpa@zytor.com \
    --cc=linux-arch@vger.kernel.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=mingo@redhat.com \
    --cc=pbonzini@redhat.com \
    --cc=tglx@linutronix.de \
    --cc=thomas.lendacky@amd.com \
    --cc=x86@kernel.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).