From: Abhishek Sahu <absahu@codeaurora.org>
To: Sricharan R <sricharan@codeaurora.org>
Cc: Archit Taneja <architt@codeaurora.org>,
dwmw2@infradead.org, computersforpeace@gmail.com,
boris.brezillon@free-electrons.com, marek.vasut@gmail.com,
richard@nod.at, cyrille.pitchen@wedev4u.fr, robh+dt@kernel.org,
mark.rutland@arm.com, devicetree@vger.kernel.org,
linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-mtd@lists.infradead.org, andy.gross@linaro.org
Subject: Re: [PATCH 07/14] qcom: mtd: nand: support for passing flags in transfer functions
Date: Mon, 17 Jul 2017 12:29:37 +0530 [thread overview]
Message-ID: <1ebb05e67a5d29d19da5743e8d995946@codeaurora.org> (raw)
In-Reply-To: <70776f79-6d51-5544-8be8-38e62b7c073e@codeaurora.org>
On 2017-07-10 19:40, Sricharan R wrote:
> Hi,
>
> On 7/4/2017 12:19 PM, Archit Taneja wrote:
>>
>>
>> On 06/29/2017 12:45 PM, Abhishek Sahu wrote:
>>> The BAM has multiple flags to control the transfer. This patch
>>> adds flags parameter in register and data transfer functions and
>>> modifies all these function call with appropriate flags.
>>>
>>> Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
>>> ---
>>> drivers/mtd/nand/qcom_nandc.c | 114
>>> ++++++++++++++++++++++++------------------
>>> 1 file changed, 65 insertions(+), 49 deletions(-)
>>>
>>> diff --git a/drivers/mtd/nand/qcom_nandc.c
>>> b/drivers/mtd/nand/qcom_nandc.c
>>> index 7042a65..65c9059 100644
>>> --- a/drivers/mtd/nand/qcom_nandc.c
>>> +++ b/drivers/mtd/nand/qcom_nandc.c
>>> @@ -170,6 +170,14 @@
>>> #define ECC_BCH_4BIT BIT(2)
>>> #define ECC_BCH_8BIT BIT(3)
>>> +/* Flags used for BAM DMA desc preparation*/
>>> +/* Don't set the EOT in current tx sgl */
>>> +#define NAND_BAM_NO_EOT (0x0001)
>>> +/* Set the NWD flag in current sgl */
>>> +#define NAND_BAM_NWD (0x0002)
>>> +/* Finish writing in the current sgl and start writing in another
>>> sgl */
>>> +#define NAND_BAM_NEXT_SGL (0x0004)
>>> +
>>> #define QPIC_PER_CW_MAX_CMD_ELEMENTS (32)
>>> #define QPIC_PER_CW_MAX_CMD_SGL (32)
>>> #define QPIC_PER_CW_MAX_DATA_SGL (8)
I will remove the braces and use the bit macros.
>>> @@ -712,7 +720,7 @@ static int prep_dma_desc(struct
>>> qcom_nand_controller
>>> *nandc, bool read,
>>> * @num_regs: number of registers to read
>>> */
>>> static int read_reg_dma(struct qcom_nand_controller *nandc, int
>>> first,
>>> - int num_regs)
>>> + int num_regs, unsigned int flags)
>>> {
>>> bool flow_control = false;
>>> void *vaddr;
>>> @@ -736,7 +744,7 @@ static int read_reg_dma(struct
>>> qcom_nand_controller
>>> *nandc, int first,
>>> * @num_regs: number of registers to write
>>> */
>>> static int write_reg_dma(struct qcom_nand_controller *nandc, int
>>> first,
>>> - int num_regs)
>>> + int num_regs, unsigned int flags)
>>
>> Adding flags to read_reg_dma and write_reg_dma is making things a bit
>> messy. I can't
>> think of a better way to share the code either, though.
>>
>> One thing we could consider doing is something like below. I don't
>> know if
>> it would
>> make things more legible.
>>
>> union nand_dma_props {
>> bool adm_flow_control;
>> unsigned int bam_flags;
>> };
>>
>> config_cw_read()
>> {
>> union nand_dma_props dma_props;
>> ...
>> ...
>>
>> if (is_bam)
>> dma_props.bam_flags = NAND_BAM_NWD;
>> else
>> dma_props.adm_flow_control = false;
>>
>> write_reg_dma(nandc, NAND_EXEC_CMD, 1, &dma_props);
>> ...
>> ...
>> }
The flags for each write_reg_dma and read_reg_dma will be different.
Normally, for all the API's which uses flags
(like dmaengine_prep_slave_sg), we are passing the flags directly.
this union won't help us making this code more readable.
>
> Right, with this , i think we can have two different indirections for
> functions like,
> prep_dma_desc_command and prep_dma_desc. That will help to reduce the
> bam_dma_enabled
> checks.
Since common code changes are intermixed with bam_dma_enabled check
so taking function pointer won't help much in making code more
readable.
anyway, I will analyze the final code for v2 and will check the
possibility of using function pointers.
>
> Regards,
> Sricharan
--
Abhishek Sahu
next prev parent reply other threads:[~2017-07-17 6:59 UTC|newest]
Thread overview: 55+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-06-29 7:15 [PATCH 00/14] Add QCOM QPIC NAND support Abhishek Sahu
2017-06-29 7:15 ` [PATCH 01/14] qcom: mtd: nand: Add driver data for QPIC DMA Abhishek Sahu
2017-06-29 9:46 ` Marek Vasut
2017-07-03 4:38 ` Archit Taneja
2017-07-03 19:41 ` Boris Brezillon
2017-07-17 6:11 ` Abhishek Sahu
2017-07-17 7:22 ` Boris Brezillon
2017-07-17 8:49 ` Abhishek Sahu
2017-07-03 6:21 ` Sricharan R
2017-06-29 7:15 ` [PATCH 02/14] qcom: mtd: nand: add and initialize QPIC DMA resources Abhishek Sahu
2017-06-29 9:48 ` Marek Vasut
2017-07-17 6:36 ` Abhishek Sahu
2017-07-03 5:17 ` Archit Taneja
2017-07-17 6:26 ` Abhishek Sahu
2017-07-03 6:24 ` Sricharan R
2017-07-03 6:32 ` Sricharan R
2017-06-29 7:15 ` [PATCH 03/14] qcom: mtd: nand: Fixed config error for BCH Abhishek Sahu
2017-06-29 9:49 ` Marek Vasut
2017-07-03 19:47 ` Boris Brezillon
2017-07-17 6:38 ` Abhishek Sahu
2017-07-03 6:25 ` Sricharan R
2017-06-29 7:15 ` [PATCH 04/14] qcom: mtd: nand: reorganize nand devices probing Abhishek Sahu
2017-06-29 7:15 ` [PATCH 05/14] qcom: mtd: nand: allocate bam transaction Abhishek Sahu
2017-06-29 9:50 ` Marek Vasut
2017-07-17 6:42 ` Abhishek Sahu
2017-07-03 8:22 ` Sricharan R
2017-07-17 6:44 ` Abhishek Sahu
2017-06-29 7:15 ` [PATCH 06/14] qcom: mtd: nand: add bam dma descriptor handling Abhishek Sahu
2017-07-04 6:10 ` Archit Taneja
2017-07-17 6:47 ` Abhishek Sahu
2017-06-29 7:15 ` [PATCH 07/14] qcom: mtd: nand: support for passing flags in transfer functions Abhishek Sahu
2017-06-29 9:52 ` Marek Vasut
2017-07-04 6:49 ` Archit Taneja
2017-07-10 14:10 ` Sricharan R
2017-07-17 6:59 ` Abhishek Sahu [this message]
2017-06-29 7:16 ` [PATCH 08/14] qcom: mtd: nand: Add support for additional CSRs Abhishek Sahu
2017-07-04 6:54 ` Archit Taneja
2017-07-17 7:10 ` Abhishek Sahu
2017-06-29 7:16 ` [PATCH 09/14] qcom: mtd: nand: BAM support for read page Abhishek Sahu
2017-07-04 9:40 ` Archit Taneja
2017-07-10 14:15 ` Sricharan R
2017-07-17 7:17 ` Abhishek Sahu
2017-06-29 7:16 ` [PATCH 10/14] qcom: mtd: nand: support for QPIC Page read/write Abhishek Sahu
2017-07-04 9:44 ` Archit Taneja
2017-07-17 7:25 ` Abhishek Sahu
2017-07-10 14:18 ` Sricharan R
2017-07-17 7:36 ` Abhishek Sahu
2017-06-29 7:16 ` [PATCH 11/14] qcom: mtd: nand: BAM raw read and write support Abhishek Sahu
2017-06-29 7:16 ` [PATCH 12/14] qcom: mtd: nand: change register offset defines with enums Abhishek Sahu
2017-07-04 9:55 ` Archit Taneja
2017-07-17 7:31 ` Abhishek Sahu
2017-06-29 7:16 ` [PATCH 13/14] qcom: mtd: nand: support for QPIC version 1.5.0 Abhishek Sahu
2017-07-04 9:57 ` Archit Taneja
2017-07-17 7:32 ` Abhishek Sahu
2017-06-29 7:16 ` [PATCH 14/14] qcom: mtd: nand: programmed NAND_DEV_CMD_VLD register Abhishek Sahu
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