From: Archit Taneja <architt@codeaurora.org>
To: Abhishek Sahu <absahu@codeaurora.org>,
dwmw2@infradead.org, computersforpeace@gmail.com,
boris.brezillon@free-electrons.com, marek.vasut@gmail.com,
richard@nod.at, cyrille.pitchen@wedev4u.fr, robh+dt@kernel.org,
mark.rutland@arm.com
Cc: linux-mtd@lists.infradead.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org,
andy.gross@linaro.org, sricharan@codeaurora.org
Subject: Re: [PATCH 08/14] qcom: mtd: nand: Add support for additional CSRs
Date: Tue, 4 Jul 2017 12:24:34 +0530 [thread overview]
Message-ID: <a04e02b5-56c0-3fb8-813e-a2dd8a53861f@codeaurora.org> (raw)
In-Reply-To: <1498720566-20782-9-git-send-email-absahu@codeaurora.org>
On 06/29/2017 12:46 PM, Abhishek Sahu wrote:
> 1. NAND_READ_LOCATION: provides the offset in page for
> reading in BAM DMA mode
>
> 2. NAND_ERASED_CW_DETECT_CFG: contains the status for erased
> code words
>
> 3. NAND_BUFFER_STATUS: contains the status for ECC
>
> Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
> ---
> drivers/mtd/nand/qcom_nandc.c | 67 ++++++++++++++++++++++++++++++++++++++++++-
> 1 file changed, 66 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
> index 65c9059..8e7dc9e 100644
> --- a/drivers/mtd/nand/qcom_nandc.c
> +++ b/drivers/mtd/nand/qcom_nandc.c
> @@ -54,6 +54,8 @@
> #define NAND_VERSION 0xf08
> #define NAND_READ_LOCATION_0 0xf20
> #define NAND_READ_LOCATION_1 0xf24
> +#define NAND_READ_LOCATION_2 0xf28
> +#define NAND_READ_LOCATION_3 0xf2c
>
> /* dummy register offsets, used by write_reg_dma */
> #define NAND_DEV_CMD1_RESTORE 0xdead
> @@ -132,6 +134,11 @@
> #define ERASED_PAGE (PAGE_ALL_ERASED | PAGE_ERASED)
> #define ERASED_CW (CODEWORD_ALL_ERASED | CODEWORD_ERASED)
>
> +/* NAND_READ_LOCATION_n bits */
> +#define READ_LOCATION_OFFSET 0
> +#define READ_LOCATION_SIZE 16
> +#define READ_LOCATION_LAST 31
> +
> /* Version Mask */
> #define NAND_VERSION_MAJOR_MASK 0xf0000000
> #define NAND_VERSION_MAJOR_SHIFT 28
> @@ -177,6 +184,11 @@
> #define NAND_BAM_NWD (0x0002)
> /* Finish writing in the current sgl and start writing in another sgl */
> #define NAND_BAM_NEXT_SGL (0x0004)
> +/*
> + * Erased codeword status is being used two times in single transfer so this
> + * flag will determine the current value of erased codeword status register
> + */
> +#define NAND_ERASED_CW_SET (0x0008)
>
> #define QPIC_PER_CW_MAX_CMD_ELEMENTS (32)
> #define QPIC_PER_CW_MAX_CMD_SGL (32)
> @@ -258,6 +270,13 @@ struct nandc_regs {
> __le32 orig_vld;
>
> __le32 ecc_buf_cfg;
> + __le32 read_location0;
> + __le32 read_location1;
> + __le32 read_location2;
> + __le32 read_location3;
> +
> + __le32 erased_cw_detect_cfg_clr;
> + __le32 erased_cw_detect_cfg_set;
> };
>
> /*
> @@ -504,6 +523,16 @@ static __le32 *offset_to_nandc_reg(struct nandc_regs *regs, int offset)
> return ®s->orig_vld;
> case NAND_EBI2_ECC_BUF_CFG:
> return ®s->ecc_buf_cfg;
> + case NAND_BUFFER_STATUS:
> + return ®s->clrreadstatus;
> + case NAND_READ_LOCATION_0:
> + return ®s->read_location0;
> + case NAND_READ_LOCATION_1:
> + return ®s->read_location1;
> + case NAND_READ_LOCATION_2:
> + return ®s->read_location2;
> + case NAND_READ_LOCATION_3:
> + return ®s->read_location3;
> default:
> return NULL;
> }
> @@ -545,7 +574,7 @@ static void update_rw_regs(struct qcom_nand_host *host, int num_cw, bool read)
> {
> struct nand_chip *chip = &host->chip;
> struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
> - u32 cmd, cfg0, cfg1, ecc_bch_cfg;
> + u32 cmd, cfg0, cfg1, ecc_bch_cfg, read_location0;
>
> if (read) {
> if (host->use_ecc)
> @@ -562,12 +591,20 @@ static void update_rw_regs(struct qcom_nand_host *host, int num_cw, bool read)
>
> cfg1 = host->cfg1;
> ecc_bch_cfg = host->ecc_bch_cfg;
> + if (read)
> + read_location0 = (0 << READ_LOCATION_OFFSET) |
> + (host->cw_data << READ_LOCATION_SIZE) |
> + (1 << READ_LOCATION_LAST);
> } else {
> cfg0 = (host->cfg0_raw & ~(7U << CW_PER_PAGE)) |
> (num_cw - 1) << CW_PER_PAGE;
>
> cfg1 = host->cfg1_raw;
> ecc_bch_cfg = 1 << ECC_CFG_ECC_DISABLE;
> + if (read)
> + read_location0 = (0 << READ_LOCATION_OFFSET) |
> + (host->cw_size << READ_LOCATION_SIZE) |
> + (1 << READ_LOCATION_LAST);
> }
>
> nandc_set_reg(nandc, NAND_FLASH_CMD, cmd);
> @@ -578,6 +615,9 @@ static void update_rw_regs(struct qcom_nand_host *host, int num_cw, bool read)
> nandc_set_reg(nandc, NAND_FLASH_STATUS, host->clrflashstatus);
> nandc_set_reg(nandc, NAND_READ_STATUS, host->clrreadstatus);
> nandc_set_reg(nandc, NAND_EXEC_CMD, 1);
> +
> + if (read)
> + nandc_set_reg(nandc, NAND_READ_LOCATION_0, read_location0);
> }
>
> /*
> @@ -756,6 +796,13 @@ static int write_reg_dma(struct qcom_nand_controller *nandc, int first,
> if (first == NAND_FLASH_CMD)
> flow_control = true;
>
> + if (first == NAND_ERASED_CW_DETECT_CFG) {
> + if (flags & NAND_ERASED_CW_SET)
> + vaddr = ®s->erased_cw_detect_cfg_set;
> + else
> + vaddr = ®s->erased_cw_detect_cfg_clr;
> + }
> +
> if (first == NAND_EXEC_CMD)
> flags |= NAND_BAM_NWD;
>
> @@ -808,6 +855,12 @@ static void config_cw_read(struct qcom_nand_controller *nandc)
> write_reg_dma(nandc, NAND_DEV0_CFG0, 3, 0);
> write_reg_dma(nandc, NAND_EBI2_ECC_BUF_CFG, 1, 0);
>
> + write_reg_dma(nandc, NAND_ERASED_CW_DETECT_CFG, 1, 0);
> + write_reg_dma(nandc, NAND_ERASED_CW_DETECT_CFG, 1, NAND_ERASED_CW_SET);
> + if (nandc->dma_bam_enabled)
> + write_reg_dma(nandc, NAND_READ_LOCATION_0, 1,
> + NAND_BAM_NEXT_SGL);
> +
> write_reg_dma(nandc, NAND_EXEC_CMD, 1,
> NAND_BAM_NWD | NAND_BAM_NEXT_SGL);
>
> @@ -882,6 +935,10 @@ static int nandc_param(struct qcom_nand_host *host)
>
> nandc_set_reg(nandc, NAND_DEV_CMD1_RESTORE, nandc->cmd1);
> nandc_set_reg(nandc, NAND_DEV_CMD_VLD_RESTORE, nandc->vld);
> + nandc_set_reg(nandc, NAND_READ_LOCATION_0,
> + (0 << READ_LOCATION_OFFSET) |
> + (512 << READ_LOCATION_SIZE) |
> + (1 << READ_LOCATION_LAST));
>
> write_reg_dma(nandc, NAND_DEV_CMD_VLD, 1, 0);
> write_reg_dma(nandc, NAND_DEV_CMD1, 1, NAND_BAM_NEXT_SGL);
> @@ -1413,6 +1470,10 @@ static int copy_last_cw(struct qcom_nand_host *host, int page)
>
> set_address(host, host->cw_size * (ecc->steps - 1), page);
> update_rw_regs(host, 1, true);
> + nandc_set_reg(nandc, NAND_READ_LOCATION_0,
> + (0 << READ_LOCATION_OFFSET) |
> + (size << READ_LOCATION_SIZE) |
> + (1 << READ_LOCATION_LAST));
>
> config_cw_read(nandc);
>
> @@ -2147,6 +2208,10 @@ static int qcom_nand_host_setup(struct qcom_nand_host *host)
>
> host->clrflashstatus = FS_READY_BSY_N;
> host->clrreadstatus = 0xc0;
> + nandc->regs->erased_cw_detect_cfg_clr =
> + cpu_to_le32(CLR_ERASED_PAGE_DET);
> + nandc->regs->erased_cw_detect_cfg_set =
> + cpu_to_le32(SET_ERASED_PAGE_DET);
>
Can these 2 be put in qcom_nand_host like done for other registers?
Thanks,
Archit
> dev_dbg(nandc->dev,
> "cfg0 %x cfg1 %x ecc_buf_cfg %x ecc_bch cfg %x cw_size %d cw_data %d strength %d parity_bytes %d steps %d\n",
>
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
next prev parent reply other threads:[~2017-07-04 6:54 UTC|newest]
Thread overview: 55+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-06-29 7:15 [PATCH 00/14] Add QCOM QPIC NAND support Abhishek Sahu
2017-06-29 7:15 ` [PATCH 01/14] qcom: mtd: nand: Add driver data for QPIC DMA Abhishek Sahu
2017-06-29 9:46 ` Marek Vasut
2017-07-03 4:38 ` Archit Taneja
2017-07-03 19:41 ` Boris Brezillon
2017-07-17 6:11 ` Abhishek Sahu
2017-07-17 7:22 ` Boris Brezillon
2017-07-17 8:49 ` Abhishek Sahu
2017-07-03 6:21 ` Sricharan R
2017-06-29 7:15 ` [PATCH 02/14] qcom: mtd: nand: add and initialize QPIC DMA resources Abhishek Sahu
2017-06-29 9:48 ` Marek Vasut
2017-07-17 6:36 ` Abhishek Sahu
2017-07-03 5:17 ` Archit Taneja
2017-07-17 6:26 ` Abhishek Sahu
2017-07-03 6:24 ` Sricharan R
2017-07-03 6:32 ` Sricharan R
2017-06-29 7:15 ` [PATCH 03/14] qcom: mtd: nand: Fixed config error for BCH Abhishek Sahu
2017-06-29 9:49 ` Marek Vasut
2017-07-03 19:47 ` Boris Brezillon
2017-07-17 6:38 ` Abhishek Sahu
2017-07-03 6:25 ` Sricharan R
2017-06-29 7:15 ` [PATCH 04/14] qcom: mtd: nand: reorganize nand devices probing Abhishek Sahu
2017-06-29 7:15 ` [PATCH 05/14] qcom: mtd: nand: allocate bam transaction Abhishek Sahu
2017-06-29 9:50 ` Marek Vasut
2017-07-17 6:42 ` Abhishek Sahu
2017-07-03 8:22 ` Sricharan R
2017-07-17 6:44 ` Abhishek Sahu
2017-06-29 7:15 ` [PATCH 06/14] qcom: mtd: nand: add bam dma descriptor handling Abhishek Sahu
2017-07-04 6:10 ` Archit Taneja
2017-07-17 6:47 ` Abhishek Sahu
2017-06-29 7:15 ` [PATCH 07/14] qcom: mtd: nand: support for passing flags in transfer functions Abhishek Sahu
2017-06-29 9:52 ` Marek Vasut
2017-07-04 6:49 ` Archit Taneja
2017-07-10 14:10 ` Sricharan R
2017-07-17 6:59 ` Abhishek Sahu
2017-06-29 7:16 ` [PATCH 08/14] qcom: mtd: nand: Add support for additional CSRs Abhishek Sahu
2017-07-04 6:54 ` Archit Taneja [this message]
2017-07-17 7:10 ` Abhishek Sahu
2017-06-29 7:16 ` [PATCH 09/14] qcom: mtd: nand: BAM support for read page Abhishek Sahu
2017-07-04 9:40 ` Archit Taneja
2017-07-10 14:15 ` Sricharan R
2017-07-17 7:17 ` Abhishek Sahu
2017-06-29 7:16 ` [PATCH 10/14] qcom: mtd: nand: support for QPIC Page read/write Abhishek Sahu
2017-07-04 9:44 ` Archit Taneja
2017-07-17 7:25 ` Abhishek Sahu
2017-07-10 14:18 ` Sricharan R
2017-07-17 7:36 ` Abhishek Sahu
2017-06-29 7:16 ` [PATCH 11/14] qcom: mtd: nand: BAM raw read and write support Abhishek Sahu
2017-06-29 7:16 ` [PATCH 12/14] qcom: mtd: nand: change register offset defines with enums Abhishek Sahu
2017-07-04 9:55 ` Archit Taneja
2017-07-17 7:31 ` Abhishek Sahu
2017-06-29 7:16 ` [PATCH 13/14] qcom: mtd: nand: support for QPIC version 1.5.0 Abhishek Sahu
2017-07-04 9:57 ` Archit Taneja
2017-07-17 7:32 ` Abhishek Sahu
2017-06-29 7:16 ` [PATCH 14/14] qcom: mtd: nand: programmed NAND_DEV_CMD_VLD register Abhishek Sahu
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