* [PATCH v4 0/2] Add Basic SoC support for MT7622
@ 2017-06-14 16:11 sean.wang
2017-06-14 16:11 ` [PATCH v4 1/2] arm64: dts: mt7622: add basic nodes to the mt7622.dtsi file sean.wang
2017-06-14 16:11 ` [PATCH v4 2/2] arm64: dts: mt7622: add dts file for MT7622 reference board variant 1 sean.wang
0 siblings, 2 replies; 5+ messages in thread
From: sean.wang @ 2017-06-14 16:11 UTC (permalink / raw)
To: robh+dt, matthias.bgg, mark.rutland, devicetree, john, linux-mediatek
Cc: linux-arm-kernel, linux-kernel, Sean Wang
From: Sean Wang <sean.wang@mediatek.com>
Changes since v3:
- get rid of those accepted patches
- rebased to branch v4.12-next/dts64 in Matthias' tree
- fixed uart node in dts with two clocks as described in bindings documentation
Changes since v2:
- merge back required basic clock nodes into the .dtsi file
- update the property of interrupts in timer nodes with 2 CPUs
Changes since v1:
- update SPDX-License-Identifier
- remove next-level-cache property since cache geometry detection was removed since 4.12
This patch set adds basic SoC support for MediaTek MT7622
SoC based on 4.12-rc1.
Sean Wang (2):
arm64: dts: mt7622: add basic nodes to the mt7622.dtsi file
arm64: dts: mt7622: add dts file for MT7622 reference board variant 1
arch/arm64/boot/dts/mediatek/Makefile | 1 +
arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts | 27 +++++++
arch/arm64/boot/dts/mediatek/mt7622.dtsi | 104 +++++++++++++++++++++++++++
3 files changed, 132 insertions(+)
create mode 100644 arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
create mode 100644 arch/arm64/boot/dts/mediatek/mt7622.dtsi
--
2.7.4
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH v4 1/2] arm64: dts: mt7622: add basic nodes to the mt7622.dtsi file
2017-06-14 16:11 [PATCH v4 0/2] Add Basic SoC support for MT7622 sean.wang
@ 2017-06-14 16:11 ` sean.wang
2017-06-15 16:04 ` Matthias Brugger
2017-06-14 16:11 ` [PATCH v4 2/2] arm64: dts: mt7622: add dts file for MT7622 reference board variant 1 sean.wang
1 sibling, 1 reply; 5+ messages in thread
From: sean.wang @ 2017-06-14 16:11 UTC (permalink / raw)
To: robh+dt, matthias.bgg, mark.rutland, devicetree, john, linux-mediatek
Cc: linux-arm-kernel, linux-kernel, Sean Wang
From: Sean Wang <sean.wang@mediatek.com>
add basic nodes into the mt7622.dtsi for the system
bring-up which includes ARM CPU, GIC, timer, MediaTek
UART, SYSIRQ and one reserved memory region for ATF.
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt7622.dtsi | 104 +++++++++++++++++++++++++++++++
1 file changed, 104 insertions(+)
create mode 100644 arch/arm64/boot/dts/mediatek/mt7622.dtsi
diff --git a/arch/arm64/boot/dts/mediatek/mt7622.dtsi b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
new file mode 100644
index 0000000..239b9b3
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
@@ -0,0 +1,104 @@
+/*
+ * Copyright (c) 2017 MediaTek Inc.
+ * Author: Ming Huang <ming.huang@mediatek.com>
+ * Sean Wang <sean.wang@mediatek.com>
+ *
+ * SPDX-License-Identifier: (GPL-2.0 OR MIT)
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+ compatible = "mediatek,mt7622";
+ interrupt-parent = <&sysirq>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <0x0 0x0>;
+ enable-method = "psci";
+ clock-frequency = <1300000000>;
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <0x0 0x1>;
+ enable-method = "psci";
+ clock-frequency = <1300000000>;
+ };
+ };
+
+ uart_clk: dummy25m {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <25000000>;
+ };
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ /* 192 KiB reserved for ARM Trusted Firmware (BL31) */
+ secmon_reserved: secmon@43000000 {
+ reg = <0 0x43000000 0 0x30000>;
+ no-map;
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
+ IRQ_TYPE_LEVEL_HIGH)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
+ IRQ_TYPE_LEVEL_HIGH)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) |
+ IRQ_TYPE_LEVEL_HIGH)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
+ IRQ_TYPE_LEVEL_HIGH)>;
+ };
+
+ sysirq: interrupt-controller@10200620 {
+ compatible = "mediatek,mt7622-sysirq",
+ "mediatek,mt6577-sysirq";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ interrupt-parent = <&gic>;
+ reg = <0 0x10200620 0 0x20>;
+ };
+
+ gic: interrupt-controller@10300000 {
+ compatible = "arm,gic-400";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ interrupt-parent = <&gic>;
+ reg = <0 0x10310000 0 0x1000>,
+ <0 0x10320000 0 0x1000>,
+ <0 0x10340000 0 0x2000>,
+ <0 0x10360000 0 0x2000>;
+ };
+
+ uart0: serial@11002000 {
+ compatible = "mediatek,mt7622-uart",
+ "mediatek,mt6577-uart";
+ reg = <0 0x11002000 0 0x400>;
+ interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&uart_clk>, <&uart_clk>;
+ clock-names = "baud", "bus";
+ status = "disabled";
+ };
+};
--
2.7.4
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH v4 2/2] arm64: dts: mt7622: add dts file for MT7622 reference board variant 1
2017-06-14 16:11 [PATCH v4 0/2] Add Basic SoC support for MT7622 sean.wang
2017-06-14 16:11 ` [PATCH v4 1/2] arm64: dts: mt7622: add basic nodes to the mt7622.dtsi file sean.wang
@ 2017-06-14 16:11 ` sean.wang
1 sibling, 0 replies; 5+ messages in thread
From: sean.wang @ 2017-06-14 16:11 UTC (permalink / raw)
To: robh+dt, matthias.bgg, mark.rutland, devicetree, john, linux-mediatek
Cc: linux-arm-kernel, linux-kernel, Sean Wang
From: Sean Wang <sean.wang@mediatek.com>
Add the support for the MT7622 reference board variant 1 from
MediaTek.
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
---
arch/arm64/boot/dts/mediatek/Makefile | 1 +
arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts | 27 +++++++++++++++++++++++++++
2 files changed, 28 insertions(+)
create mode 100644 arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile
index 015eb07..89371be 100644
--- a/arch/arm64/boot/dts/mediatek/Makefile
+++ b/arch/arm64/boot/dts/mediatek/Makefile
@@ -1,6 +1,7 @@
dtb-$(CONFIG_ARCH_MEDIATEK) += mt6755-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt6795-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-evb.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-rfb1.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-evb.dtb
always := $(dtb-y)
diff --git a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
new file mode 100644
index 0000000..c08309d
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
@@ -0,0 +1,27 @@
+/*
+ * Copyright (c) 2017 MediaTek Inc.
+ * Author: Ming Huang <ming.huang@mediatek.com>
+ * Sean Wang <sean.wang@mediatek.com>
+ *
+ * SPDX-License-Identifier: (GPL-2.0 OR MIT)
+ */
+
+/dts-v1/;
+#include "mt7622.dtsi"
+
+/ {
+ model = "MediaTek MT7622 RFB1 board";
+ compatible = "mediatek,mt7622-rfb1", "mediatek,mt7622";
+
+ chosen {
+ bootargs = "console=ttyS0,115200n1";
+ };
+
+ memory {
+ reg = <0 0x40000000 0 0x3F000000>;
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
--
2.7.4
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH v4 1/2] arm64: dts: mt7622: add basic nodes to the mt7622.dtsi file
2017-06-14 16:11 ` [PATCH v4 1/2] arm64: dts: mt7622: add basic nodes to the mt7622.dtsi file sean.wang
@ 2017-06-15 16:04 ` Matthias Brugger
2017-06-15 17:39 ` Sean Wang
0 siblings, 1 reply; 5+ messages in thread
From: Matthias Brugger @ 2017-06-15 16:04 UTC (permalink / raw)
To: sean.wang, robh+dt, mark.rutland, devicetree, john, linux-mediatek
Cc: linux-arm-kernel, linux-kernel
On 14/06/17 18:11, sean.wang@mediatek.com wrote:
> From: Sean Wang <sean.wang@mediatek.com>
>
> add basic nodes into the mt7622.dtsi for the system
> bring-up which includes ARM CPU, GIC, timer, MediaTek
> UART, SYSIRQ and one reserved memory region for ATF.
>
> Signed-off-by: Sean Wang <sean.wang@mediatek.com>
> ---
> arch/arm64/boot/dts/mediatek/mt7622.dtsi | 104 +++++++++++++++++++++++++++++++
> 1 file changed, 104 insertions(+)
> create mode 100644 arch/arm64/boot/dts/mediatek/mt7622.dtsi
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt7622.dtsi b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
> new file mode 100644
> index 0000000..239b9b3
> --- /dev/null
> +++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
> @@ -0,0 +1,104 @@
> +/*
> + * Copyright (c) 2017 MediaTek Inc.
> + * Author: Ming Huang <ming.huang@mediatek.com>
> + * Sean Wang <sean.wang@mediatek.com>
> + *
> + * SPDX-License-Identifier: (GPL-2.0 OR MIT)
> + */
> +
> +#include <dt-bindings/interrupt-controller/irq.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +/ {
> + compatible = "mediatek,mt7622";
> + interrupt-parent = <&sysirq>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + cpus {
> + #address-cells = <2>;
> + #size-cells = <0>;
> +
> + cpu0: cpu@0 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53", "arm,armv8";
> + reg = <0x0 0x0>;
> + enable-method = "psci";
> + clock-frequency = <1300000000>;
> + };
> +
> + cpu1: cpu@1 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53", "arm,armv8";
> + reg = <0x0 0x1>;
> + enable-method = "psci";
> + clock-frequency = <1300000000>;
> + };
> + };
> +
> + uart_clk: dummy25m {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <25000000>;
> + };
> +
> + psci {
> + compatible = "arm,psci-0.2";
> + method = "smc";
> + };
> +
> + reserved-memory {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + /* 192 KiB reserved for ARM Trusted Firmware (BL31) */
> + secmon_reserved: secmon@43000000 {
> + reg = <0 0x43000000 0 0x30000>;
> + no-map;
> + };
> + };
> +
> + timer {
> + compatible = "arm,armv8-timer";
> + interrupt-parent = <&gic>;
> + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
> + IRQ_TYPE_LEVEL_HIGH)>,
> + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
> + IRQ_TYPE_LEVEL_HIGH)>,
> + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) |
> + IRQ_TYPE_LEVEL_HIGH)>,
> + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
> + IRQ_TYPE_LEVEL_HIGH)>;
> + };
> +
> + sysirq: interrupt-controller@10200620 {
> + compatible = "mediatek,mt7622-sysirq",
> + "mediatek,mt6577-sysirq";
> + interrupt-controller;
> + #interrupt-cells = <3>;
> + interrupt-parent = <&gic>;
> + reg = <0 0x10200620 0 0x20>;
> + };
> +
> + gic: interrupt-controller@10300000 {
> + compatible = "arm,gic-400";
> + interrupt-controller;
> + #interrupt-cells = <3>;
> + interrupt-parent = <&gic>;
> + reg = <0 0x10310000 0 0x1000>,
> + <0 0x10320000 0 0x1000>,
> + <0 0x10340000 0 0x2000>,
> + <0 0x10360000 0 0x2000>;
> + };
> +
> + uart0: serial@11002000 {
> + compatible = "mediatek,mt7622-uart",
> + "mediatek,mt6577-uart";
> + reg = <0 0x11002000 0 0x400>;
> + interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
> + clocks = <&uart_clk>, <&uart_clk>;
Please add a dummy clock node with the correct frequency, as done in
other chips as well.
Thanks,
Matthias
> + clock-names = "baud", "bus";
> + status = "disabled";
> + };
> +};
>
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH v4 1/2] arm64: dts: mt7622: add basic nodes to the mt7622.dtsi file
2017-06-15 16:04 ` Matthias Brugger
@ 2017-06-15 17:39 ` Sean Wang
0 siblings, 0 replies; 5+ messages in thread
From: Sean Wang @ 2017-06-15 17:39 UTC (permalink / raw)
To: Matthias Brugger
Cc: robh+dt, mark.rutland, devicetree, john, linux-mediatek,
linux-arm-kernel, linux-kernel
On Thu, 2017-06-15 at 18:04 +0200, Matthias Brugger wrote:
>
> On 14/06/17 18:11, sean.wang@mediatek.com wrote:
> > From: Sean Wang <sean.wang@mediatek.com>
> >
> > add basic nodes into the mt7622.dtsi for the system
> > bring-up which includes ARM CPU, GIC, timer, MediaTek
> > UART, SYSIRQ and one reserved memory region for ATF.
> >
> > Signed-off-by: Sean Wang <sean.wang@mediatek.com>
> > ---
> > arch/arm64/boot/dts/mediatek/mt7622.dtsi | 104 +++++++++++++++++++++++++++++++
> > 1 file changed, 104 insertions(+)
> > create mode 100644 arch/arm64/boot/dts/mediatek/mt7622.dtsi
> >
> > diff --git a/arch/arm64/boot/dts/mediatek/mt7622.dtsi b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
> > new file mode 100644
> > index 0000000..239b9b3
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
> > @@ -0,0 +1,104 @@
> > +/*
> > + * Copyright (c) 2017 MediaTek Inc.
> > + * Author: Ming Huang <ming.huang@mediatek.com>
> > + * Sean Wang <sean.wang@mediatek.com>
> > + *
> > + * SPDX-License-Identifier: (GPL-2.0 OR MIT)
> > + */
> > +
> > +#include <dt-bindings/interrupt-controller/irq.h>
> > +#include <dt-bindings/interrupt-controller/arm-gic.h>
> > +
> > +/ {
> > + compatible = "mediatek,mt7622";
> > + interrupt-parent = <&sysirq>;
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > +
> > + cpus {
> > + #address-cells = <2>;
> > + #size-cells = <0>;
> > +
> > + cpu0: cpu@0 {
> > + device_type = "cpu";
> > + compatible = "arm,cortex-a53", "arm,armv8";
> > + reg = <0x0 0x0>;
> > + enable-method = "psci";
> > + clock-frequency = <1300000000>;
> > + };
> > +
> > + cpu1: cpu@1 {
> > + device_type = "cpu";
> > + compatible = "arm,cortex-a53", "arm,armv8";
> > + reg = <0x0 0x1>;
> > + enable-method = "psci";
> > + clock-frequency = <1300000000>;
> > + };
> > + };
> > +
> > + uart_clk: dummy25m {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + clock-frequency = <25000000>;
> > + };
> > +
> > + psci {
> > + compatible = "arm,psci-0.2";
> > + method = "smc";
> > + };
> > +
> > + reserved-memory {
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > + ranges;
> > +
> > + /* 192 KiB reserved for ARM Trusted Firmware (BL31) */
> > + secmon_reserved: secmon@43000000 {
> > + reg = <0 0x43000000 0 0x30000>;
> > + no-map;
> > + };
> > + };
> > +
> > + timer {
> > + compatible = "arm,armv8-timer";
> > + interrupt-parent = <&gic>;
> > + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
> > + IRQ_TYPE_LEVEL_HIGH)>,
> > + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
> > + IRQ_TYPE_LEVEL_HIGH)>,
> > + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) |
> > + IRQ_TYPE_LEVEL_HIGH)>,
> > + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
> > + IRQ_TYPE_LEVEL_HIGH)>;
> > + };
> > +
> > + sysirq: interrupt-controller@10200620 {
> > + compatible = "mediatek,mt7622-sysirq",
> > + "mediatek,mt6577-sysirq";
> > + interrupt-controller;
> > + #interrupt-cells = <3>;
> > + interrupt-parent = <&gic>;
> > + reg = <0 0x10200620 0 0x20>;
> > + };
> > +
> > + gic: interrupt-controller@10300000 {
> > + compatible = "arm,gic-400";
> > + interrupt-controller;
> > + #interrupt-cells = <3>;
> > + interrupt-parent = <&gic>;
> > + reg = <0 0x10310000 0 0x1000>,
> > + <0 0x10320000 0 0x1000>,
> > + <0 0x10340000 0 0x2000>,
> > + <0 0x10360000 0 0x2000>;
> > + };
> > +
> > + uart0: serial@11002000 {
> > + compatible = "mediatek,mt7622-uart",
> > + "mediatek,mt6577-uart";
> > + reg = <0 0x11002000 0 0x400>;
> > + interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
> > + clocks = <&uart_clk>, <&uart_clk>;
>
> Please add a dummy clock node with the correct frequency, as done in
> other chips as well.
>
> Thanks,
> Matthias
>
Okay, the uart clock should be 50MHz, and bus clock should be 280MHz
from AXI bus
I will update in the next version .
Sean
> > + clock-names = "baud", "bus";
> > + status = "disabled";
> > + };
> > +};
> >
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2017-06-15 17:39 UTC | newest]
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2017-06-14 16:11 [PATCH v4 0/2] Add Basic SoC support for MT7622 sean.wang
2017-06-14 16:11 ` [PATCH v4 1/2] arm64: dts: mt7622: add basic nodes to the mt7622.dtsi file sean.wang
2017-06-15 16:04 ` Matthias Brugger
2017-06-15 17:39 ` Sean Wang
2017-06-14 16:11 ` [PATCH v4 2/2] arm64: dts: mt7622: add dts file for MT7622 reference board variant 1 sean.wang
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