From: Dilip Kota <eswara.kota@linux.intel.com>
To: broonie@kernel.org, robh@kernel.org, linux-spi@vger.kernel.org,
devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org, daniel.schwierzeck@gmail.com,
hauke@hauke-m.de, andriy.shevchenko@intel.com,
cheol.yong.kim@intel.com, chuanhua.lei@linux.intel.com,
qi-ming.wu@intel.com, Dilip Kota <eswara.kota@linux.intel.com>
Subject: [PATCH 3/4] dt-bindings: spi: Add support to Lightning Mountain SoC
Date: Fri, 24 Apr 2020 18:42:32 +0800 [thread overview]
Message-ID: <1f447a5ab8fee5bc9116ba70b0344193c9c6cc06.1587702428.git.eswara.kota@linux.intel.com> (raw)
In-Reply-To: <cover.1587702428.git.eswara.kota@linux.intel.com>
In-Reply-To: <cover.1587702428.git.eswara.kota@linux.intel.com>
Add support to SPI controller on Intel Atom based Lightning Mountain
SoC which reuses the Lantiq SPI controller IP.
Signed-off-by: Dilip Kota <eswara.kota@linux.intel.com>
---
.../devicetree/bindings/spi/spi-lantiq-ssc.txt | 21 +++++++++++++++++++--
1 file changed, 19 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/spi/spi-lantiq-ssc.txt b/Documentation/devicetree/bindings/spi/spi-lantiq-ssc.txt
index ce3230c8e28d..76a3dd35f796 100644
--- a/Documentation/devicetree/bindings/spi/spi-lantiq-ssc.txt
+++ b/Documentation/devicetree/bindings/spi/spi-lantiq-ssc.txt
@@ -1,11 +1,17 @@
Lantiq Synchronous Serial Controller (SSC) SPI master driver
Required properties:
-- compatible: "lantiq,ase-spi", "lantiq,falcon-spi", "lantiq,xrx100-spi"
+- compatible: "lantiq,ase-spi", "lantiq,falcon-spi", "lantiq,xrx100-spi",
+ "intel,lgm-spi"
- #address-cells: see spi-bus.txt
- #size-cells: see spi-bus.txt
- reg: address and length of the spi master registers
-- interrupts: should contain the "spi_rx", "spi_tx" and "spi_err" interrupt.
+- interrupts:
+ For compatible "intel,lgm-ssc" - the common interrupt number for
+ all of tx rx & err interrupts.
+ or
+ For rest of the compatibles, should contain the "spi_rx", "spi_tx" and
+ "spi_err" interrupt.
Optional properties:
@@ -27,3 +33,14 @@ spi: spi@e100800 {
num-cs = <6>;
base-cs = <1>;
};
+
+ssc0: spi@e0800000 {
+ compatible = "intel,lgm-spi";
+ reg = <0xe0800000 0x400>;
+ interrupt-parent = <&ioapic1>;
+ interrupts = <35 1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&cgu0 LGM_CLK_NGI>, <&cgu0 LGM_GCLK_SSC0>;
+ clock-names = "freq", "gate";
+};
--
2.11.0
next prev parent reply other threads:[~2020-04-24 10:43 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-04-24 10:42 [PATCH 0/4] spi: lantiq: Synchronize interrupts, transfers and add new features Dilip Kota
2020-04-24 10:42 ` [PATCH 1/4] spi: lantiq: Synchronize interrupt handlers and transfers Dilip Kota
2020-04-24 11:25 ` Mark Brown
2020-04-27 6:01 ` Dilip Kota
2020-04-27 13:45 ` Mark Brown
2020-04-28 5:39 ` Dilip Kota
2020-04-28 10:00 ` Mark Brown
2020-04-29 7:20 ` Dilip Kota
2020-04-29 12:27 ` Mark Brown
2020-04-27 21:52 ` Hauke Mehrtens
2020-04-28 6:03 ` Dilip Kota
2020-04-28 11:10 ` Daniel Schwierzeck
2020-04-28 11:30 ` Hauke Mehrtens
2020-04-29 8:22 ` Dilip Kota
2020-04-29 8:20 ` Dilip Kota
2020-04-29 12:13 ` Mark Brown
2020-05-04 10:15 ` Dilip Kota
2020-05-05 11:23 ` Mark Brown
2020-05-06 7:40 ` Dilip Kota
2020-07-16 9:36 ` Dilip Kota
2020-04-24 10:42 ` [PATCH 2/4] spi: lantiq: Dynamic configuration of interrupts and FIFO size Dilip Kota
2020-04-24 10:42 ` Dilip Kota [this message]
2020-05-11 21:22 ` [PATCH 3/4] dt-bindings: spi: Add support to Lightning Mountain SoC Rob Herring
2020-04-24 10:42 ` [PATCH 4/4] spi: lantiq: " Dilip Kota
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