From: Jerome Brunet <jbrunet@baylibre.com>
To: Yu Tu <yu.tu@amlogic.com>,
linux-serial@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
Jiri Slaby <jirislaby@kernel.org>,
Neil Armstrong <narmstrong@baylibre.com>,
Kevin Hilman <khilman@baylibre.com>,
Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Subject: Re: [PATCH V6 4/5] tty: serial: meson: Make some bit of the REG5 register writable
Date: Thu, 20 Jan 2022 22:49:28 +0100 [thread overview]
Message-ID: <1j7dau2hxi.fsf@starbuckisacylon.baylibre.com> (raw)
In-Reply-To: <20220118030911.12815-5-yu.tu@amlogic.com>
On Tue 18 Jan 2022 at 11:09, Yu Tu <yu.tu@amlogic.com> wrote:
> The UART_REG5 register defaults to 0. The console port is set in
> ROMCODE. But other UART ports default to 0, so make bit24 and
> bit[26,27] writable so that the UART can choose a more
> appropriate clock.
Suggestion: Instead of talking bits (which is a bit cryptic) tell us
what is actually does
Something like:
Make the internal clock source mux and divider writeable, allowing the
uart to deviate from the settings intially applied by the ROMCode and
using the most appropriate clocks
>
> Signed-off-by: Yu Tu <yu.tu@amlogic.com>
> ---
> drivers/tty/serial/meson_uart.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/tty/serial/meson_uart.c b/drivers/tty/serial/meson_uart.c
> index 92fa91c825e6..4e7b2b38ab0a 100644
> --- a/drivers/tty/serial/meson_uart.c
> +++ b/drivers/tty/serial/meson_uart.c
> @@ -678,7 +678,7 @@ static int meson_uart_probe_clocks(struct uart_port *port)
> CLK_SET_RATE_NO_REPARENT,
> port->membase + AML_UART_REG5,
> 26, 2,
> - CLK_DIVIDER_READ_ONLY,
> + CLK_DIVIDER_ROUND_CLOSEST,
> xtal_div_table, NULL);
> if (IS_ERR(hw))
> return PTR_ERR(hw);
> @@ -708,7 +708,7 @@ static int meson_uart_probe_clocks(struct uart_port *port)
> CLK_SET_RATE_PARENT,
> port->membase + AML_UART_REG5,
> 24, 0x1,
> - CLK_MUX_READ_ONLY,
> + CLK_MUX_ROUND_CLOSEST,
> NULL, NULL);
> if (IS_ERR(hw))
> return PTR_ERR(hw);
next prev parent reply other threads:[~2022-01-20 21:53 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-01-18 3:09 [PATCH V6 0/5] Use CCF to describe the UART baud rate clock Yu Tu
2022-01-18 3:09 ` [PATCH V6 1/5] tty: serial: meson: Move request the register region to probe Yu Tu
2022-01-18 9:35 ` Jiri Slaby
2022-01-18 3:09 ` [PATCH V6 2/5] tty: serial: meson: Use devm_ioremap_resource to get register mapped memory Yu Tu
2022-01-18 9:36 ` Jiri Slaby
2022-01-18 3:09 ` [PATCH V6 3/5] tty: serial: meson: Describes the calculation of the UART baud rate clock using a clock frame Yu Tu
2022-01-18 9:39 ` Jiri Slaby
2022-01-19 6:00 ` Yu Tu
2022-01-20 21:48 ` Jerome Brunet
2022-02-21 8:26 ` Yu Tu
2022-01-20 21:40 ` Jerome Brunet
2022-01-21 2:51 ` Yu Tu
2022-02-21 8:52 ` Yu Tu
2022-01-18 3:09 ` [PATCH V6 4/5] tty: serial: meson: Make some bit of the REG5 register writable Yu Tu
2022-01-20 21:49 ` Jerome Brunet [this message]
2022-02-21 8:24 ` Yu Tu
2022-01-18 3:09 ` [PATCH V6 5/5] tty: serial: meson: Added S4 SOC compatibility Yu Tu
2022-01-19 22:37 ` [PATCH V6 0/5] Use CCF to describe the UART baud rate clock Kevin Hilman
2022-01-20 8:43 ` Yu Tu
2022-01-24 19:58 ` Kevin Hilman
2022-02-07 14:19 ` Yu Tu
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