[PATCH][2.5][RFT] sfence wmb for K7,P3,VIAC3-2(?)

[PATCH][2.5][RFT] sfence wmb for K7,P3,VIAC3-2(?)

[Zwane Mwaikambo]

Stress tested on 8way PIII 700, Dave, does the C3 have sfence?

Index: linux-2.5.66/arch/i386/Kconfig
===================================================================
RCS file: /build/cvsroot/linux-2.5.66/arch/i386/Kconfig,v
retrieving revision 1.1.1.1
diff -u -p -B -r1.1.1.1 Kconfig
--- linux-2.5.66/arch/i386/Kconfig	24 Mar 2003 23:40:26 -0000	1.1.1.1
+++ linux-2.5.66/arch/i386/Kconfig	1 Apr 2003 08:04:42 -0000
@@ -368,6 +368,11 @@ config X86_PREFETCH
 	depends on MPENTIUMIII || MPENTIUM4 || MVIAC3_2
 	default y
 
+config X86_SSE
+	bool
+	depends on MK7 || MPENTIUMIII || MVIAC3_2
+	default y
+
 config X86_SSE2
 	bool
 	depends on MK8 || MPENTIUM4
Index: linux-2.5.66/include/asm-i386/system.h
===================================================================
RCS file: /build/cvsroot/linux-2.5.66/include/asm-i386/system.h,v
retrieving revision 1.1.1.1
diff -u -p -B -r1.1.1.1 system.h
--- linux-2.5.66/include/asm-i386/system.h	24 Mar 2003 23:40:20 -0000	1.1.1.1
+++ linux-2.5.66/include/asm-i386/system.h	1 Apr 2003 05:39:00 -0000
@@ -355,11 +355,15 @@ static inline unsigned long __cmpxchg(vo
 
 #define read_barrier_depends()	do { } while(0)
 
+#ifdef CONFIG_X86_SSE
+#define wmb()	__asm__ __volatile__ ("sfence;": : :"memory")
+#else
 #ifdef CONFIG_X86_OOSTORE
 #define wmb() 	__asm__ __volatile__ ("lock; addl $0,0(%%esp)": : :"memory")
 #else
 #define wmb()	__asm__ __volatile__ ("": : :"memory")
 #endif
+#endif /* CONFIG_X86_SSE */
 
 #ifdef CONFIG_SMP
 #define smp_mb()	mb()

Re: [PATCH][2.5][RFT] sfence wmb for K7,P3,VIAC3-2(?)

[Zwane Mwaikambo]

On Tue, 1 Apr 2003, Zwane Mwaikambo wrote:

> +config X86_SSE
> +	bool
> +	depends on MK7 || MPENTIUMIII || MVIAC3_2
> +	default y
> +

Bad option to flag against as pointed out by someone, seeing as K7 
implimented half the SSE instructions.

urgh...

-- 
function.linuxpower.ca

Re: [PATCH][2.5][RFT] sfence wmb for K7,P3,VIAC3-2(?)

[Andi Kleen]

On Tue, 2003-04-01 at 10:22, Zwane Mwaikambo wrote:
> On Tue, 1 Apr 2003, Zwane Mwaikambo wrote:
> 
> > +config X86_SSE
> > +	bool
> > +	depends on MK7 || MPENTIUMIII || MVIAC3_2
> > +	default y
> > +
> 
> Bad option to flag against as pointed out by someone, seeing as K7 
> implimented half the SSE instructions.

SSE2 != SSE1. K7 has SSE1, like the Pentium 3.

X86_SSE is SSE1

sfence is part of SSE2. That's X86_SSE2

-Andi

Re: [PATCH][2.5][RFT] sfence wmb for K7,P3,VIAC3-2(?)

[Dave Jones]

On Tue, Apr 01, 2003 at 12:11:00PM +0200, Andi Kleen wrote:
 > sfence is part of SSE2. That's X86_SSE2

I'm not so sure this is correct. A quick google suggests
otherwise, and the C3 Nehemiah (which only supports SSE1) seems
to run sfence instructions just fine.

		Dave

Re: [PATCH][2.5][RFT] sfence wmb for K7,P3,VIAC3-2(?)

[Andi Kleen]

On Tue, 2003-04-01 at 13:28, Dave Jones wrote:
> On Tue, Apr 01, 2003 at 12:11:00PM +0200, Andi Kleen wrote:
>  > sfence is part of SSE2. That's X86_SSE2
> 
> I'm not so sure this is correct. A quick google suggests
> otherwise, and the C3 Nehemiah (which only supports SSE1) seems
> to run sfence instructions just fine.

Yes, you're correct. It was SSE1, not SSE2.

The problem Zwane encountered is that early Athlons don't support SSE1,
only XP+ do

To use it he would need an a new CONFIG split for Athlon XP and earlier
Athlon. iirc it didn't make much difference on the athlon anyways which
has quite fast locked operations on exclusive cachelines - sfence seems
to be more useful on P4.

-Andi

Re: [PATCH][2.5][RFT] sfence wmb for K7,P3,VIAC3-2(?)

[Zwane Mwaikambo]

On Tue, 1 Apr 2003, Andi Kleen wrote:

> Yes, you're correct. It was SSE1, not SSE2.
> 
> The problem Zwane encountered is that early Athlons don't support SSE1,
> only XP+ do

hmm wouldn't they illegal op? Some tested this on an Athlon 600.

> To use it he would need an a new CONFIG split for Athlon XP and earlier
> Athlon. iirc it didn't make much difference on the athlon anyways which
> has quite fast locked operations on exclusive cachelines - sfence seems
> to be more useful on P4.

How about this instead then;

Index: linux-2.5.66/arch/i386/Kconfig
===================================================================
RCS file: /build/cvsroot/linux-2.5.66/arch/i386/Kconfig,v
retrieving revision 1.1.1.1
diff -u -p -B -r1.1.1.1 Kconfig
--- linux-2.5.66/arch/i386/Kconfig	24 Mar 2003 23:40:26 -0000	1.1.1.1
+++ linux-2.5.66/arch/i386/Kconfig	1 Apr 2003 16:02:46 -0000
@@ -368,6 +368,11 @@ config X86_PREFETCH
 	depends on MPENTIUMIII || MPENTIUM4 || MVIAC3_2
 	default y
 
+config X86_USE_SFENCE
+	bool
+	depends on MPENTIUM4
+	default y
+
 config X86_SSE2
 	bool
 	depends on MK8 || MPENTIUM4
Index: linux-2.5.66/include/asm-i386/system.h
===================================================================
RCS file: /build/cvsroot/linux-2.5.66/include/asm-i386/system.h,v
retrieving revision 1.1.1.1
diff -u -p -B -r1.1.1.1 system.h
--- linux-2.5.66/include/asm-i386/system.h	24 Mar 2003 23:40:20 -0000	1.1.1.1
+++ linux-2.5.66/include/asm-i386/system.h	1 Apr 2003 16:03:50 -0000
@@ -355,11 +355,15 @@ static inline unsigned long __cmpxchg(vo
 
 #define read_barrier_depends()	do { } while(0)
 
+#ifdef CONFIG_X86_USE_SFENCE
+#define wmb()	__asm__ __volatile__ ("sfence;": : :"memory")
+#else
 #ifdef CONFIG_X86_OOSTORE
 #define wmb() 	__asm__ __volatile__ ("lock; addl $0,0(%%esp)": : :"memory")
 #else
 #define wmb()	__asm__ __volatile__ ("": : :"memory")
 #endif
+#endif /* CONFIG_USE_SFENCE */
 
 #ifdef CONFIG_SMP
 #define smp_mb()	mb()

-- 
function.linuxpower.ca

Re: [PATCH][2.5][RFT] sfence wmb for K7,P3,VIAC3-2(?)

[Dave Jones]

On Tue, Apr 01, 2003 at 11:07:21AM -0500, Zwane Mwaikambo wrote:

 > > Yes, you're correct. It was SSE1, not SSE2.
 > > The problem Zwane encountered is that early Athlons don't support SSE1,
 > > only XP+ do
 > 
 > hmm wouldn't they illegal op? Some tested this on an Athlon 600.

I'm not 100% sure on this, but I *think* 3dnow had an sfence which was
opcode compatable with SSE's instruction.
 
		Dave

Re: [PATCH][2.5][RFT] sfence wmb for K7,P3,VIAC3-2(?)

[Daniel Egger]

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Am Die, 2003-04-01 um 18.26 schrieb Dave Jones:

> I'm not 100% sure on this, but I *think* 3dnow had an sfence which was
> opcode compatable with SSE's instruction.

At best the enhanced 3dnow had it. I couldn't find it in the regular
3dnow "technology manual" and don't know where I put the darn other
one....

-- 
Servus,
       Daniel

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Re: [PATCH][2.5][RFT] sfence wmb for K7,P3,VIAC3-2(?)

[Dave Jones]

On Tue, Apr 01, 2003 at 08:31:01PM +0200, Daniel Egger wrote:

 > > I'm not 100% sure on this, but I *think* 3dnow had an sfence which was
 > > opcode compatable with SSE's instruction.
 > At best the enhanced 3dnow had it. I couldn't find it in the regular
 > 3dnow "technology manual" and don't know where I put the darn other
 > one....

Even the early athlons had 3dnowext, so this is a mystery solved afiacs

		Dave