Re: top stack (l)users for 2.5.69

From: Chuck Ebbert <76306.1226@compuserve.com>
To: Jvrn Engel <joern@wohnheim.fh-wedel.de>
Cc: linux-kernel <linux-kernel@vger.kernel.org>
Subject: Re: top stack (l)users for 2.5.69
Date: Thu, 8 May 2003 10:08:36 -0400	[thread overview]
Message-ID: <200305081009_MC3-1-37FA-2407@compuserve.com> (raw)

> I have no idea, what a 'typical processor' might look like. But the
> thing most CPU seem to have in common is that they save two registers
> either on the stack or into other registers that only exist for this
> purpose (SRR on PPC).
>
> Once that has happened, the OS has the job to figure out where it's
> stack (or equivalent) is located, *without* clobbering the registers.
> Once that is done, it can save all the registern on the stack,
> including SRR.

  On i386 the CPU automatically switches to the stack corresponding to
the privilege level (PL) of the interrupt handler, then pushes the
instruction pointer and flags onto that stack.  It is theoretically
possible to write unprivileged interrupt handlers by using conforming
code segments, in which case a stack switch will not occur, but such a
handler cannot touch anything but registers and stack so it's not very
useful.