* Re: [PATCH] remove IO APIC newline
2003-06-27 18:41 ` [PATCH] remove IO APIC newline Jeff Garzik
@ 2003-06-27 18:57 ` Diego Calleja García
2003-07-01 6:03 ` Martin Schlemmer
0 siblings, 1 reply; 5+ messages in thread
From: Diego Calleja García @ 2003-06-27 18:57 UTC (permalink / raw)
To: Jeff Garzik; +Cc: linux-kernel
[-- Attachment #1: Type: text/plain, Size: 2686 bytes --]
On Fri, 27 Jun 2003 14:41:11 -0400
Jeff Garzik <jgarzik@pobox.com> wrote:
> Personally the IO-APIC gunk is gunk that should be hidden behind
> DPRINTK... SMP machines spam dmesg _way_ too much. Especially once you
> get above 4 processors.
I did a patch wich makes dmesg output of SMP machines better. Well, it doesn't
adds or removes any line; but it says "CPUX:". The patch ugly, basically
it adds smp_processor_id() output in every printk i found. I did it because
IMHO messages like "Intel machine check architecture supported" in a SMP machine
are ugly. I'd found it specially nice for big SMP boxes because this does dmesg
easily grep'able.
-Initializing CPU#0
+CPU0: Initializing
[...]
-Calibrating delay loop... 1602.35 BogoMIPS
+CPU0: Calibrating delay loop... 1602.35 BogoMIPS
[...]
-CPU: L1 I cache: 16K, L1 D cache: 16K
-CPU: L2 cache: 256K
-CPU: After generic, caps: 0383fbff 00000000 00000000 00000040
-Intel machine check architecture supported.
-Intel machine check reporting enabled on CPU#0.
-Enabling fast FPU save and restore... done.
-Enabling unmasked SIMD FPU exception support... done.
-Checking 'hlt' instruction... OK.
+CPU0: L1 I cache: 16K, L1 D cache: 16K
+CPU0: L2 cache: 256K
+CPU0: After generic, caps: 0383fbff 00000000 00000000 00000040
+CPU0: Intel machine check architecture supported.
+CPU0: Intel machine check reporting enabled.
+CPU0: Enabling fast FPU save and restore... done.
+CPU0: Enabling unmasked SIMD FPU exception support... done.
+CPU0: Checking 'hlt' instruction... OK.
[...]
-enabled ExtINT on CPU#0
-ESR value before enabling vector: 00000000
-ESR value after enabling vector: 00000000
+CPU0: enabled ExtINT.
+CPU0: ESR value before enabling vector: 00000000
+CPU0: ESR value after enabling vector: 00000000
[...]
-Initializing CPU#1
-masked ExtINT on CPU#1
-ESR value before enabling vector: 00000000
-ESR value after enabling vector: 00000000
-Calibrating delay loop... 1605.63 BogoMIPS
-CPU: L1 I cache: 16K, L1 D cache: 16K
-CPU: L2 cache: 256K
-CPU: After generic, caps: 0383fbff 00000000 00000000 00000040
-Intel machine check architecture supported.
-Intel machine check reporting enabled on CPU#1.
+CPU1: Initializing
+CPU1: masked ExtINT.
+CPU1: ESR value before enabling vector: 00000000
+CPU1: ESR value after enabling vector: 00000000
+CPU1: Calibrating delay loop... 1605.63 BogoMIPS
+CPU1: L1 I cache: 16K, L1 D cache: 16K
+CPU1: L2 cache: 256K
+CPU1: After generic, caps: 0383fbff 00000000 00000000 00000040
+CPU1: Intel machine check architecture supported.
+CPU1: Intel machine check reporting enabled.
[...]
-Enabling SEP on CPU 1
-Enabling SEP on CPU 0
+CPU1: Enabling SEP
+CPU0: Enabling SEP
[-- Attachment #2: dmesg-cleanup.patch --]
[-- Type: application/octet-stream, Size: 29654 bytes --]
diff -Nur unsta/arch/i386/kernel/apic.c unsta.moo/arch/i386/kernel/apic.c
--- unsta/arch/i386/kernel/apic.c 2003-06-24 20:54:21.000000000 +0200
+++ unsta.moo/arch/i386/kernel/apic.c 2003-06-26 17:31:49.000000000 +0200
@@ -408,10 +408,10 @@
value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
if (!smp_processor_id() && (pic_mode || !value)) {
value = APIC_DM_EXTINT;
- printk("enabled ExtINT on CPU#%d\n", smp_processor_id());
+ printk("CPU%d: enabled ExtINT.\n", smp_processor_id());
} else {
value = APIC_DM_EXTINT | APIC_LVT_MASKED;
- printk("masked ExtINT on CPU#%d\n", smp_processor_id());
+ printk("CPU%d: masked ExtINT.\n", smp_processor_id());
}
apic_write_around(APIC_LVT0, value);
@@ -431,7 +431,8 @@
if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
apic_write(APIC_ESR, 0);
value = apic_read(APIC_ESR);
- printk("ESR value before enabling vector: %08lx\n", value);
+ printk("CPU%d: ESR value before enabling vector: %08lx\n",
+ smp_processor_id(), value);
value = ERROR_APIC_VECTOR; // enables sending errors
apic_write_around(APIC_LVTERR, value);
@@ -441,7 +442,8 @@
if (maxlvt > 3)
apic_write(APIC_ESR, 0);
value = apic_read(APIC_ESR);
- printk("ESR value after enabling vector: %08lx\n", value);
+ printk("CPU%d: ESR value after enabling vector: %08lx\n",
+ smp_processor_id(), value);
} else {
if (esr_disable)
/*
@@ -450,9 +452,9 @@
* ESR disabled - we can't do anything useful with the
* errors anyway - mbligh
*/
- printk("Leaving ESR disabled.\n");
+ printk("CPU%d: Leaving ESR disabled.\n", smp_processor_id());
else
- printk("No ESR for 82489DX.\n");
+ printk("CPU%d: No ESR for 82489DX.\n", smp_processor_id());
}
if (nmi_watchdog == NMI_LOCAL_APIC)
diff -Nur unsta/arch/i386/kernel/cpu/amd.c unsta.moo/arch/i386/kernel/cpu/amd.c
--- unsta/arch/i386/kernel/cpu/amd.c 2003-05-05 21:00:02.000000000 +0200
+++ unsta.moo/arch/i386/kernel/cpu/amd.c 2003-06-26 17:11:44.000000000 +0200
@@ -74,7 +74,7 @@
void (*f_vide)(void);
unsigned long d, d2;
- printk(KERN_INFO "AMD K6 stepping B detected - ");
+ printk(KERN_INFO "CPU%d: AMD K6 stepping B detected - ", smp_processor_id());
/*
* It looks like AMD fixed the 2.6.2 bug and improved indirect
@@ -90,7 +90,7 @@
d = d2-d;
/* Knock these two lines out if it debugs out ok */
- printk(KERN_INFO "AMD K6 stepping B detected - ");
+ printk(KERN_INFO "CPU%d: AMD K6 stepping B detected - ", smp_processor_id());
/* -- cut here -- */
if (d > 20*K6_BUG_LOOP)
printk("system stability may be impaired when more than 32 MB are used.\n");
@@ -114,8 +114,8 @@
wbinvd();
wrmsr(MSR_K6_WHCR, l, h);
local_irq_restore(flags);
- printk(KERN_INFO "Enabling old style K6 write allocation for %d Mb\n",
- mbytes);
+ printk(KERN_INFO "CPU%d: Enabling old style K6 write allocation for %d Mb\n",
+ smp_processor_id(), mbytes);
}
break;
}
@@ -135,8 +135,8 @@
wbinvd();
wrmsr(MSR_K6_WHCR, l, h);
local_irq_restore(flags);
- printk(KERN_INFO "Enabling new style K6 write allocation for %d Mb\n",
- mbytes);
+ printk(KERN_INFO "CPU%d: Enabling new style K6 write allocation for %d Mb\n",
+ smp_processor_id(), mbytes);
}
/* Set MTRR capability flag if appropriate */
@@ -155,7 +155,8 @@
*/
if (c->x86_model >= 6 && c->x86_model <= 10) {
if (!cpu_has(c, X86_FEATURE_XMM)) {
- printk(KERN_INFO "Enabling disabled K7/SSE Support.\n");
+ printk(KERN_INFO "CPU%d: Enabling disabled K7/SSE Support.\n",
+ smp_processor_id());
rdmsr(MSR_K7_HWCR, l, h);
l &= ~0x00008000;
wrmsr(MSR_K7_HWCR, l, h);
@@ -170,8 +171,8 @@
if ((c->x86_model == 8 && c->x86_mask>=1) || (c->x86_model > 8)) {
rdmsr(MSR_K7_CLK_CTL, l, h);
if ((l & 0xfff00000) != 0x20000000) {
- printk ("CPU: CLK_CTL MSR was %x. Reprogramming to %x\n", l,
- ((l & 0x000fffff)|0x20000000));
+ printk ("CPU%d: CLK_CTL MSR was %x. Reprogramming to %x\n",
+ smp_processor_id(), l, ((l & 0x000fffff)|0x20000000));
wrmsr(MSR_K7_CLK_CTL, (l & 0x000fffff)|0x20000000, h);
}
}
diff -Nur unsta/arch/i386/kernel/cpu/centaur.c unsta.moo/arch/i386/kernel/cpu/centaur.c
--- unsta/arch/i386/kernel/cpu/centaur.c 2003-03-18 19:01:35.000000000 +0100
+++ unsta.moo/arch/i386/kernel/cpu/centaur.c 2003-06-26 16:55:33.000000000 +0200
@@ -1,6 +1,7 @@
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/bitops.h>
+#include <linux/smp.h>
#include <asm/processor.h>
#include <asm/msr.h>
#include <asm/e820.h>
@@ -320,7 +321,7 @@
name="C6";
fcr_set=ECX8|DSMC|EDCTLB|EMMX|ERETSTK;
fcr_clr=DPDC;
- printk(KERN_NOTICE "Disabling bugged TSC.\n");
+ printk(KERN_NOTICE "CPU%d: Disabling bugged TSC.\n", smp_processor_id());
clear_bit(X86_FEATURE_TSC, c->x86_capability);
#ifdef CONFIG_X86_OOSTORE
centaur_create_optimal_mcr();
@@ -394,10 +395,12 @@
newlo=(lo|fcr_set) & (~fcr_clr);
if (newlo!=lo) {
- printk(KERN_INFO "Centaur FCR was 0x%X now 0x%X\n", lo, newlo );
+ printk(KERN_INFO "CPU%d: Centaur FCR was 0x%X now 0x%X\n",
+ smp_processor_id(), lo, newlo );
wrmsr(MSR_IDT_FCR1, newlo, hi );
} else {
- printk(KERN_INFO "Centaur FCR is 0x%X\n",lo);
+ printk(KERN_INFO "CPU%d: Centaur FCR is 0x%X\n",
+ smp_processor_id(), lo);
}
/* Emulate MTRRs using Centaur's MCR. */
set_bit(X86_FEATURE_CENTAUR_MCR, c->x86_capability);
diff -Nur unsta/arch/i386/kernel/cpu/common.c unsta.moo/arch/i386/kernel/cpu/common.c
--- unsta/arch/i386/kernel/cpu/common.c 2003-06-25 17:09:13.000000000 +0200
+++ unsta.moo/arch/i386/kernel/cpu/common.c 2003-06-26 17:28:38.000000000 +0200
@@ -83,8 +83,8 @@
if (n >= 0x80000005) {
cpuid(0x80000005, &dummy, &dummy, &ecx, &edx);
- printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n",
- edx>>24, edx&0xFF, ecx>>24, ecx&0xFF);
+ printk(KERN_INFO "CPU%d: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n",
+ smp_processor_id(), edx>>24, edx&0xFF, ecx>>24, ecx&0xFF);
c->x86_cache_size=(ecx>>24)+(edx>>24);
}
@@ -107,8 +107,8 @@
c->x86_cache_size = l2size;
- printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n",
- l2size, ecx & 0xFF);
+ printk(KERN_INFO "CPU%d: L2 Cache: %dK (%d bytes/line)\n",
+ smp_processor_id(), l2size, ecx & 0xFF);
}
/* Naming convention should be: <Name> [(<Codename>)] */
@@ -246,7 +246,7 @@
rdmsr(MSR_IA32_BBL_CR_CTL,lo,hi);
lo |= 0x200000;
wrmsr(MSR_IA32_BBL_CR_CTL,lo,hi);
- printk(KERN_NOTICE "CPU serial number disabled.\n");
+ printk(KERN_NOTICE "CPU%d: serial number disabled.\n", smp_processor_id());
clear_bit(X86_FEATURE_PN, c->x86_capability);
/* Disabling the serial number may affect the cpuid level */
@@ -341,7 +341,8 @@
/* Now the feature flags better reflect actual CPU features! */
- printk(KERN_DEBUG "CPU: After generic, caps: %08lx %08lx %08lx %08lx\n",
+ printk(KERN_DEBUG "CPU%d: After generic, caps: %08lx %08lx %08lx %08lx\n",
+ smp_processor_id(),
c->x86_capability[0],
c->x86_capability[1],
c->x86_capability[2],
@@ -452,15 +453,15 @@
struct thread_struct *thread = ¤t->thread;
if (test_and_set_bit(cpu, &cpu_initialized)) {
- printk(KERN_WARNING "CPU#%d already initialized!\n", cpu);
+ printk(KERN_WARNING "CPU%d: already initialized!\n", cpu);
for (;;) local_irq_enable();
}
- printk(KERN_INFO "Initializing CPU#%d\n", cpu);
+ printk(KERN_INFO "CPU%d: Initializing\n", cpu);
if (cpu_has_vme || cpu_has_tsc || cpu_has_de)
clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
if (tsc_disable && cpu_has_tsc) {
- printk(KERN_NOTICE "Disabling TSC...\n");
+ printk(KERN_NOTICE "CPU%d: Disabling TSC...\n", cpu);
/**** FIX-HPA: DOES THIS REALLY BELONG HERE? ****/
clear_bit(X86_FEATURE_TSC, boot_cpu_data.x86_capability);
set_in_cr4(X86_CR4_TSD);
diff -Nur unsta/arch/i386/kernel/cpu/cyrix.c unsta.moo/arch/i386/kernel/cpu/cyrix.c
--- unsta/arch/i386/kernel/cpu/cyrix.c 2003-06-26 16:22:38.000000000 +0200
+++ unsta.moo/arch/i386/kernel/cpu/cyrix.c 2003-06-26 16:23:06.000000000 +0200
@@ -99,7 +99,8 @@
local_irq_restore(flags);
if (ccr5 & 2) { /* possible wrong calibration done */
- printk(KERN_INFO "Recalibrating delay loop with SLOP bit reset\n");
+ printk(KERN_INFO "CPU%d: Recalibrating delay loop with SLOP bit reset\n",
+ smp_processor_id());
calibrate_delay();
c->loops_per_jiffy = loops_per_jiffy;
}
@@ -112,7 +113,8 @@
#ifdef CONFIG_OOSTORE
u8 ccr3;
- printk(KERN_INFO "Enable Memory access reorder on Cyrix/NSC processor.\n");
+ printk(KERN_INFO "CPU%d: Enable Memory access reorder on Cyrix/NSC processor.\n",
+ smp_processor_id());
ccr3 = getCx86(CX86_CCR3);
setCx86(CX86_CCR3, (ccr3 & 0x0f) | 0x10); /* enable MAPEN */
@@ -267,7 +269,8 @@
VSA1 we work around however.
*/
- printk(KERN_INFO "Working around Cyrix MediaGX virtual DMA bugs.\n");
+ printk(KERN_INFO "CPU%d: Working around Cyrix MediaGX virtual DMA bugs.\n",
+ smp_processor_id());
isa_dma_bridge_buggy = 2;
#endif
c->x86_cache_size=16; /* Yep 16K integrated cache thats it */
Los ficheros binarios unsta/arch/i386/kernel/cpu/.cyrix.c.swp y unsta.moo/arch/i386/kernel/cpu/.cyrix.c.swp son distintos
diff -Nur unsta/arch/i386/kernel/cpu/intel.c unsta.moo/arch/i386/kernel/cpu/intel.c
--- unsta/arch/i386/kernel/cpu/intel.c 2003-06-26 16:22:38.000000000 +0200
+++ unsta.moo/arch/i386/kernel/cpu/intel.c 2003-06-26 16:55:57.000000000 +0200
@@ -61,10 +61,11 @@
if((ident&15) < 8)
{
- printk(KERN_INFO "Pentium Pro with Errata#50 detected. Taking evasive action.\n");
+ printk(KERN_INFO "CPU%d: Pentium Pro with Errata#50 detected. Taking evasive action.\n",
+ smp_processor_id());
return 1;
}
- printk(KERN_INFO "Your Pentium Pro seems ok.\n");
+ printk(KERN_INFO "CPU%d: Your Pentium Pro seems ok.\n", smp_processor_id());
return 0;
}
@@ -139,8 +140,10 @@
if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_mask == 1)) {
rdmsr (MSR_IA32_MISC_ENABLE, lo, hi);
if ((lo & (1<<9)) == 0) {
- printk (KERN_INFO "CPU: C0 stepping P4 Xeon detected.\n");
- printk (KERN_INFO "CPU: Disabling hardware prefetching (Errata 037)\n");
+ printk (KERN_INFO "CPU%d: C0 stepping P4 Xeon detected.\n",
+ smp_processor_id());
+ printk (KERN_INFO "CPU%d: Disabling hardware prefetching (Errata 037)\n",
+ smp_processor_id());
lo |= (1<<9); /* Disable hw prefetching */
wrmsr (MSR_IA32_MISC_ENABLE, lo, hi);
}
@@ -166,7 +169,8 @@
c->f00f_bug = 1;
if ( !f00f_workaround_enabled ) {
trap_init_f00f_bug();
- printk(KERN_NOTICE "Intel Pentium with F0 0F bug - workaround enabled.\n");
+ printk(KERN_NOTICE "CPU%d: Intel Pentium with F0 0F bug - workaround enabled.\n",
+ smp_processor_id());
f00f_workaround_enabled = 1;
}
}
@@ -226,15 +230,16 @@
}
if ( trace )
- printk (KERN_INFO "CPU: Trace cache: %dK uops", trace);
+ printk (KERN_INFO "CPU%d: Trace cache: %dK uops",
+ smp_processor_id(), trace);
else if ( l1i )
- printk (KERN_INFO "CPU: L1 I cache: %dK", l1i);
+ printk (KERN_INFO "CPU%d: L1 I cache: %dK", smp_processor_id(), l1i);
if ( l1d )
printk(", L1 D cache: %dK\n", l1d);
if ( l2 )
- printk(KERN_INFO "CPU: L2 cache: %dK\n", l2);
+ printk(KERN_INFO "CPU%d: L2 cache: %dK\n", smp_processor_id(), l2);
if ( l3 )
- printk(KERN_INFO "CPU: L3 cache: %dK\n", l3);
+ printk(KERN_INFO "CPU%d: L3 cache: %dK\n", smp_processor_id(), l3);
/*
* This assumes the L3 cache is shared; it typically lives in
@@ -293,7 +298,7 @@
smp_num_siblings = (ebx & 0xff0000) >> 16;
if (smp_num_siblings == 1) {
- printk(KERN_INFO "CPU: Hyper-Threading is disabled\n");
+ printk(KERN_INFO "CPU%d: Hyper-Threading is disabled\n", cpu);
} else if (smp_num_siblings > 1 ) {
index_lsb = 0;
index_msb = 31;
@@ -303,7 +308,8 @@
*/
#define NR_SIBLINGS 2
if (smp_num_siblings != NR_SIBLINGS) {
- printk(KERN_WARNING "CPU: Unsupported number of the siblings %d", smp_num_siblings);
+ printk(KERN_WARNING "CPU%d: Unsupported number of the siblings %d",
+ cpu, smp_num_siblings);
smp_num_siblings = 1;
goto too_many_siblings;
}
@@ -322,8 +328,8 @@
initial_apic_id = ebx >> 24 & 0xff;
phys_proc_id[cpu] = initial_apic_id >> index_msb;
- printk(KERN_INFO "CPU: Physical Processor ID: %d\n",
- phys_proc_id[cpu]);
+ printk(KERN_INFO "CPU%d: Physical Processor ID: %d\n",
+ cpu, phys_proc_id[cpu]);
}
}
diff -Nur unsta/arch/i386/kernel/cpu/mcheck/k7.c unsta.moo/arch/i386/kernel/cpu/mcheck/k7.c
--- unsta/arch/i386/kernel/cpu/mcheck/k7.c 2003-05-05 21:00:02.000000000 +0200
+++ unsta.moo/arch/i386/kernel/cpu/mcheck/k7.c 2003-06-26 17:13:25.000000000 +0200
@@ -28,7 +28,7 @@
if (mcgstl & (1<<0)) /* Recoverable ? */
recover=0;
- printk (KERN_EMERG "CPU %d: Machine Check Exception: %08x%08x\n",
+ printk (KERN_EMERG "CPU%d: Machine Check Exception: %08x%08x\n",
smp_processor_id(), mcgsth, mcgstl);
for (i=0; i<nr_mce_banks; i++) {
@@ -38,7 +38,8 @@
recover |= 1;
if (high & (1<<25))
recover |= 2;
- printk (KERN_EMERG "Bank %d: %08x%08x", i, high, low);
+ printk (KERN_EMERG "CPU%d: Bank %d: %08x%08x",
+ smp_processor_id(), i, high, low);
high &= ~(1<<31);
if (high & (1<<27)) {
rdmsr (MSR_IA32_MC0_MISC+i*4, alow, ahigh);
@@ -57,7 +58,7 @@
}
if (recover&2)
- panic ("CPU context corrupt");
+ panic ("CPU%d: context corrupt", smp_processor_id());
if (recover&1)
panic ("Unable to continue");
printk (KERN_EMERG "Attempting to continue.\n");
@@ -75,7 +76,8 @@
machine_check_vector = k7_machine_check;
wmb();
- printk (KERN_INFO "Intel machine check architecture supported.\n");
+ printk (KERN_INFO "CPU%d: Intel machine check architecture supported.\n",
+ smp_processor_id());
rdmsr (MSR_IA32_MCG_CAP, l, h);
if (l & (1<<8)) /* Control register present ? */
wrmsr (MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff);
@@ -87,6 +89,6 @@
}
set_in_cr4 (X86_CR4_MCE);
- printk (KERN_INFO "Intel machine check reporting enabled on CPU#%d.\n",
+ printk (KERN_INFO "CPU%d: Intel machine check reporting enabled.\n",
smp_processor_id());
}
diff -Nur unsta/arch/i386/kernel/cpu/mcheck/mce.c unsta.moo/arch/i386/kernel/cpu/mcheck/mce.c
--- unsta/arch/i386/kernel/cpu/mcheck/mce.c 2002-12-16 03:08:14.000000000 +0100
+++ unsta.moo/arch/i386/kernel/cpu/mcheck/mce.c 2003-06-26 16:39:10.000000000 +0200
@@ -20,7 +20,8 @@
/* Handle unconfigured int18 (should never happen) */
static void unexpected_machine_check(struct pt_regs * regs, long error_code)
{
- printk(KERN_ERR "CPU#%d: Unexpected int18 (Machine Check).\n", smp_processor_id());
+ printk(KERN_ERR "CPU%d: Unexpected int18 (Machine Check).\n",
+ smp_processor_id());
}
/* Call the installed machine check handler for this CPU setup. */
diff -Nur unsta/arch/i386/kernel/cpu/mcheck/non-fatal.c unsta.moo/arch/i386/kernel/cpu/mcheck/non-fatal.c
--- unsta/arch/i386/kernel/cpu/mcheck/non-fatal.c 2003-04-20 13:00:18.000000000 +0200
+++ unsta.moo/arch/i386/kernel/cpu/mcheck/non-fatal.c 2003-06-26 16:39:27.000000000 +0200
@@ -34,9 +34,10 @@
rdmsr (MSR_IA32_MC0_STATUS+i*4, low, high);
if (high & (1<<31)) {
- printk (KERN_EMERG "MCE: The hardware reports a non fatal, correctable incident occurred on CPU %d.\n",
+ printk (KERN_EMERG "CPU%d: Correctable incident; MCE: The hardware reports a non fatal.\n",
smp_processor_id());
- printk (KERN_EMERG "Bank %d: %08x%08x\n", i, high, low);
+ printk (KERN_EMERG "CPU%d: Bank %d: %08x%08x\n",
+ smp_processor_id(), i, high, low);
/* Scrub the error so we don't pick it up in MCE_RATE seconds time. */
wrmsr (MSR_IA32_MC0_STATUS+i*4, 0UL, 0UL);
@@ -77,7 +78,8 @@
mce_timer.function = &mce_timerfunc;
add_timer (&mce_timer);
timerset = 1;
- printk(KERN_INFO "Machine check exception polling timer started.\n");
+ printk(KERN_INFO "CPU%d: Machine check exception polling timer started.\n",
+ smp_processor_id());
}
return 0;
}
diff -Nur unsta/arch/i386/kernel/cpu/mcheck/p4.c unsta.moo/arch/i386/kernel/cpu/mcheck/p4.c
--- unsta/arch/i386/kernel/cpu/mcheck/p4.c 2003-04-20 13:00:18.000000000 +0200
+++ unsta.moo/arch/i386/kernel/cpu/mcheck/p4.c 2003-06-26 16:57:15.000000000 +0200
@@ -38,7 +38,7 @@
#ifdef CONFIG_X86_MCE_P4THERMAL
static void unexpected_thermal_interrupt(struct pt_regs *regs)
{
- printk(KERN_ERR "CPU#%d: Unexpected LVT TMR interrupt!\n", smp_processor_id());
+ printk(KERN_ERR "CPU%d: Unexpected LVT TMR interrupt!\n", smp_processor_id());
}
/* P4/Xeon Thermal transition interrupt handler */
@@ -51,10 +51,10 @@
rdmsr (MSR_IA32_THERM_STATUS, l, h);
if (l & 1) {
- printk(KERN_EMERG "CPU#%d: Temperature above threshold\n", cpu);
- printk(KERN_EMERG "CPU#%d: Running in modulated clock mode\n", cpu);
+ printk(KERN_EMERG "CPU%d: Temperature above threshold\n", cpu);
+ printk(KERN_EMERG "CPU%d: Running in modulated clock mode\n", cpu);
} else {
- printk(KERN_INFO "CPU#%d: Temperature/speed normal\n", cpu);
+ printk(KERN_INFO "CPU%d: Temperature/speed normal\n", cpu);
}
}
@@ -89,13 +89,13 @@
rdmsr (MSR_IA32_MISC_ENABLE, l, h);
h = apic_read(APIC_LVTTHMR);
if ((l & (1<<3)) && (h & APIC_DM_SMI)) {
- printk(KERN_DEBUG "CPU#%d: Thermal monitoring handled by SMI\n", cpu);
+ printk(KERN_DEBUG "CPU%d: Thermal monitoring handled by SMI\n", cpu);
return; /* -EBUSY */
}
/* check whether a vector already exists, temporarily masked? */
if (h & APIC_VECTOR_MASK) {
- printk(KERN_DEBUG "CPU#%d: Thermal LVT vector (%#x) already installed\n",
+ printk(KERN_DEBUG "CPU%d: Thermal LVT vector (%#x) already installed\n",
cpu, (h & APIC_VECTOR_MASK));
return; /* -EBUSY */
}
@@ -116,7 +116,7 @@
l = apic_read (APIC_LVTTHMR);
apic_write_around (APIC_LVTTHMR, l & ~APIC_LVT_MASKED);
- printk (KERN_INFO "CPU#%d: Thermal monitoring enabled\n", cpu);
+ printk (KERN_INFO "CPU%d: Thermal monitoring enabled\n", cpu);
return;
}
#endif /* CONFIG_X86_MCE_P4THERMAL */
@@ -160,7 +160,7 @@
if (mcgstl & (1<<0)) /* Recoverable ? */
recover=0;
- printk (KERN_EMERG "CPU %d: Machine Check Exception: %08x%08x\n",
+ printk (KERN_EMERG "CPU%d: Machine Check Exception: %08x%08x\n",
smp_processor_id(), mcgsth, mcgstl);
if (intel_get_extended_msrs(&dbg)) {
@@ -179,7 +179,8 @@
recover |= 1;
if (high & (1<<25))
recover |= 2;
- printk (KERN_EMERG "Bank %d: %08x%08x", i, high, low);
+ printk (KERN_EMERG "CPU%d: Bank %d: %08x%08x",
+ smp_processor_id(), i, high, low);
high &= ~(1<<31);
if (high & (1<<27)) {
rdmsr (MSR_IA32_MC0_MISC+i*4, alow, ahigh);
@@ -194,11 +195,11 @@
}
if (recover & 2)
- panic ("CPU context corrupt");
+ panic ("CPU%d: Context corrupt", smp_processor_id());
if (recover & 1)
- panic ("Unable to continue");
+ panic ("CPU%d: Unable to continue", smp_processor_id());
- printk(KERN_EMERG "Attempting to continue.\n");
+ printk(KERN_EMERG "CPU%d: Attempting to continue.\n", smp_processor_id());
/*
* Do not clear the MSR_IA32_MCi_STATUS if the error is not
* recoverable/continuable.This will allow BIOS to look at the MSRs
@@ -228,7 +229,8 @@
machine_check_vector = intel_machine_check;
wmb();
- printk (KERN_INFO "Intel machine check architecture supported.\n");
+ printk (KERN_INFO "CPU%d: Intel machine check architecture supported.\n",
+ smp_processor_id());
rdmsr (MSR_IA32_MCG_CAP, l, h);
if (l & (1<<8)) /* Control register present ? */
wrmsr (MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff);
@@ -240,7 +242,7 @@
}
set_in_cr4 (X86_CR4_MCE);
- printk (KERN_INFO "Intel machine check reporting enabled on CPU#%d.\n",
+ printk (KERN_INFO "CPU%d: Intel machine check reporting enabled.\n",
smp_processor_id());
/* Check for P4/Xeon extended MCE MSRs */
diff -Nur unsta/arch/i386/kernel/cpu/mcheck/p5.c unsta.moo/arch/i386/kernel/cpu/mcheck/p5.c
--- unsta/arch/i386/kernel/cpu/mcheck/p5.c 2002-12-16 03:08:11.000000000 +0100
+++ unsta.moo/arch/i386/kernel/cpu/mcheck/p5.c 2003-06-26 16:43:20.000000000 +0200
@@ -21,9 +21,11 @@
u32 loaddr, hi, lotype;
rdmsr(MSR_IA32_P5_MC_ADDR, loaddr, hi);
rdmsr(MSR_IA32_P5_MC_TYPE, lotype, hi);
- printk(KERN_EMERG "CPU#%d: Machine Check Exception: 0x%8X (type 0x%8X).\n", smp_processor_id(), loaddr, lotype);
+ printk(KERN_EMERG "CPU%d: Machine Check Exception: 0x%8X (type 0x%8X).\n",
+ smp_processor_id(), loaddr, lotype);
if(lotype&(1<<5))
- printk(KERN_EMERG "CPU#%d: Possible thermal failure (CPU on fire ?).\n", smp_processor_id());
+ printk(KERN_EMERG "CPU%d: Possible thermal failure (CPU on fire ?).\n",
+ smp_processor_id());
}
/* Set up machine check reporting for processors with Intel style MCE */
@@ -44,9 +46,11 @@
/* Read registers before enabling */
rdmsr(MSR_IA32_P5_MC_ADDR, l, h);
rdmsr(MSR_IA32_P5_MC_TYPE, l, h);
- printk(KERN_INFO "Intel old style machine check architecture supported.\n");
+ printk(KERN_INFO "CPU%d: Intel old style machine check architecture supported.\n",
+ smp_processor_id());
/* Enable MCE */
set_in_cr4(X86_CR4_MCE);
- printk(KERN_INFO "Intel old style machine check reporting enabled on CPU#%d.\n", smp_processor_id());
+ printk(KERN_INFO "CPU%d: Intel old style machine check reporting enabled.\n",
+ smp_processor_id());
}
diff -Nur unsta/arch/i386/kernel/cpu/mcheck/p6.c unsta.moo/arch/i386/kernel/cpu/mcheck/p6.c
--- unsta/arch/i386/kernel/cpu/mcheck/p6.c 2003-06-25 16:51:25.000000000 +0200
+++ unsta.moo/arch/i386/kernel/cpu/mcheck/p6.c 2003-06-26 16:45:57.000000000 +0200
@@ -27,7 +27,7 @@
if (mcgstl & (1<<0)) /* Recoverable ? */
recover=0;
- printk (KERN_EMERG "CPU %d: Machine Check Exception: %08x%08x\n",
+ printk (KERN_EMERG "CPU%d: Machine Check Exception: %08x%08x\n",
smp_processor_id(), mcgsth, mcgstl);
for (i=0; i<nr_mce_banks; i++) {
@@ -37,7 +37,8 @@
recover |= 1;
if (high & (1<<25))
recover |= 2;
- printk (KERN_EMERG "Bank %d: %08x%08x", i, high, low);
+ printk (KERN_EMERG "CPU%d: Bank %d: %08x%08x",
+ smp_processor_id(), i, high, low);
high &= ~(1<<31);
if (high & (1<<27)) {
rdmsr (MSR_IA32_MC0_MISC+i*4, alow, ahigh);
@@ -52,11 +53,11 @@
}
if (recover & 2)
- panic ("CPU context corrupt");
+ panic ("CPU%d: Context corrupt", smp_processor_id());
if (recover & 1)
- panic ("Unable to continue");
+ panic ("CPU%d: Unable to continue", smp_processor_id());
- printk (KERN_EMERG "Attempting to continue.\n");
+ printk (KERN_EMERG "CPU%d: Attempting to continue.\n", smp_processor_id());
/*
* Do not clear the MSR_IA32_MCi_STATUS if the error is not
* recoverable/continuable.This will allow BIOS to look at the MSRs
@@ -95,7 +96,8 @@
machine_check_vector = intel_machine_check;
wmb();
- printk (KERN_INFO "Intel machine check architecture supported.\n");
+ printk (KERN_INFO "CPU%d: Intel machine check architecture supported.\n",
+ smp_processor_id());
rdmsr (MSR_IA32_MCG_CAP, l, h);
if (l & (1<<8)) /* Control register present ? */
wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff);
@@ -108,6 +110,6 @@
}
set_in_cr4 (X86_CR4_MCE);
- printk (KERN_INFO "Intel machine check reporting enabled on CPU#%d.\n",
+ printk (KERN_INFO "CPU%d: Intel machine check reporting enabled.\n",
smp_processor_id());
}
diff -Nur unsta/arch/i386/kernel/cpu/mcheck/winchip.c unsta.moo/arch/i386/kernel/cpu/mcheck/winchip.c
--- unsta/arch/i386/kernel/cpu/mcheck/winchip.c 2002-12-16 03:07:59.000000000 +0100
+++ unsta.moo/arch/i386/kernel/cpu/mcheck/winchip.c 2003-06-26 16:47:40.000000000 +0200
@@ -17,7 +17,8 @@
/* Machine check handler for WinChip C6 */
static void winchip_machine_check(struct pt_regs * regs, long error_code)
{
- printk(KERN_EMERG "CPU0: Machine Check Exception.\n");
+ printk(KERN_EMERG "CPU%d: Machine Check Exception.\n",
+ smp_processor_id());
}
/* Set up machine check reporting on the Winchip C6 series */
@@ -31,5 +32,6 @@
lo&= ~(1<<4); /* Enable MCE */
wrmsr(MSR_IDT_FCR1, lo, hi);
set_in_cr4(X86_CR4_MCE);
- printk(KERN_INFO "Winchip machine check reporting enabled on CPU#0.\n");
+ printk(KERN_INFO "CPU%d: Winchip machine check reporting enabled.\n",
+ smp_processor_id());
}
diff -Nur unsta/arch/i386/kernel/cpu/rise.c unsta.moo/arch/i386/kernel/cpu/rise.c
--- unsta/arch/i386/kernel/cpu/rise.c 2002-12-16 03:07:48.000000000 +0100
+++ unsta.moo/arch/i386/kernel/cpu/rise.c 2003-06-26 16:56:20.000000000 +0200
@@ -1,13 +1,14 @@
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/bitops.h>
+#include <linux/smp.h>
#include <asm/processor.h>
#include "cpu.h"
static void __init init_rise(struct cpuinfo_x86 *c)
{
- printk("CPU: Rise iDragon");
+ printk("CPU%d: Rise iDragon", smp_processor_id());
if (c->x86_model > 2)
printk(" II");
printk("\n");
diff -Nur unsta/arch/i386/kernel/cpu/transmeta.c unsta.moo/arch/i386/kernel/cpu/transmeta.c
--- unsta/arch/i386/kernel/cpu/transmeta.c 2002-12-16 03:07:46.000000000 +0100
+++ unsta.moo/arch/i386/kernel/cpu/transmeta.c 2003-06-26 17:10:54.000000000 +0200
@@ -1,5 +1,6 @@
#include <linux/kernel.h>
#include <linux/init.h>
+#include <linux/smp.h>
#include <asm/processor.h>
#include <asm/msr.h>
#include "cpu.h"
@@ -18,7 +19,8 @@
max = cpuid_eax(0x80860000);
if ( max >= 0x80860001 ) {
cpuid(0x80860001, &dummy, &cpu_rev, &cpu_freq, &cpu_flags);
- printk(KERN_INFO "CPU: Processor revision %u.%u.%u.%u, %u MHz\n",
+ printk(KERN_INFO "CPU%d: Processor revision %u.%u.%u.%u, %u MHz\n",
+ smp_processor_id(),
(cpu_rev >> 24) & 0xff,
(cpu_rev >> 16) & 0xff,
(cpu_rev >> 8) & 0xff,
@@ -27,7 +29,8 @@
}
if ( max >= 0x80860002 ) {
cpuid(0x80860002, &dummy, &cms_rev1, &cms_rev2, &dummy);
- printk(KERN_INFO "CPU: Code Morphing Software revision %u.%u.%u-%u-%u\n",
+ printk(KERN_INFO "CPU%d: Code Morphing Software revision %u.%u.%u-%u-%u\n",
+ smp_processor_id(),
(cms_rev1 >> 24) & 0xff,
(cms_rev1 >> 16) & 0xff,
(cms_rev1 >> 8) & 0xff,
@@ -56,7 +59,7 @@
(void *)&cpu_info[56],
(void *)&cpu_info[60]);
cpu_info[64] = '\0';
- printk(KERN_INFO "CPU: %s\n", cpu_info);
+ printk(KERN_INFO "CPU%d: %s\n", smp_processor_id(), cpu_info);
}
/* Unhide possibly hidden capability flags */
diff -Nur unsta/arch/i386/kernel/io_apic.c unsta.moo/arch/i386/kernel/io_apic.c
--- unsta/arch/i386/kernel/io_apic.c 2003-06-24 20:54:21.000000000 +0200
+++ unsta.moo/arch/i386/kernel/io_apic.c 2003-06-26 17:49:23.000000000 +0200
@@ -1298,7 +1298,6 @@
*(int *)®_02 = io_apic_read(apic, 2);
spin_unlock_irqrestore(&ioapic_lock, flags);
- printk("\n");
printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
printk(KERN_DEBUG ".... register #00: %08X\n", *(int *)®_00);
printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.ID);
diff -Nur unsta/arch/i386/kernel/sysenter.c unsta.moo/arch/i386/kernel/sysenter.c
--- unsta/arch/i386/kernel/sysenter.c 2003-05-27 21:03:16.000000000 +0200
+++ unsta.moo/arch/i386/kernel/sysenter.c 2003-06-26 17:24:44.000000000 +0200
@@ -32,7 +32,7 @@
wrmsr(MSR_IA32_SYSENTER_ESP, tss->esp1, 0);
wrmsr(MSR_IA32_SYSENTER_EIP, (unsigned long) sysenter_entry, 0);
- printk("Enabling SEP on CPU %d\n", cpu);
+ printk("CPU%d: Enabling SEP\n", cpu);
put_cpu();
}
diff -Nur unsta/include/asm-i386/bugs.h unsta.moo/include/asm-i386/bugs.h
--- unsta/include/asm-i386/bugs.h 2003-06-25 17:40:52.000000000 +0200
+++ unsta.moo/include/asm-i386/bugs.h 2003-06-26 17:18:57.000000000 +0200
@@ -98,12 +98,14 @@
__buggy_fxsr_alignment();
}
if (cpu_has_fxsr) {
- printk(KERN_INFO "Enabling fast FPU save and restore... ");
+ printk(KERN_INFO "CPU%d: Enabling fast FPU save and restore... ",
+ smp_processor_id());
set_in_cr4(X86_CR4_OSFXSR);
printk("done.\n");
}
if (cpu_has_xmm) {
- printk(KERN_INFO "Enabling unmasked SIMD FPU exception support... ");
+ printk(KERN_INFO "CPU%d: Enabling unmasked SIMD FPU exception support... ",
+ smp_processor_id());
set_in_cr4(X86_CR4_OSXMMEXCPT);
printk("done.\n");
}
@@ -126,7 +128,7 @@
static void __init check_hlt(void)
{
- printk(KERN_INFO "Checking 'hlt' instruction... ");
+ printk(KERN_INFO "CPU%d: Checking 'hlt' instruction... ", smp_processor_id());
if (!boot_cpu_data.hlt_works_ok) {
printk("disabled\n");
return;
@@ -145,7 +147,7 @@
#ifndef CONFIG_X86_POPAD_OK
int res, inp = (int) &res;
- printk(KERN_INFO "Checking for popad bug... ");
+ printk(KERN_INFO "CPU%d: Checking for popad bug... ", smp_processor_id());
__asm__ __volatile__(
"movl $12345678,%%eax; movl $0,%%edi; pusha; popa; movl (%%edx,%%edi),%%ecx "
: "=&a" (res)
diff -Nur unsta/init/main.c unsta.moo/init/main.c
--- unsta/init/main.c 2003-06-24 20:54:35.000000000 +0200
+++ unsta.moo/init/main.c 2003-06-26 17:38:09.000000000 +0200
@@ -38,6 +38,7 @@
#include <linux/moduleparam.h>
#include <linux/writeback.h>
#include <linux/cpu.h>
+#include <linux/smp.h>
#include <asm/io.h>
#include <asm/bugs.h>
@@ -194,7 +195,7 @@
loops_per_jiffy = (1<<12);
- printk("Calibrating delay loop... ");
+ printk("CPU%d: Calibrating delay loop... ", smp_processor_id());
while (loops_per_jiffy <<= 1) {
/* wait for "start of" clock tick */
ticks = jiffies;
^ permalink raw reply [flat|nested] 5+ messages in thread