* CPU boot problem on 2.6.0-test3-bk8
@ 2003-08-20 21:58 Andrew Theurer
2003-08-21 1:02 ` Dave Hansen
0 siblings, 1 reply; 19+ messages in thread
From: Andrew Theurer @ 2003-08-20 21:58 UTC (permalink / raw)
To: linux-kernel
[-- Attachment #1: Type: text/plain, Size: 424 bytes --]
Maybe this is already known, but just in case:
I cannot fully boot on an x440 system with 2.6.0-test3-bk8. The kernel tries
to boot more than the 16 logical processors, and after failing (no response)
on cpus 16, 17, and 18, it still thinks it has 19 cpus total. It finally
gets stuck at "checking TSC synchronization across 19 CPUs:"
Attached is the boot log. Any ideas? I'll try -test3-bk7 next
-Andrew Theurer
[-- Attachment #2: 260-test3-bk8 --]
[-- Type: text/plain, Size: 20088 bytes --]
root (hd0,0)
Filesystem type is ext2fs, partition type 0x83
kernel /bzImage-2.6.0-test3 ro root=/dev/sda7 console=ttyS0,38400n8
[Linux-bzImage, setup=0xc00, size=0x1fc885]
Linux version 2.6.0-test3-bk8 (root@x4408way2) (gcc version 3.2.2) #1 SMP Wed Aug 20 17:43:34 CDT 2003
Video mode to be used for restore is ffff
BIOS-provided physical RAM map:
BIOS-e820: 0000000000000000 - 000000000009dc00 (usable)
BIOS-e820: 000000000009dc00 - 00000000000a0000 (reserved)
BIOS-e820: 00000000000e0000 - 0000000000100000 (reserved)
BIOS-e820: 0000000000100000 - 00000000dffb6ec0 (usable)
BIOS-e820: 00000000dffb6ec0 - 00000000dffbf800 (ACPI data)
BIOS-e820: 00000000dffbf800 - 00000000e0000000 (reserved)
BIOS-e820: 00000000fec00000 - 0000000100000000 (reserved)
BIOS-e820: 0000000100000000 - 0000000320000000 (usable)
get_memcfg_from_srat: assigning address to rsdp
RSD PTR v0 [IBM ]
Begin table scan....
CPU 0x00 in proximity domain 0x00
CPU 0x02 in proximity domain 0x00
CPU 0x10 in proximity domain 0x00
CPU 0x12 in proximity domain 0x00
CPU 0x20 in proximity domain 0x01
CPU 0x22 in proximity domain 0x01
CPU 0x30 in proximity domain 0x01
CPU 0x32 in proximity domain 0x01
CPU 0x01 in proximity domain 0x00
CPU 0x03 in proximity domain 0x00
CPU 0x11 in proximity domain 0x00
CPU 0x13 in proximity domain 0x00
CPU 0x21 in proximity domain 0x01
CPU 0x23 in proximity domain 0x01
CPU 0x31 in proximity domain 0x01
CPU 0x33 in proximity domain 0x01
Memory range 0x0 to 0xE0000 (type 0x1) in proximity domain 0x00 enabled
Memory range 0x100000 to 0x220000 (type 0x1) in proximity domain 0x00 enabled
Memory range 0x220000 to 0x320000 (type 0x1) in proximity domain 0x01 enabled
acpi20_parse_srat: Entry length value is zero; can't parse any further!
pxm bitmap: 03 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
Number of logical nodes in system = 2
Number of memory chunks in system = 3
chunk 0 nid 0 start_pfn 00000000 end_pfn 000e0000
chunk 1 nid 0 start_pfn 00100000 end_pfn 00220000
chunk 2 nid 1 start_pfn 00220000 end_pfn 00320000
Reserving 11776 pages of KVA for lmem_map of node 1
Shrinking node 1 from 3276800 pages to 3265024 pages
Reserving total of 11776 pages for numa KVA remap
11904MB HIGHMEM available.
850MB LOWMEM available.
min_low_pfn = 1445, max_low_pfn = 217600, highstart_pfn = 229376
Low memory ends at vaddr f5200000
node 0 will remap to vaddr f8000000 - f8000000
node 1 will remap to vaddr f5200000 - f8000000
High memory starts at vaddr f8000000
ACPI: S3 and PAE do not like each other for now, S3 disabled.
found SMP MP-table at 0009dd40
hm, page 0009d000 reserved twice.
hm, page 0009e000 reserved twice.
hm, page 0009e000 reserved twice.
hm, page 0009f000 reserved twice.
On node 0 totalpages: 2097152
DMA zone: 4096 pages, LIFO batch:1
Normal zone: 213504 pages, LIFO batch:16
HighMem zone: 1879552 pages, LIFO batch:16
BUG: wrong zone alignment, it will crash
On node 1 totalpages: 1036800
DMA zone: 0 pages, LIFO batch:1
Normal zone: 0 pages, LIFO batch:1
HighMem zone: 1036800 pages, LIFO batch:16
DMI 2.3 present.
IBM machine detected. Enabling interrupts during APM calls.
IBM machine detected. Disabling SMBus accesses.
IBM eserver xSeries 440 detected: force use of acpi=ht
ACPI: RSDP (v000 IBM ) @ 0x000fdba0
ACPI: RSDT (v001 IBM SERVIGIL 0x00001000 IBM 0x45444f43) @ 0xdffbf780
ACPI: FADT (v001 IBM SERVIGIL 0x00001000 IBM 0x45444f43) @ 0xdffbf700
ACPI: MADT (v001 IBM SERVIGIL 0x00001000 IBM 0x45444f43) @ 0xdffbf580
ACPI: SRAT (v001 IBM SERVIGIL 0x00001000 IBM 0x45444f43) @ 0xdffbf3c0
ACPI: DSDT (v001 IBM SERVIGIL 0x00001000 INTL 0x02002025) @ 0x00000000
ACPI: Local APIC address 0xfee00000
ACPI: LAPIC (acpi_id[0x00] lapic_id[0x00] enabled)
Processor #0 15:1 APIC version 20
ACPI: LAPIC (acpi_id[0x01] lapic_id[0x02] enabled)
Processor #2 15:1 APIC version 20
ACPI: LAPIC (acpi_id[0x02] lapic_id[0x10] enabled)
Processor #16 15:1 APIC version 20
ACPI: LAPIC (acpi_id[0x03] lapic_id[0x12] enabled)
Processor #18 15:1 APIC version 20
ACPI: LAPIC (acpi_id[0x04] lapic_id[0x20] enabled)
Processor #32 15:1 APIC version 20
ACPI: LAPIC (acpi_id[0x05] lapic_id[0x22] enabled)
Processor #34 15:1 APIC version 20
ACPI: LAPIC (acpi_id[0x06] lapic_id[0x30] enabled)
Processor #48 15:1 APIC version 20
ACPI: LAPIC (acpi_id[0x07] lapic_id[0x32] enabled)
Processor #50 15:1 APIC version 20
ACPI: LAPIC (acpi_id[0x08] lapic_id[0x01] enabled)
Processor #1 15:1 APIC version 20
ACPI: LAPIC (acpi_id[0x09] lapic_id[0x03] enabled)
Processor #3 15:1 APIC version 20
ACPI: LAPIC (acpi_id[0x0a] lapic_id[0x11] enabled)
Processor #17 15:1 APIC version 20
ACPI: LAPIC (acpi_id[0x0b] lapic_id[0x13] enabled)
Processor #19 15:1 APIC version 20
ACPI: LAPIC (acpi_id[0x0c] lapic_id[0x21] enabled)
Processor #33 15:1 APIC version 20
ACPI: LAPIC (acpi_id[0x0d] lapic_id[0x23] enabled)
Processor #35 15:1 APIC version 20
ACPI: LAPIC (acpi_id[0x0e] lapic_id[0x31] enabled)
Processor #49 15:1 APIC version 20
ACPI: LAPIC (acpi_id[0x0f] lapic_id[0x33] enabled)
Processor #51 15:1 APIC version 20
ACPI: LAPIC_NMI (acpi_id[0x00] polarity[0x0] trigger[0x0] lint[0x1])
ACPI: LAPIC_NMI (acpi_id[0x01] polarity[0x0] trigger[0x0] lint[0x1])
ACPI: LAPIC_NMI (acpi_id[0x02] polarity[0x0] trigger[0x0] lint[0x1])
ACPI: LAPIC_NMI (acpi_id[0x03] polarity[0x0] trigger[0x0] lint[0x1])
ACPI: LAPIC_NMI (acpi_id[0x04] polarity[0x0] trigger[0x0] lint[0x1])
ACPI: LAPIC_NMI (acpi_id[0x05] polarity[0x0] trigger[0x0] lint[0x1])
ACPI: LAPIC_NMI (acpi_id[0x06] polarity[0x0] trigger[0x0] lint[0x1])
ACPI: LAPIC_NMI (acpi_id[0x07] polarity[0x0] trigger[0x0] lint[0x1])
ACPI: LAPIC_NMI (acpi_id[0x08] polarity[0x0] trigger[0x0] lint[0x1])
ACPI: LAPIC_NMI (acpi_id[0x09] polarity[0x0] trigger[0x0] lint[0x1])
ACPI: LAPIC_NMI (acpi_id[0x0a] polarity[0x0] trigger[0x0] lint[0x1])
ACPI: LAPIC_NMI (acpi_id[0x0b] polarity[0x0] trigger[0x0] lint[0x1])
ACPI: LAPIC_NMI (acpi_id[0x0c] polarity[0x0] trigger[0x0] lint[0x1])
ACPI: LAPIC_NMI (acpi_id[0x0d] polarity[0x0] trigger[0x0] lint[0x1])
ACPI: LAPIC_NMI (acpi_id[0x0e] polarity[0x0] trigger[0x0] lint[0x1])
ACPI: LAPIC_NMI (acpi_id[0x0f] polarity[0x0] trigger[0x0] lint[0x1])
Using ACPI for processor (LAPIC) configuration information
Intel MultiProcessor Specification v1.4
Virtual Wire compatibility mode.
OEM ID: IBM ENSW Product ID: VIGIL SMP APIC at: 0xFEE00000
I/O APIC #14 Version 17 at 0xFEC00000.
I/O APIC #13 Version 17 at 0xFEC01000.
Enabling APIC mode: Summit. Using 2 I/O APICs
Processors: 16
Building zonelist for node : 0
Building zonelist for node : 1
Kernel command line: ro root=/dev/sda7 console=ttyS0,38400n8
Initializing CPU#0
PID hash table entries: 4096 (order 12: 32768 bytes)
Summit chipset: Starting Cyclone Counter.
Detected 1498.568 MHz processor.
Console: colour VGA+ 80x25
Calibrating delay loop... 193.02 BogoMIPS
Initializing highpages for node 0
Initializing highpages for node 1
Memory: 12431384k/13107200k available (3113k kernel code, 102620k reserved, 1120k data, 204k init, 11665112k highmem)
Dentry cache hash table entries: 1048576 (order: 10, 4194304 bytes)
Inode-cache hash table entries: 1048576 (order: 10, 4194304 bytes)
Mount-cache hash table entries: 512 (order: 0, 4096 bytes)
-> /dev
-> /dev/console
-> /root
CPU: Trace cache: 12K uops, L1 D cache: 8K
CPU: L2 cache: 256K
CPU: L3 cache: 512K
CPU: Physical Processor ID: 0
Intel machine check architecture supported.
Intel machine check reporting enabled on CPU#0.
CPU#0: Intel P4/Xeon Extended MCE MSRs (12) available
CPU#0: Thermal monitoring enabled
Enabling fast FPU save and restore... done.
Enabling unmasked SIMD FPU exception support... done.
Checking 'hlt' instruction... OK.
POSIX conformance testing by UNIFIX
CPU0: Intel(R) Genuine CPU 1.50GHz stepping 01
per-CPU timeslice cutoff: 731.48 usecs.
task migration cache decay timeout: 1 msecs.
enabled ExtINT on CPU#0
Leaving ESR disabled.
Mapping cpu 0 to node 0
Booting processor 1/2 eip 2000
Initializing CPU#1
masked ExtINT on CPU#1
Leaving ESR disabled.
Mapping cpu 1 to node 0
Calibrating delay loop... 199.16 BogoMIPS
CPU: Trace cache: 12K uops, L1 D cache: 8K
CPU: L2 cache: 256K
CPU: L3 cache: 512K
CPU: Physical Processor ID: 1
Intel machine check architecture supported.
Intel machine check reporting enabled on CPU#1.
CPU#1: Intel P4/Xeon Extended MCE MSRs (12) available
CPU#1: Thermal monitoring enabled
CPU1: Intel(R) Xeon(TM) CPU 1.50GHz stepping 01
Booting processor 2/16 eip 2000
Initializing CPU#2
masked ExtINT on CPU#2
Leaving ESR disabled.
Mapping cpu 2 to node 0
Calibrating delay loop... 199.16 BogoMIPS
CPU: Trace cache: 12K uops, L1 D cache: 8K
CPU: L2 cache: 256K
CPU: L3 cache: 512K
CPU: Physical Processor ID: 2
Intel machine check architecture supported.
Intel machine check reporting enabled on CPU#2.
CPU#2: Intel P4/Xeon Extended MCE MSRs (12) available
CPU#2: Thermal monitoring enabled
CPU2: Intel(R) Xeon(TM) CPU 1.50GHz stepping 01
Booting processor 3/18 eip 2000
Initializing CPU#3
masked ExtINT on CPU#3
Leaving ESR disabled.
Mapping cpu 3 to node 0
Calibrating delay loop... 199.16 BogoMIPS
CPU: Trace cache: 12K uops, L1 D cache: 8K
CPU: L2 cache: 256K
CPU: L3 cache: 512K
CPU: Physical Processor ID: 3
Intel machine check architecture supported.
Intel machine check reporting enabled on CPU#3.
CPU#3: Intel P4/Xeon Extended MCE MSRs (12) available
CPU#3: Thermal monitoring enabled
CPU3: Intel(R) Xeon(TM) CPU 1.50GHz stepping 01
Booting processor 4/32 eip 2000
Initializing CPU#4
masked ExtINT on CPU#4
Leaving ESR disabled.
Mapping cpu 4 to node 1
Calibrating delay loop... 198.65 BogoMIPS
CPU: Trace cache: 12K uops, L1 D cache: 8K
CPU: L2 cache: 256K
CPU: L3 cache: 512K
CPU: Physical Processor ID: 8
Intel machine check architecture supported.
Intel machine check reporting enabled on CPU#4.
CPU#4: Intel P4/Xeon Extended MCE MSRs (12) available
CPU#4: Thermal monitoring enabled
CPU4: Intel(R) Genuine CPU 1.50GHz stepping 01
Booting processor 5/34 eip 2000
Initializing CPU#5
masked ExtINT on CPU#5
Leaving ESR disabled.
Mapping cpu 5 to node 1
Calibrating delay loop... 199.16 BogoMIPS
CPU: Trace cache: 12K uops, L1 D cache: 8K
CPU: L2 cache: 256K
CPU: L3 cache: 512K
CPU: Physical Processor ID: 9
Intel machine check architecture supported.
Intel machine check reporting enabled on CPU#5.
CPU#5: Intel P4/Xeon Extended MCE MSRs (12) available
CPU#5: Thermal monitoring enabled
CPU5: Intel(R) Xeon(TM) CPU 1.50GHz stepping 01
Booting processor 6/48 eip 2000
Initializing CPU#6
masked ExtINT on CPU#6
Leaving ESR disabled.
Mapping cpu 6 to node 1
Calibrating delay loop... 199.16 BogoMIPS
CPU: Trace cache: 12K uops, L1 D cache: 8K
CPU: L2 cache: 256K
CPU: L3 cache: 512K
CPU: Physical Processor ID: 10
Intel machine check architecture supported.
Intel machine check reporting enabled on CPU#6.
CPU#6: Intel P4/Xeon Extended MCE MSRs (12) available
CPU#6: Thermal monitoring enabled
CPU6: Intel(R) Xeon(TM) CPU 1.50GHz stepping 01
Booting processor 7/50 eip 2000
Initializing CPU#7
masked ExtINT on CPU#7
Leaving ESR disabled.
Mapping cpu 7 to node 1
Calibrating delay loop... 198.65 BogoMIPS
CPU: Trace cache: 12K uops, L1 D cache: 8K
CPU: L2 cache: 256K
CPU: L3 cache: 512K
CPU: Physical Processor ID: 11
Intel machine check architecture supported.
Intel machine check reporting enabled on CPU#7.
CPU#7: Intel P4/Xeon Extended MCE MSRs (12) available
CPU#7: Thermal monitoring enabled
CPU7: Intel(R) Xeon(TM) CPU 1.50GHz stepping 01
Booting processor 8/1 eip 2000
Initializing CPU#8
masked ExtINT on CPU#8
Leaving ESR disabled.
Mapping cpu 8 to node 0
Calibrating delay loop... 199.16 BogoMIPS
CPU: Trace cache: 12K uops, L1 D cache: 8K
CPU: L2 cache: 256K
CPU: L3 cache: 512K
CPU: Physical Processor ID: 0
Intel machine check architecture supported.
Intel machine check reporting enabled on CPU#8.
CPU#8: Intel P4/Xeon Extended MCE MSRs (12) available
CPU#8: Thermal monitoring enabled
CPU8: Intel(R) Genuine CPU 1.50GHz stepping 01
Booting processor 9/3 eip 2000
Initializing CPU#9
masked ExtINT on CPU#9
Leaving ESR disabled.
Mapping cpu 9 to node 0
Calibrating delay loop... 199.16 BogoMIPS
CPU: Trace cache: 12K uops, L1 D cache: 8K
CPU: L2 cache: 256K
CPU: L3 cache: 512K
CPU: Physical Processor ID: 1
Intel machine check architecture supported.
Intel machine check reporting enabled on CPU#9.
CPU#9: Intel P4/Xeon Extended MCE MSRs (12) available
CPU#9: Thermal monitoring enabled
CPU9: Intel(R) Xeon(TM) CPU 1.50GHz stepping 01
Booting processor 10/17 eip 2000
Initializing CPU#10
masked ExtINT on CPU#10
Leaving ESR disabled.
Mapping cpu 10 to node 0
Calibrating delay loop... 199.16 BogoMIPS
CPU: Trace cache: 12K uops, L1 D cache: 8K
CPU: L2 cache: 256K
CPU: L3 cache: 512K
CPU: Physical Processor ID: 2
Intel machine check architecture supported.
Intel machine check reporting enabled on CPU#10.
CPU#10: Intel P4/Xeon Extended MCE MSRs (12) available
CPU#10: Thermal monitoring enabled
CPU10: Intel(R) Xeon(TM) CPU 1.50GHz stepping 01
Booting processor 11/19 eip 2000
Initializing CPU#11
masked ExtINT on CPU#11
Leaving ESR disabled.
Mapping cpu 11 to node 0
Calibrating delay loop... 199.16 BogoMIPS
CPU: Trace cache: 12K uops, L1 D cache: 8K
CPU: L2 cache: 256K
CPU: L3 cache: 512K
CPU: Physical Processor ID: 3
Intel machine check architecture supported.
Intel machine check reporting enabled on CPU#11.
CPU#11: Intel P4/Xeon Extended MCE MSRs (12) available
CPU#11: Thermal monitoring enabled
CPU11: Intel(R) Xeon(TM) CPU 1.50GHz stepping 01
Booting processor 12/33 eip 2000
Initializing CPU#12
masked ExtINT on CPU#12
Leaving ESR disabled.
Mapping cpu 12 to node 1
Calibrating delay loop... 199.16 BogoMIPS
CPU: Trace cache: 12K uops, L1 D cache: 8K
CPU: L2 cache: 256K
CPU: L3 cache: 512K
CPU: Physical Processor ID: 8
Intel machine check architecture supported.
Intel machine check reporting enabled on CPU#12.
CPU#12: Intel P4/Xeon Extended MCE MSRs (12) available
CPU#12: Thermal monitoring enabled
CPU12: Intel(R) Genuine CPU 1.50GHz stepping 01
Booting processor 13/35 eip 2000
Initializing CPU#13
masked ExtINT on CPU#13
Leaving ESR disabled.
Mapping cpu 13 to node 1
Calibrating delay loop... 198.65 BogoMIPS
CPU: Trace cache: 12K uops, L1 D cache: 8K
CPU: L2 cache: 256K
CPU: L3 cache: 512K
CPU: Physical Processor ID: 9
Intel machine check architecture supported.
Intel machine check reporting enabled on CPU#13.
CPU#13: Intel P4/Xeon Extended MCE MSRs (12) available
CPU#13: Thermal monitoring enabled
CPU13: Intel(R) Xeon(TM) CPU 1.50GHz stepping 01
Booting processor 14/49 eip 2000
Initializing CPU#14
masked ExtINT on CPU#14
Leaving ESR disabled.
Mapping cpu 14 to node 1
Calibrating delay loop... 198.65 BogoMIPS
CPU: Trace cache: 12K uops, L1 D cache: 8K
CPU: L2 cache: 256K
CPU: L3 cache: 512K
CPU: Physical Processor ID: 10
Intel machine check architecture supported.
Intel machine check reporting enabled on CPU#14.
CPU#14: Intel P4/Xeon Extended MCE MSRs (12) available
CPU#14: Thermal monitoring enabled
CPU14: Intel(R) Xeon(TM) CPU 1.50GHz stepping 01
Booting processor 15/51 eip 2000
Initializing CPU#15
masked ExtINT on CPU#15
Leaving ESR disabled.
Mapping cpu 15 to node 1
Calibrating delay loop... 198.65 BogoMIPS
CPU: Trace cache: 12K uops, L1 D cache: 8K
CPU: L2 cache: 256K
CPU: L3 cache: 512K
CPU: Physical Processor ID: 11
Intel machine check architecture supported.
Intel machine check reporting enabled on CPU#15.
CPU#15: Intel P4/Xeon Extended MCE MSRs (12) available
CPU#15: Thermal monitoring enabled
CPU15: Intel(R) Xeon(TM) CPU 1.50GHz stepping 01
Booting processor 16/74 eip 2000
Not responding.
Unmapping cpu 16 from all nodes
CPU #74 not responding - cannot use it.
Booting processor 16/159 eip 2000
Not responding.
Unmapping cpu 16 from all nodes
CPU #159 not responding - cannot use it.
Booting processor 16/17 eip 2000
Initializing CPU#16
masked ExtINT on CPU#16
Leaving ESR disabled.
Mapping cpu 16 to node 0
Calibrating delay loop... 199.16 BogoMIPS
CPU: Trace cache: 12K uops, L1 D cache: 8K
CPU: L2 cache: 256K
CPU: L3 cache: 512K
CPU: Physical Processor ID: 2
Intel machine check architecture supported.
Intel machine check reporting enabled on CPU#16.
CPU#16: Intel P4/Xeon Extended MCE MSRs (12) available
CPU#16: Thermal monitoring enabled
CPU16: Intel(R) Xeon(TM) CPU 1.50GHz stepping 01
Booting processor 17/192 eip 2000
Not responding.
Unmapping cpu 17 from all nodes
CPU #192 not responding - cannot use it.
Booting processor 17/233 eip 2000
Not responding.
Unmapping cpu 17 from all nodes
CPU #233 not responding - cannot use it.
Booting processor 17/159 eip 2000
Not responding.
Unmapping cpu 17 from all nodes
CPU #159 not responding - cannot use it.
Booting processor 17/17 eip 2000
Initializing CPU#17
masked ExtINT on CPU#17
Leaving ESR disabled.
Mapping cpu 17 to node 0
Calibrating delay loop... 199.16 BogoMIPS
CPU: Trace cache: 12K uops, L1 D cache: 8K
CPU: L2 cache: 256K
CPU: L3 cache: 512K
CPU: Physical Processor ID: 2
Intel machine check architecture supported.
Intel machine check reporting enabled on CPU#17.
CPU#17: Intel P4/Xeon Extended MCE MSRs (12) available
CPU#17: Thermal monitoring enabled
CPU17: Intel(R) Xeon(TM) CPU 1.50GHz stepping 01
Booting processor 18/192 eip 2000
Not responding.
Unmapping cpu 18 from all nodes
CPU #192 not responding - cannot use it.
Booting processor 18/108 eip 2000
Not responding.
Unmapping cpu 18 from all nodes
CPU #108 not responding - cannot use it.
Booting processor 18/97 eip 2000
Not responding.
Unmapping cpu 18 from all nodes
CPU #97 not responding - cannot use it.
Booting processor 18/112 eip 2000
Not responding.
Unmapping cpu 18 from all nodes
CPU #112 not responding - cannot use it.
Booting processor 18/105 eip 2000
Not responding.
Unmapping cpu 18 from all nodes
CPU #105 not responding - cannot use it.
Booting processor 18/99 eip 2000
Not responding.
Unmapping cpu 18 from all nodes
CPU #99 not responding - cannot use it.
Booting processor 18/160 eip 2000
Not responding.
Unmapping cpu 18 from all nodes
CPU #160 not responding - cannot use it.
Booting processor 18/185 eip 2000
Not responding.
Unmapping cpu 18 from all nodes
CPU #185 not responding - cannot use it.
Booting processor 18/72 eip 2000
Not responding.
Unmapping cpu 18 from all nodes
CPU #72 not responding - cannot use it.
Booting processor 18/192 eip 2000
Not responding.
Unmapping cpu 18 from all nodes
CPU #192 not responding - cannot use it.
Booting processor 18/232 eip 2000
Not responding.
Unmapping cpu 18 from all nodes
CPU #232 not responding - cannot use it.
Booting processor 18/3 eip 2000
Initializing CPU#18
masked ExtINT on CPU#18
Leaving ESR disabled.
Mapping cpu 18 to node 0
Calibrating delay loop... 199.16 BogoMIPS
CPU: Trace cache: 12K uops, L1 D cache: 8K
CPU: L2 cache: 256K
CPU: L3 cache: 512K
CPU: Physical Processor ID: 1
Intel machine check architecture supported.
Intel machine check reporting enabled on CPU#18.
CPU#18: Intel P4/Xeon Extended MCE MSRs (12) available
CPU#18: Thermal monitoring enabled
CPU18: Intel(R) Xeon(TM) CPU 1.50GHz stepping 01
Total of 19 processors activated (3775.48 BogoMIPS).
cpu_sibling_map[0] = 8
cpu_sibling_map[1] = 9
cpu_sibling_map[2] = 10
cpu_sibling_map[3] = 11
cpu_sibling_map[4] = 12
cpu_sibling_map[5] = 13
cpu_sibling_map[6] = 14
cpu_sibling_map[7] = 15
cpu_sibling_map[8] = 0
cpu_sibling_map[9] = 1
cpu_sibling_map[10] = 2
cpu_sibling_map[11] = 3
cpu_sibling_map[12] = 4
cpu_sibling_map[13] = 5
cpu_sibling_map[14] = 6
cpu_sibling_map[15] = 7
cpu_sibling_map[16] = 2
cpu_sibling_map[17] = 2
cpu_sibling_map[18] = 1
ENABLING IO-APIC IRQs
Setting 14 in the phys_id_present_map
...changing IO-APIC physical APIC ID to 14 ... ok.
Setting 13 in the phys_id_present_map
...changing IO-APIC physical APIC ID to 13 ... ok.
..TIMER: vector=0x31 pin1=0 pin2=-1
testing the IO APIC.......................
.................................... done.
Using local APIC timer interrupts.
calibrating APIC timer ...
..... CPU clock speed is 1496.0767 MHz.
..... host bus clock speed is 99.0784 MHz.
checking TSC synchronization across 19 CPUs:
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: CPU boot problem on 2.6.0-test3-bk8
2003-08-20 21:58 CPU boot problem on 2.6.0-test3-bk8 Andrew Theurer
@ 2003-08-21 1:02 ` Dave Hansen
2003-08-21 1:13 ` Andrew Theurer
0 siblings, 1 reply; 19+ messages in thread
From: Dave Hansen @ 2003-08-21 1:02 UTC (permalink / raw)
To: Andrew Theurer; +Cc: linux-kernel
On Wed, 2003-08-20 at 14:58, Andrew Theurer wrote:
> Maybe this is already known, but just in case:
> I cannot fully boot on an x440 system with 2.6.0-test3-bk8. The kernel tries
> to boot more than the 16 logical processors, and after failing (no response)
> on cpus 16, 17, and 18, it still thinks it has 19 cpus total. It finally
> gets stuck at "checking TSC synchronization across 19 CPUs:"
>
> Attached is the boot log. Any ideas? I'll try -test3-bk7 next
Can you see if it works without HT on? Did it work on plain -test3?
My 16-way x440 with no HT boots fine on test3.
--
Dave Hansen
haveblue@us.ibm.com
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: CPU boot problem on 2.6.0-test3-bk8
2003-08-21 1:02 ` Dave Hansen
@ 2003-08-21 1:13 ` Andrew Theurer
2003-08-21 3:42 ` Dave Hansen
0 siblings, 1 reply; 19+ messages in thread
From: Andrew Theurer @ 2003-08-21 1:13 UTC (permalink / raw)
To: Dave Hansen; +Cc: linux-kernel
On Wednesday 20 August 2003 20:02, Dave Hansen wrote:
> On Wed, 2003-08-20 at 14:58, Andrew Theurer wrote:
> > Maybe this is already known, but just in case:
> > I cannot fully boot on an x440 system with 2.6.0-test3-bk8. The kernel
> > tries to boot more than the 16 logical processors, and after failing (no
> > response) on cpus 16, 17, and 18, it still thinks it has 19 cpus total.
> > It finally gets stuck at "checking TSC synchronization across 19 CPUs:"
> >
> > Attached is the boot log. Any ideas? I'll try -test3-bk7 next
>
> Can you see if it works without HT on? Did it work on plain -test3?
> My 16-way x440 with no HT boots fine on test3.
I'll try without HT to see what happens. FWIW, it boots fine with HT if I set
maxcpus=16. I am wondering if (apicid == BAD_APIC) test is not working in
smp_boot_cpus.
-Andrew Theurer
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: CPU boot problem on 2.6.0-test3-bk8
2003-08-21 1:13 ` Andrew Theurer
@ 2003-08-21 3:42 ` Dave Hansen
2003-08-21 14:10 ` Andrew Theurer
0 siblings, 1 reply; 19+ messages in thread
From: Dave Hansen @ 2003-08-21 3:42 UTC (permalink / raw)
To: Andrew Theurer
Cc: linux-kernel, William Lee Irwin III, Andrew Morton, Martin J. Bligh
[-- Attachment #1: Type: text/plain, Size: 1726 bytes --]
On Wed, 2003-08-20 at 18:13, Andrew Theurer wrote:
> On Wednesday 20 August 2003 20:02, Dave Hansen wrote:
> > On Wed, 2003-08-20 at 14:58, Andrew Theurer wrote:
> > > Maybe this is already known, but just in case:
> > > I cannot fully boot on an x440 system with 2.6.0-test3-bk8. The kernel
> > > tries to boot more than the 16 logical processors, and after failing (no
> > > response) on cpus 16, 17, and 18, it still thinks it has 19 cpus total.
> > > It finally gets stuck at "checking TSC synchronization across 19 CPUs:"
> > >
> > > Attached is the boot log. Any ideas? I'll try -test3-bk7 next
> >
> > Can you see if it works without HT on? Did it work on plain -test3?
> > My 16-way x440 with no HT boots fine on test3.
>
> I'll try without HT to see what happens. FWIW, it boots fine with HT if I set
> maxcpus=16. I am wondering if (apicid == BAD_APIC) test is not working in
> smp_boot_cpus.
Hmmm. This is looking like fallout from the massive wli-bomb. Here's
the loop that controls the cpu booting, before and after cpumask_t:
- for (bit = 0; kicked < NR_CPUS && bit < BITS_PER_LONG; bit++) + for
(bit = 0; kicked < NR_CPUS && bit < MAX_APICS; bit++)
apicid = cpu_present_to_apicid(bit);
"kicked" only gets incremented for CPUs that were successfully booted,
so it doesn't help terminate the loop much. MAX_APICS is 256 on summit,
which is *MUCH* bigger than BITS_PER_LONG.
cpu_2_logical_apicid[NR_CPUS] which is referenced from
cpu_present_to_apicid() is getting referenced up to MAX_APICs, which is
bigger than NR_CPUS. Overflow. Bang. garbage != BAD_APICID :)
Attached patch fixes it. We sure do have a lot of duplicate code in the
subarches. <sigh>
--
Dave Hansen
haveblue@us.ibm.com
[-- Attachment #2: cpu_to_logical_apicid-fix-2.6.0-test3-bk8-0.patch --]
[-- Type: text/x-patch, Size: 2325 bytes --]
diff -urp linux-2.6.0-test3-clean/include/asm-i386/mach-bigsmp/mach_apic.h linux-2.6.0-test3-work/include/asm-i386/mach-bigsmp/mach_apic.h
--- linux-2.6.0-test3-clean/include/asm-i386/mach-bigsmp/mach_apic.h Wed Aug 20 19:54:32 2003
+++ linux-2.6.0-test3-work/include/asm-i386/mach-bigsmp/mach_apic.h Wed Aug 20 20:23:52 2003
@@ -98,6 +98,8 @@ extern u8 cpu_2_logical_apicid[];
/* Mapping from cpu number to logical apicid */
static inline int cpu_to_logical_apicid(int cpu)
{
+ if (cpu >= NR_CPUS)
+ return BAD_APICID;
return (int)cpu_2_logical_apicid[cpu];
}
diff -urp linux-2.6.0-test3-clean/include/asm-i386/mach-es7000/mach_apic.h linux-2.6.0-test3-work/include/asm-i386/mach-es7000/mach_apic.h
--- linux-2.6.0-test3-clean/include/asm-i386/mach-es7000/mach_apic.h Wed Aug 20 19:54:32 2003
+++ linux-2.6.0-test3-work/include/asm-i386/mach-es7000/mach_apic.h Wed Aug 20 20:23:56 2003
@@ -123,6 +123,8 @@ extern u8 cpu_2_logical_apicid[];
/* Mapping from cpu number to logical apicid */
static inline int cpu_to_logical_apicid(int cpu)
{
+ if (cpu >= NR_CPUS)
+ return BAD_APICID;
return (int)cpu_2_logical_apicid[cpu];
}
diff -urp linux-2.6.0-test3-clean/include/asm-i386/mach-numaq/mach_apic.h linux-2.6.0-test3-work/include/asm-i386/mach-numaq/mach_apic.h
--- linux-2.6.0-test3-clean/include/asm-i386/mach-numaq/mach_apic.h Wed Aug 20 19:54:32 2003
+++ linux-2.6.0-test3-work/include/asm-i386/mach-numaq/mach_apic.h Wed Aug 20 20:23:59 2003
@@ -60,6 +60,8 @@ static inline physid_mask_t ioapic_phys_
extern u8 cpu_2_logical_apicid[];
static inline int cpu_to_logical_apicid(int cpu)
{
+ if (cpu >= NR_CPUS)
+ return BAD_APICID;
return (int)cpu_2_logical_apicid[cpu];
}
diff -urp linux-2.6.0-test3-clean/include/asm-i386/mach-summit/mach_apic.h linux-2.6.0-test3-work/include/asm-i386/mach-summit/mach_apic.h
--- linux-2.6.0-test3-clean/include/asm-i386/mach-summit/mach_apic.h Wed Aug 20 19:54:32 2003
+++ linux-2.6.0-test3-work/include/asm-i386/mach-summit/mach_apic.h Wed Aug 20 20:24:03 2003
@@ -80,6 +80,8 @@ static inline int apicid_to_node(int log
extern u8 cpu_2_logical_apicid[];
static inline int cpu_to_logical_apicid(int cpu)
{
+ if (cpu >= NR_CPUS)
+ return BAD_APICID;
return (int)cpu_2_logical_apicid[cpu];
}
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: CPU boot problem on 2.6.0-test3-bk8
2003-08-21 3:42 ` Dave Hansen
@ 2003-08-21 14:10 ` Andrew Theurer
2003-08-21 14:58 ` Dave Hansen
2003-08-21 15:28 ` Dave Hansen
0 siblings, 2 replies; 19+ messages in thread
From: Andrew Theurer @ 2003-08-21 14:10 UTC (permalink / raw)
To: Dave Hansen
Cc: linux-kernel, William Lee Irwin III, Andrew Morton, Martin J. Bligh
[-- Attachment #1: Type: text/plain, Size: 2002 bytes --]
On Wednesday 20 August 2003 22:42, Dave Hansen wrote:
> On Wed, 2003-08-20 at 18:13, Andrew Theurer wrote:
> > On Wednesday 20 August 2003 20:02, Dave Hansen wrote:
> > > On Wed, 2003-08-20 at 14:58, Andrew Theurer wrote:
> > > > Maybe this is already known, but just in case:
> > > > I cannot fully boot on an x440 system with 2.6.0-test3-bk8. The
> > > > kernel tries to boot more than the 16 logical processors, and after
> > > > failing (no response) on cpus 16, 17, and 18, it still thinks it has
> > > > 19 cpus total. It finally gets stuck at "checking TSC synchronization
> > > > across 19 CPUs:"
> > > >
> > > > Attached is the boot log. Any ideas? I'll try -test3-bk7 next
> > >
> > > Can you see if it works without HT on? Did it work on plain -test3?
> > > My 16-way x440 with no HT boots fine on test3.
> >
> > I'll try without HT to see what happens. FWIW, it boots fine with HT if
> > I set maxcpus=16. I am wondering if (apicid == BAD_APIC) test is not
> > working in smp_boot_cpus.
>
> Hmmm. This is looking like fallout from the massive wli-bomb. Here's
> the loop that controls the cpu booting, before and after cpumask_t:
>
> - for (bit = 0; kicked < NR_CPUS && bit < BITS_PER_LONG; bit++) + for
> (bit = 0; kicked < NR_CPUS && bit < MAX_APICS; bit++)
> apicid = cpu_present_to_apicid(bit);
>
> "kicked" only gets incremented for CPUs that were successfully booted,
> so it doesn't help terminate the loop much. MAX_APICS is 256 on summit,
> which is *MUCH* bigger than BITS_PER_LONG.
> cpu_2_logical_apicid[NR_CPUS] which is referenced from
> cpu_present_to_apicid() is getting referenced up to MAX_APICs, which is
> bigger than NR_CPUS. Overflow. Bang. garbage != BAD_APICID :)
Still looks like we have a problem (see attached boot log). Maybe we should
change that for loop to:
for (bit = 0; kicked < num_processors && bit < BITS_PER_LONG; bit++)
So we only loop for the actual number processors found in mpparse.c? This
seems to work for me.
-Andrew Theurer
[-- Attachment #2: 260test3bk8patch1 --]
[-- Type: text/plain, Size: 22791 bytes --]
GRUB version 0.93 (631K lower / 3668699K upper memory)
+-------------------------------------------------------------------------+||||||||||||||||||||||||+-------------------------------------------------------------------------+
Use the ^ and v keys to select which entry is highlighted.
Press enter to boot the selected OS, 'e' to edit the
commands before booting, 'a' to modify the kernel arguments
before booting, or 'c' for a command-line. 2.6.0-test3 2.6.0-test3-bk4 2.6.0-test3-bk5 2.6.0-test3-bk6 2.6.0-test3-bk7 2.6.0-test3-bk8 2.6.0-test2-numaschedgood 2.6.0-test2 249e25summit_patch 249e20summit2 249e20summit 2.6.0-test2-numasched vThe highlighted entry will be booted automatically in 10 seconds. The highlighted entry will be booted automatically in 9 seconds. The highlighted entry will be booted automatically in 8 seconds. The highlighted entry will be booted automatically in 7 seconds. Booting '2.6.0-test3-bk8'
root (hd0,0)
Filesystem type is ext2fs, partition type 0x83
kernel /bzImage-2.6.0-test3-bk8 ro root=/dev/sda7 console=ttyS0,38400n8
[Linux-bzImage, setup=0xc00, size=0x1fc8a6]
Linux version 2.6.0-test3-bk8 (root@x4408way2) (gcc version 3.2.2) #3 SMP Thu Aug 21 10:13:50 CDT 2003
Video mode to be used for restore is ffff
BIOS-provided physical RAM map:
BIOS-e820: 0000000000000000 - 000000000009dc00 (usable)
BIOS-e820: 000000000009dc00 - 00000000000a0000 (reserved)
BIOS-e820: 00000000000e0000 - 0000000000100000 (reserved)
BIOS-e820: 0000000000100000 - 00000000dffb6ec0 (usable)
BIOS-e820: 00000000dffb6ec0 - 00000000dffbf800 (ACPI data)
BIOS-e820: 00000000dffbf800 - 00000000e0000000 (reserved)
BIOS-e820: 00000000fec00000 - 0000000100000000 (reserved)
BIOS-e820: 0000000100000000 - 0000000320000000 (usable)
get_memcfg_from_srat: assigning address to rsdp
RSD PTR v0 [IBM ]
Begin table scan....
CPU 0x00 in proximity domain 0x00
CPU 0x02 in proximity domain 0x00
CPU 0x10 in proximity domain 0x00
CPU 0x12 in proximity domain 0x00
CPU 0x20 in proximity domain 0x01
CPU 0x22 in proximity domain 0x01
CPU 0x30 in proximity domain 0x01
CPU 0x32 in proximity domain 0x01
CPU 0x01 in proximity domain 0x00
CPU 0x03 in proximity domain 0x00
CPU 0x11 in proximity domain 0x00
CPU 0x13 in proximity domain 0x00
CPU 0x21 in proximity domain 0x01
CPU 0x23 in proximity domain 0x01
CPU 0x31 in proximity domain 0x01
CPU 0x33 in proximity domain 0x01
Memory range 0x0 to 0xE0000 (type 0x1) in proximity domain 0x00 enabled
Memory range 0x100000 to 0x220000 (type 0x1) in proximity domain 0x00 enabled
Memory range 0x220000 to 0x320000 (type 0x1) in proximity domain 0x01 enabled
acpi20_parse_srat: Entry length value is zero; can't parse any further!
pxm bitmap: 03 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
Number of logical nodes in system = 2
Number of memory chunks in system = 3
chunk 0 nid 0 start_pfn 00000000 end_pfn 000e0000
chunk 1 nid 0 start_pfn 00100000 end_pfn 00220000
chunk 2 nid 1 start_pfn 00220000 end_pfn 00320000
Reserving 11776 pages of KVA for lmem_map of node 1
Shrinking node 1 from 3276800 pages to 3265024 pages
Reserving total of 11776 pages for numa KVA remap
11904MB HIGHMEM available.
850MB LOWMEM available.
min_low_pfn = 1445, max_low_pfn = 217600, highstart_pfn = 229376
Low memory ends at vaddr f5200000
node 0 will remap to vaddr f8000000 - f8000000
node 1 will remap to vaddr f5200000 - f8000000
High memory starts at vaddr f8000000
ACPI: S3 and PAE do not like each other for now, S3 disabled.
found SMP MP-table at 0009dd40
hm, page 0009d000 reserved twice.
hm, page 0009e000 reserved twice.
hm, page 0009e000 reserved twice.
hm, page 0009f000 reserved twice.
On node 0 totalpages: 2097152
DMA zone: 4096 pages, LIFO batch:1
Normal zone: 213504 pages, LIFO batch:16
HighMem zone: 1879552 pages, LIFO batch:16
BUG: wrong zone alignment, it will crash
On node 1 totalpages: 1036800
DMA zone: 0 pages, LIFO batch:1
Normal zone: 0 pages, LIFO batch:1
HighMem zone: 1036800 pages, LIFO batch:16
DMI 2.3 present.
IBM machine detected. Enabling interrupts during APM calls.
IBM machine detected. Disabling SMBus accesses.
IBM eserver xSeries 440 detected: force use of acpi=ht
ACPI: RSDP (v000 IBM ) @ 0x000fdba0
ACPI: RSDT (v001 IBM SERVIGIL 0x00001000 IBM 0x45444f43) @ 0xdffbf780
ACPI: FADT (v001 IBM SERVIGIL 0x00001000 IBM 0x45444f43) @ 0xdffbf700
ACPI: MADT (v001 IBM SERVIGIL 0x00001000 IBM 0x45444f43) @ 0xdffbf580
ACPI: SRAT (v001 IBM SERVIGIL 0x00001000 IBM 0x45444f43) @ 0xdffbf3c0
ACPI: DSDT (v001 IBM SERVIGIL 0x00001000 INTL 0x02002025) @ 0x00000000
ACPI: Local APIC address 0xfee00000
ACPI: LAPIC (acpi_id[0x00] lapic_id[0x00] enabled)
Processor #0 15:1 APIC version 20
ACPI: LAPIC (acpi_id[0x01] lapic_id[0x02] enabled)
Processor #2 15:1 APIC version 20
ACPI: LAPIC (acpi_id[0x02] lapic_id[0x10] enabled)
Processor #16 15:1 APIC version 20
ACPI: LAPIC (acpi_id[0x03] lapic_id[0x12] enabled)
Processor #18 15:1 APIC version 20
ACPI: LAPIC (acpi_id[0x04] lapic_id[0x20] enabled)
Processor #32 15:1 APIC version 20
ACPI: LAPIC (acpi_id[0x05] lapic_id[0x22] enabled)
Processor #34 15:1 APIC version 20
ACPI: LAPIC (acpi_id[0x06] lapic_id[0x30] enabled)
Processor #48 15:1 APIC version 20
ACPI: LAPIC (acpi_id[0x07] lapic_id[0x32] enabled)
Processor #50 15:1 APIC version 20
ACPI: LAPIC (acpi_id[0x08] lapic_id[0x01] enabled)
Processor #1 15:1 APIC version 20
ACPI: LAPIC (acpi_id[0x09] lapic_id[0x03] enabled)
Processor #3 15:1 APIC version 20
ACPI: LAPIC (acpi_id[0x0a] lapic_id[0x11] enabled)
Processor #17 15:1 APIC version 20
ACPI: LAPIC (acpi_id[0x0b] lapic_id[0x13] enabled)
Processor #19 15:1 APIC version 20
ACPI: LAPIC (acpi_id[0x0c] lapic_id[0x21] enabled)
Processor #33 15:1 APIC version 20
ACPI: LAPIC (acpi_id[0x0d] lapic_id[0x23] enabled)
Processor #35 15:1 APIC version 20
ACPI: LAPIC (acpi_id[0x0e] lapic_id[0x31] enabled)
Processor #49 15:1 APIC version 20
ACPI: LAPIC (acpi_id[0x0f] lapic_id[0x33] enabled)
Processor #51 15:1 APIC version 20
ACPI: LAPIC_NMI (acpi_id[0x00] polarity[0x0] trigger[0x0] lint[0x1])
ACPI: LAPIC_NMI (acpi_id[0x01] polarity[0x0] trigger[0x0] lint[0x1])
ACPI: LAPIC_NMI (acpi_id[0x02] polarity[0x0] trigger[0x0] lint[0x1])
ACPI: LAPIC_NMI (acpi_id[0x03] polarity[0x0] trigger[0x0] lint[0x1])
ACPI: LAPIC_NMI (acpi_id[0x04] polarity[0x0] trigger[0x0] lint[0x1])
ACPI: LAPIC_NMI (acpi_id[0x05] polarity[0x0] trigger[0x0] lint[0x1])
ACPI: LAPIC_NMI (acpi_id[0x06] polarity[0x0] trigger[0x0] lint[0x1])
ACPI: LAPIC_NMI (acpi_id[0x07] polarity[0x0] trigger[0x0] lint[0x1])
ACPI: LAPIC_NMI (acpi_id[0x08] polarity[0x0] trigger[0x0] lint[0x1])
ACPI: LAPIC_NMI (acpi_id[0x09] polarity[0x0] trigger[0x0] lint[0x1])
ACPI: LAPIC_NMI (acpi_id[0x0a] polarity[0x0] trigger[0x0] lint[0x1])
ACPI: LAPIC_NMI (acpi_id[0x0b] polarity[0x0] trigger[0x0] lint[0x1])
ACPI: LAPIC_NMI (acpi_id[0x0c] polarity[0x0] trigger[0x0] lint[0x1])
ACPI: LAPIC_NMI (acpi_id[0x0d] polarity[0x0] trigger[0x0] lint[0x1])
ACPI: LAPIC_NMI (acpi_id[0x0e] polarity[0x0] trigger[0x0] lint[0x1])
ACPI: LAPIC_NMI (acpi_id[0x0f] polarity[0x0] trigger[0x0] lint[0x1])
Using ACPI for processor (LAPIC) configuration information
Intel MultiProcessor Specification v1.4
Virtual Wire compatibility mode.
OEM ID: IBM ENSW Product ID: VIGIL SMP APIC at: 0xFEE00000
I/O APIC #14 Version 17 at 0xFEC00000.
I/O APIC #13 Version 17 at 0xFEC01000.
Enabling APIC mode: Summit. Using 2 I/O APICs
Processors: 16
Building zonelist for node : 0
Building zonelist for node : 1
Kernel command line: ro root=/dev/sda7 console=ttyS0,38400n8
Initializing CPU#0
PID hash table entries: 4096 (order 12: 32768 bytes)
Summit chipset: Starting Cyclone Counter.
Detected 1498.475 MHz processor.
Console: colour VGA+ 80x25
Calibrating delay loop... 193.02 BogoMIPS
Initializing highpages for node 0
Initializing highpages for node 1
Memory: 12431384k/13107200k available (3113k kernel code, 102620k reserved, 1120k data, 204k init, 11665112k highmem)
Dentry cache hash table entries: 1048576 (order: 10, 4194304 bytes)
Inode-cache hash table entries: 1048576 (order: 10, 4194304 bytes)
Mount-cache hash table entries: 512 (order: 0, 4096 bytes)
-> /dev
-> /dev/console
-> /root
CPU: Trace cache: 12K uops, L1 D cache: 8K
CPU: L2 cache: 256K
CPU: L3 cache: 512K
CPU: Physical Processor ID: 0
Intel machine check architecture supported.
Intel machine check reporting enabled on CPU#0.
CPU#0: Intel P4/Xeon Extended MCE MSRs (12) available
CPU#0: Thermal monitoring enabled
Enabling fast FPU save and restore... done.
Enabling unmasked SIMD FPU exception support... done.
Checking 'hlt' instruction... OK.
POSIX conformance testing by UNIFIX
CPU0: Intel(R) Genuine CPU 1.50GHz stepping 01
per-CPU timeslice cutoff: 731.48 usecs.
task migration cache decay timeout: 1 msecs.
enabled ExtINT on CPU#0
Leaving ESR disabled.
Mapping cpu 0 to node 0
Booting processor 1/2 eip 2000
Initializing CPU#1
masked ExtINT on CPU#1
Leaving ESR disabled.
Mapping cpu 1 to node 0
Calibrating delay loop... 199.16 BogoMIPS
CPU: Trace cache: 12K uops, L1 D cache: 8K
CPU: L2 cache: 256K
CPU: L3 cache: 512K
CPU: Physical Processor ID: 1
Intel machine check architecture supported.
Intel machine check reporting enabled on CPU#1.
CPU#1: Intel P4/Xeon Extended MCE MSRs (12) available
CPU#1: Thermal monitoring enabled
CPU1: Intel(R) Xeon(TM) CPU 1.50GHz stepping 01
Booting processor 2/16 eip 2000
Initializing CPU#2
masked ExtINT on CPU#2
Leaving ESR disabled.
Mapping cpu 2 to node 0
Calibrating delay loop... 198.65 BogoMIPS
CPU: Trace cache: 12K uops, L1 D cache: 8K
CPU: L2 cache: 256K
CPU: L3 cache: 512K
CPU: Physical Processor ID: 2
Intel machine check architecture supported.
Intel machine check reporting enabled on CPU#2.
CPU#2: Intel P4/Xeon Extended MCE MSRs (12) available
CPU#2: Thermal monitoring enabled
CPU2: Intel(R) Xeon(TM) CPU 1.50GHz stepping 01
Booting processor 3/18 eip 2000
Initializing CPU#3
masked ExtINT on CPU#3
Leaving ESR disabled.
Mapping cpu 3 to node 0
Calibrating delay loop... 199.16 BogoMIPS
CPU: Trace cache: 12K uops, L1 D cache: 8K
CPU: L2 cache: 256K
CPU: L3 cache: 512K
CPU: Physical Processor ID: 3
Intel machine check architecture supported.
Intel machine check reporting enabled on CPU#3.
CPU#3: Intel P4/Xeon Extended MCE MSRs (12) available
CPU#3: Thermal monitoring enabled
CPU3: Intel(R) Xeon(TM) CPU 1.50GHz stepping 01
Booting processor 4/32 eip 2000
Initializing CPU#4
masked ExtINT on CPU#4
Leaving ESR disabled.
Mapping cpu 4 to node 1
Calibrating delay loop... 198.65 BogoMIPS
CPU: Trace cache: 12K uops, L1 D cache: 8K
CPU: L2 cache: 256K
CPU: L3 cache: 512K
CPU: Physical Processor ID: 8
Intel machine check architecture supported.
Intel machine check reporting enabled on CPU#4.
CPU#4: Intel P4/Xeon Extended MCE MSRs (12) available
CPU#4: Thermal monitoring enabled
CPU4: Intel(R) Genuine CPU 1.50GHz stepping 01
Booting processor 5/34 eip 2000
Initializing CPU#5
masked ExtINT on CPU#5
Leaving ESR disabled.
Mapping cpu 5 to node 1
Calibrating delay loop... 199.16 BogoMIPS
CPU: Trace cache: 12K uops, L1 D cache: 8K
CPU: L2 cache: 256K
CPU: L3 cache: 512K
CPU: Physical Processor ID: 9
Intel machine check architecture supported.
Intel machine check reporting enabled on CPU#5.
CPU#5: Intel P4/Xeon Extended MCE MSRs (12) available
CPU#5: Thermal monitoring enabled
CPU5: Intel(R) Xeon(TM) CPU 1.50GHz stepping 01
Booting processor 6/48 eip 2000
Initializing CPU#6
masked ExtINT on CPU#6
Leaving ESR disabled.
Mapping cpu 6 to node 1
Calibrating delay loop... 199.16 BogoMIPS
CPU: Trace cache: 12K uops, L1 D cache: 8K
CPU: L2 cache: 256K
CPU: L3 cache: 512K
CPU: Physical Processor ID: 10
Intel machine check architecture supported.
Intel machine check reporting enabled on CPU#6.
CPU#6: Intel P4/Xeon Extended MCE MSRs (12) available
CPU#6: Thermal monitoring enabled
CPU6: Intel(R) Xeon(TM) CPU 1.50GHz stepping 01
Booting processor 7/50 eip 2000
Initializing CPU#7
masked ExtINT on CPU#7
Leaving ESR disabled.
Mapping cpu 7 to node 1
Calibrating delay loop... 199.16 BogoMIPS
CPU: Trace cache: 12K uops, L1 D cache: 8K
CPU: L2 cache: 256K
CPU: L3 cache: 512K
CPU: Physical Processor ID: 11
Intel machine check architecture supported.
Intel machine check reporting enabled on CPU#7.
CPU#7: Intel P4/Xeon Extended MCE MSRs (12) available
CPU#7: Thermal monitoring enabled
CPU7: Intel(R) Xeon(TM) CPU 1.50GHz stepping 01
Booting processor 8/1 eip 2000
Initializing CPU#8
masked ExtINT on CPU#8
Leaving ESR disabled.
Mapping cpu 8 to node 0
Calibrating delay loop... 199.16 BogoMIPS
CPU: Trace cache: 12K uops, L1 D cache: 8K
CPU: L2 cache: 256K
CPU: L3 cache: 512K
CPU: Physical Processor ID: 0
Intel machine check architecture supported.
Intel machine check reporting enabled on CPU#8.
CPU#8: Intel P4/Xeon Extended MCE MSRs (12) available
CPU#8: Thermal monitoring enabled
CPU8: Intel(R) Genuine CPU 1.50GHz stepping 01
Booting processor 9/3 eip 2000
Initializing CPU#9
masked ExtINT on CPU#9
Leaving ESR disabled.
Mapping cpu 9 to node 0
Calibrating delay loop... 199.16 BogoMIPS
CPU: Trace cache: 12K uops, L1 D cache: 8K
CPU: L2 cache: 256K
CPU: L3 cache: 512K
CPU: Physical Processor ID: 1
Intel machine check architecture supported.
Intel machine check reporting enabled on CPU#9.
CPU#9: Intel P4/Xeon Extended MCE MSRs (12) available
CPU#9: Thermal monitoring enabled
CPU9: Intel(R) Xeon(TM) CPU 1.50GHz stepping 01
Booting processor 10/17 eip 2000
Initializing CPU#10
masked ExtINT on CPU#10
Leaving ESR disabled.
Mapping cpu 10 to node 0
Calibrating delay loop... 199.16 BogoMIPS
CPU: Trace cache: 12K uops, L1 D cache: 8K
CPU: L2 cache: 256K
CPU: L3 cache: 512K
CPU: Physical Processor ID: 2
Intel machine check architecture supported.
Intel machine check reporting enabled on CPU#10.
CPU#10: Intel P4/Xeon Extended MCE MSRs (12) available
CPU#10: Thermal monitoring enabled
CPU10: Intel(R) Xeon(TM) CPU 1.50GHz stepping 01
Booting processor 11/19 eip 2000
Initializing CPU#11
masked ExtINT on CPU#11
Leaving ESR disabled.
Mapping cpu 11 to node 0
Calibrating delay loop... 199.16 BogoMIPS
CPU: Trace cache: 12K uops, L1 D cache: 8K
CPU: L2 cache: 256K
CPU: L3 cache: 512K
CPU: Physical Processor ID: 3
Intel machine check architecture supported.
Intel machine check reporting enabled on CPU#11.
CPU#11: Intel P4/Xeon Extended MCE MSRs (12) available
CPU#11: Thermal monitoring enabled
CPU11: Intel(R) Xeon(TM) CPU 1.50GHz stepping 01
Booting processor 12/33 eip 2000
Initializing CPU#12
masked ExtINT on CPU#12
Leaving ESR disabled.
Mapping cpu 12 to node 1
Calibrating delay loop... 198.65 BogoMIPS
CPU: Trace cache: 12K uops, L1 D cache: 8K
CPU: L2 cache: 256K
CPU: L3 cache: 512K
CPU: Physical Processor ID: 8
Intel machine check architecture supported.
Intel machine check reporting enabled on CPU#12.
CPU#12: Intel P4/Xeon Extended MCE MSRs (12) available
CPU#12: Thermal monitoring enabled
CPU12: Intel(R) Genuine CPU 1.50GHz stepping 01
Booting processor 13/35 eip 2000
Initializing CPU#13
masked ExtINT on CPU#13
Leaving ESR disabled.
Mapping cpu 13 to node 1
Calibrating delay loop... 198.65 BogoMIPS
CPU: Trace cache: 12K uops, L1 D cache: 8K
CPU: L2 cache: 256K
CPU: L3 cache: 512K
CPU: Physical Processor ID: 9
Intel machine check architecture supported.
Intel machine check reporting enabled on CPU#13.
CPU#13: Intel P4/Xeon Extended MCE MSRs (12) available
CPU#13: Thermal monitoring enabled
CPU13: Intel(R) Xeon(TM) CPU 1.50GHz stepping 01
Booting processor 14/49 eip 2000
Initializing CPU#14
masked ExtINT on CPU#14
Leaving ESR disabled.
Mapping cpu 14 to node 1
Calibrating delay loop... 198.65 BogoMIPS
CPU: Trace cache: 12K uops, L1 D cache: 8K
CPU: L2 cache: 256K
CPU: L3 cache: 512K
CPU: Physical Processor ID: 10
Intel machine check architecture supported.
Intel machine check reporting enabled on CPU#14.
CPU#14: Intel P4/Xeon Extended MCE MSRs (12) available
CPU#14: Thermal monitoring enabled
CPU14: Intel(R) Xeon(TM) CPU 1.50GHz stepping 01
Booting processor 15/51 eip 2000
Initializing CPU#15
masked ExtINT on CPU#15
Leaving ESR disabled.
Mapping cpu 15 to node 1
Calibrating delay loop... 198.65 BogoMIPS
CPU: Trace cache: 12K uops, L1 D cache: 8K
CPU: L2 cache: 256K
CPU: L3 cache: 512K
CPU: Physical Processor ID: 11
Intel machine check architecture supported.
Intel machine check reporting enabled on CPU#15.
CPU#15: Intel P4/Xeon Extended MCE MSRs (12) available
CPU#15: Thermal monitoring enabled
CPU15: Intel(R) Xeon(TM) CPU 1.50GHz stepping 01
Booting processor 16/114 eip 2000
Not responding.
Unmapping cpu 16 from all nodes
CPU #114 not responding - cannot use it.
Booting processor 16/159 eip 2000
Not responding.
Unmapping cpu 16 from all nodes
CPU #159 not responding - cannot use it.
Booting processor 16/17 eip 2000
Initializing CPU#16
masked ExtINT on CPU#16
Leaving ESR disabled.
Mapping cpu 16 to node 0
Calibrating delay loop... 199.16 BogoMIPS
CPU: Trace cache: 12K uops, L1 D cache: 8K
CPU: L2 cache: 256K
CPU: L3 cache: 512K
CPU: Physical Processor ID: 2
Intel machine check architecture supported.
Intel machine check reporting enabled on CPU#16.
CPU#16: Intel P4/Xeon Extended MCE MSRs (12) available
CPU#16: Thermal monitoring enabled
CPU16: Intel(R) Xeon(TM) CPU 1.50GHz stepping 01
Booting processor 17/192 eip 2000
Not responding.
Unmapping cpu 17 from all nodes
CPU #192 not responding - cannot use it.
Booting processor 17/17 eip 2000
Initializing CPU#17
masked ExtINT on CPU#17
Leaving ESR disabled.
Mapping cpu 17 to node 0
Calibrating delay loop... 199.16 BogoMIPS
CPU: Trace cache: 12K uops, L1 D cache: 8K
CPU: L2 cache: 256K
CPU: L3 cache: 512K
CPU: Physical Processor ID: 2
Intel machine check architecture supported.
Intel machine check reporting enabled on CPU#17.
CPU#17: Intel P4/Xeon Extended MCE MSRs (12) available
CPU#17: Thermal monitoring enabled
CPU17: Intel(R) Xeon(TM) CPU 1.50GHz stepping 01
Booting processor 18/160 eip 2000
Not responding.
Unmapping cpu 18 from all nodes
CPU #160 not responding - cannot use it.
Booting processor 18/17 eip 2000
Initializing CPU#18
masked ExtINT on CPU#18
Leaving ESR disabled.
Mapping cpu 18 to node 0
Calibrating delay loop... 199.16 BogoMIPS
CPU: Trace cache: 12K uops, L1 D cache: 8K
CPU: L2 cache: 256K
CPU: L3 cache: 512K
CPU: Physical Processor ID: 2
Intel machine check architecture supported.
Intel machine check reporting enabled on CPU#18.
CPU#18: Intel P4/Xeon Extended MCE MSRs (12) available
CPU#18: Thermal monitoring enabled
CPU18: Intel(R) Xeon(TM) CPU 1.50GHz stepping 01
Booting processor 19/192 eip 2000
Not responding.
Unmapping cpu 19 from all nodes
CPU #192 not responding - cannot use it.
Booting processor 19/108 eip 2000
Not responding.
Unmapping cpu 19 from all nodes
CPU #108 not responding - cannot use it.
Booting processor 19/97 eip 2000
Not responding.
Unmapping cpu 19 from all nodes
CPU #97 not responding - cannot use it.
Booting processor 19/112 eip 2000
Not responding.
Unmapping cpu 19 from all nodes
CPU #112 not responding - cannot use it.
Booting processor 19/105 eip 2000
Not responding.
Unmapping cpu 19 from all nodes
CPU #105 not responding - cannot use it.
Booting processor 19/99 eip 2000
Not responding.
Unmapping cpu 19 from all nodes
CPU #99 not responding - cannot use it.
Booting processor 19/160 eip 2000
Not responding.
Unmapping cpu 19 from all nodes
CPU #160 not responding - cannot use it.
Booting processor 19/185 eip 2000
Not responding.
Unmapping cpu 19 from all nodes
CPU #185 not responding - cannot use it.
Booting processor 19/72 eip 2000
Not responding.
Unmapping cpu 19 from all nodes
CPU #72 not responding - cannot use it.
Booting processor 19/192 eip 2000
Not responding.
Unmapping cpu 19 from all nodes
CPU #192 not responding - cannot use it.
Booting processor 19/232 eip 2000
Not responding.
Unmapping cpu 19 from all nodes
CPU #232 not responding - cannot use it.
Booting processor 19/3 eip 2000
Initializing CPU#19
masked ExtINT on CPU#19
Leaving ESR disabled.
Mapping cpu 19 to node 0
Calibrating delay loop... 199.16 BogoMIPS
CPU: Trace cache: 12K uops, L1 D cache: 8K
CPU: L2 cache: 256K
CPU: L3 cache: 512K
CPU: Physical Processor ID: 1
Intel machine check architecture supported.
Intel machine check reporting enabled on CPU#19.
CPU#19: Intel P4/Xeon Extended MCE MSRs (12) available
CPU#19: Thermal monitoring enabled
CPU19: Intel(R) Xeon(TM) CPU 1.50GHz stepping 01
Total of 20 processors activated (3974.14 BogoMIPS).
cpu_sibling_map[0] = 8
cpu_sibling_map[1] = 9
cpu_sibling_map[2] = 10
cpu_sibling_map[3] = 11
cpu_sibling_map[4] = 12
cpu_sibling_map[5] = 13
cpu_sibling_map[6] = 14
cpu_sibling_map[7] = 15
cpu_sibling_map[8] = 0
cpu_sibling_map[9] = 1
cpu_sibling_map[10] = 2
cpu_sibling_map[11] = 3
cpu_sibling_map[12] = 4
cpu_sibling_map[13] = 5
cpu_sibling_map[14] = 6
cpu_sibling_map[15] = 7
cpu_sibling_map[16] = 2
cpu_sibling_map[17] = 2
cpu_sibling_map[18] = 2
cpu_sibling_map[19] = 1
ENABLING IO-APIC IRQs
Setting 14 in the phys_id_present_map
...changing IO-APIC physical APIC ID to 14 ... ok.
Setting 13 in the phys_id_present_map
...changing IO-APIC physical APIC ID to 13 ... ok.
..TIMER: vector=0x31 pin1=0 pin2=-1
testing the IO APIC.......................
.................................... done.
Using local APIC timer interrupts.
calibrating APIC timer ...
..... CPU clock speed is 1496.0674 MHz.
..... host bus clock speed is 99.0778 MHz.
checking TSC synchronization across 20 CPUs:
[-- Attachment #3: patch-boot-cpu.260test3bk8 --]
[-- Type: text/x-diff, Size: 1576 bytes --]
diff -Naurp linux-2.6.0-test3-bk8/arch/i386/kernel/mpparse.c linux-2.6.0-test3-bk8-patch/arch/i386/kernel/mpparse.c
--- linux-2.6.0-test3-bk8/arch/i386/kernel/mpparse.c 2003-08-21 10:42:38.000000000 -0500
+++ linux-2.6.0-test3-bk8-patch/arch/i386/kernel/mpparse.c 2003-08-21 10:36:26.000000000 -0500
@@ -68,7 +68,7 @@ unsigned long mp_lapic_addr;
unsigned int boot_cpu_physical_apicid = -1U;
unsigned int boot_cpu_logical_apicid = -1U;
/* Internal processor count */
-static unsigned int __initdata num_processors;
+unsigned int __initdata num_processors;
/* Bitmask of physically existing CPUs */
physid_mask_t phys_cpu_present_map;
diff -Naurp linux-2.6.0-test3-bk8/arch/i386/kernel/smpboot.c linux-2.6.0-test3-bk8-patch/arch/i386/kernel/smpboot.c
--- linux-2.6.0-test3-bk8/arch/i386/kernel/smpboot.c 2003-08-21 10:42:38.000000000 -0500
+++ linux-2.6.0-test3-bk8-patch/arch/i386/kernel/smpboot.c 2003-08-21 10:36:26.000000000 -0500
@@ -64,6 +64,8 @@ int phys_proc_id[NR_CPUS]; /* Package ID
/* bitmap of online cpus */
cpumask_t cpu_online_map;
+extern unsigned int num_processors;
+
static cpumask_t cpu_callin_map;
cpumask_t cpu_callout_map;
static cpumask_t smp_commenced_mask;
@@ -1020,7 +1022,7 @@ static void __init smp_boot_cpus(unsigne
Dprintk("CPU present map: %lx\n", physids_coerce(phys_cpu_present_map));
kicked = 1;
- for (bit = 0; kicked < NR_CPUS && bit < MAX_APICS; bit++) {
+ for (bit = 0; kicked < num_processors && bit < MAX_APICS; bit++) {
apicid = cpu_present_to_apicid(bit);
/*
* Don't even attempt to start the boot CPU!
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: CPU boot problem on 2.6.0-test3-bk8
2003-08-21 14:10 ` Andrew Theurer
@ 2003-08-21 14:58 ` Dave Hansen
2003-08-21 15:56 ` Andrew Theurer
2003-08-21 15:28 ` Dave Hansen
1 sibling, 1 reply; 19+ messages in thread
From: Dave Hansen @ 2003-08-21 14:58 UTC (permalink / raw)
To: Andrew Theurer
Cc: linux-kernel, William Lee Irwin III, Andrew Morton, Martin J. Bligh
On Thu, 2003-08-21 at 07:10, Andrew Theurer wrote:
> So we only loop for the actual number processors found in mpparse.c? This
> seems to work for me.
I think there's a reason it was done that way. I think your patch
breaks the visws subarch, too.
Could you mark up that loop a bit and printk a bit, so we can see which
continue you're missing?
<pasting patch lazily in email because I can't be bothered to actually copy it from the machine I"m working on>
diff -urp linux-2.6.0-test3-clean/arch/i386/kernel/smpboot.c linux-2.6.0-test3-work/arch/i386/kernel/smpboot.c
--- linux-2.6.0-test3-clean/arch/i386/kernel/smpboot.c Wed Aug 20 19:54:29 2003
+++ linux-2.6.0-test3-work/arch/i386/kernel/smpboot.c Wed Aug 20 20:19:41 2003
@@ -1020,24 +1020,30 @@ static void __init smp_boot_cpus(unsigne
Dprintk("CPU present map: %lx\n", physids_coerce(phys_cpu_present_map));
kicked = 1;
- for (bit = 0; kicked < NR_CPUS && bit < MAX_APICS; bit++) {
+ for (bit = 0; kicked < NR_CPUS && bit < MAX_APICS; bit++, kicked++) {
apicid = cpu_present_to_apicid(bit);
/*
* Don't even attempt to start the boot CPU!
*/
- if ((apicid == boot_cpu_apicid) || (apicid == BAD_APICID))
+ printk("smp_boot_cpus() bit: %d\n", bit);
+ if ((apicid == boot_cpu_apicid) || (apicid == BAD_APICID)) {
+ printk("(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)\n");
+ printk("apicid: %08lx boot_cpu_apicid: %08lx BAD_APICID: %08lx\n", apicid, boot_cpu_apicid, BAD_APICID);
continue;
+ }
- if (!check_apicid_present(bit))
+ if (!check_apicid_present(bit)) {
+ printk("!check_apicid_present(bit)\n");
continue;
- if (max_cpus <= cpucount+1)
+ }
+ if (max_cpus <= cpucount+1) {
+ printk("(max_cpus <= cpucount+1)\n");
continue;
+ }
if (do_boot_cpu(apicid))
printk("CPU #%d not responding - cannot use it.\n",
apicid);
- else
- ++kicked;
}
/*
--
Dave Hansen
haveblue@us.ibm.com
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: CPU boot problem on 2.6.0-test3-bk8
2003-08-21 14:10 ` Andrew Theurer
2003-08-21 14:58 ` Dave Hansen
@ 2003-08-21 15:28 ` Dave Hansen
2003-08-21 21:04 ` William Lee Irwin III
1 sibling, 1 reply; 19+ messages in thread
From: Dave Hansen @ 2003-08-21 15:28 UTC (permalink / raw)
To: Andrew Theurer
Cc: linux-kernel, William Lee Irwin III, Andrew Morton, Martin J. Bligh
On Thu, 2003-08-21 at 07:10, Andrew Theurer wrote:
> Still looks like we have a problem (see attached boot log). Maybe we should
> change that for loop to:
>
> for (bit = 0; kicked < num_processors && bit < BITS_PER_LONG; bit++)
>
> So we only loop for the actual number processors found in mpparse.c? This
> seems to work for me.
You have something else wrong too:
[dave@nighthawk temp]$ egrep -c ^CPU\[0-9\]+: 260test3bk8patch1
20
It looks like you booted 20 processors, successfully.
You have 5 "Geniune" cpus and 16 "Xeon" cpus. Are you using plain
summit, or generic arch support?
$ egrep ^CPU\[0-9\]+: 260test3bk8patch1
CPU0: Intel(R) Genuine CPU 1.50GHz stepping 01
CPU1: Intel(R) Xeon(TM) CPU 1.50GHz stepping 01
CPU2: Intel(R) Xeon(TM) CPU 1.50GHz stepping 01
CPU3: Intel(R) Xeon(TM) CPU 1.50GHz stepping 01
CPU4: Intel(R) Genuine CPU 1.50GHz stepping 01
CPU5: Intel(R) Xeon(TM) CPU 1.50GHz stepping 01
CPU6: Intel(R) Xeon(TM) CPU 1.50GHz stepping 01
CPU7: Intel(R) Xeon(TM) CPU 1.50GHz stepping 01
CPU8: Intel(R) Genuine CPU 1.50GHz stepping 01
CPU9: Intel(R) Xeon(TM) CPU 1.50GHz stepping 01
CPU10: Intel(R) Xeon(TM) CPU 1.50GHz stepping 01
CPU11: Intel(R) Xeon(TM) CPU 1.50GHz stepping 01
CPU12: Intel(R) Genuine CPU 1.50GHz stepping 01
CPU13: Intel(R) Xeon(TM) CPU 1.50GHz stepping 01
CPU14: Intel(R) Xeon(TM) CPU 1.50GHz stepping 01
CPU15: Intel(R) Xeon(TM) CPU 1.50GHz stepping 01
CPU16: Intel(R) Xeon(TM) CPU 1.50GHz stepping 01
CPU17: Intel(R) Xeon(TM) CPU 1.50GHz stepping 01
CPU18: Intel(R) Xeon(TM) CPU 1.50GHz stepping 01
CPU19: Intel(R) Xeon(TM) CPU 1.50GHz stepping 01
--
Dave Hansen
haveblue@us.ibm.com
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: CPU boot problem on 2.6.0-test3-bk8
2003-08-21 14:58 ` Dave Hansen
@ 2003-08-21 15:56 ` Andrew Theurer
2003-08-21 16:09 ` Dave Hansen
0 siblings, 1 reply; 19+ messages in thread
From: Andrew Theurer @ 2003-08-21 15:56 UTC (permalink / raw)
To: Dave Hansen
Cc: linux-kernel, William Lee Irwin III, Andrew Morton, Martin J. Bligh
[-- Attachment #1: Type: text/plain, Size: 1270 bytes --]
On Thursday 21 August 2003 09:58, Dave Hansen wrote:
> On Thu, 2003-08-21 at 07:10, Andrew Theurer wrote:
> > So we only loop for the actual number processors found in mpparse.c?
> > This seems to work for me.
>
> I think there's a reason it was done that way. I think your patch
> breaks the visws subarch, too.
>
> Could you mark up that loop a bit and printk a bit, so we can see which
> continue you're missing?
>
> <pasting patch lazily in email because I can't be bothered to actually copy
> it from the machine I"m working on> diff -urp
> linux-2.6.0-test3-clean/arch/i386/kernel/smpboot.c
> linux-2.6.0-test3-work/arch/i386/kernel/smpboot.c ---
> linux-2.6.0-test3-clean/arch/i386/kernel/smpboot.c Wed Aug 20 19:54:29
> 2003 +++ linux-2.6.0-test3-work/arch/i386/kernel/smpboot.c Wed Aug 20
> 20:19:41 2003 @@ -1020,24 +1020,30 @@ static void __init
> smp_boot_cpus(unsigne
> Dprintk("CPU present map: %lx\n",
> physids_coerce(phys_cpu_present_map));
>
> kicked = 1;
> - for (bit = 0; kicked < NR_CPUS && bit < MAX_APICS; bit++) {
> + for (bit = 0; kicked < NR_CPUS && bit < MAX_APICS; bit++, kicked++)
This patch (plus your first one) seems to work. Perhaps the addition of
kicked++ above helped? Attached is the boot log.
[-- Attachment #2: dmesg --]
[-- Type: text/plain, Size: 35792 bytes --]
Linux version 2.6.0-test3-bk8 (root@x4408way2) (gcc version 3.2.2) #1 SMP Thu Aug 21 12:21:15 CDT 2003
Video mode to be used for restore is ffff
BIOS-provided physical RAM map:
BIOS-e820: 0000000000000000 - 000000000009dc00 (usable)
BIOS-e820: 000000000009dc00 - 00000000000a0000 (reserved)
BIOS-e820: 00000000000e0000 - 0000000000100000 (reserved)
BIOS-e820: 0000000000100000 - 00000000dffb6ec0 (usable)
BIOS-e820: 00000000dffb6ec0 - 00000000dffbf800 (ACPI data)
BIOS-e820: 00000000dffbf800 - 00000000e0000000 (reserved)
BIOS-e820: 00000000fec00000 - 0000000100000000 (reserved)
BIOS-e820: 0000000100000000 - 0000000320000000 (usable)
get_memcfg_from_srat: assigning address to rsdp
RSD PTR v0 [IBM ]
Begin table scan....
CPU 0x00 in proximity domain 0x00
CPU 0x02 in proximity domain 0x00
CPU 0x10 in proximity domain 0x00
CPU 0x12 in proximity domain 0x00
CPU 0x20 in proximity domain 0x01
CPU 0x22 in proximity domain 0x01
CPU 0x30 in proximity domain 0x01
CPU 0x32 in proximity domain 0x01
CPU 0x01 in proximity domain 0x00
CPU 0x03 in proximity domain 0x00
CPU 0x11 in proximity domain 0x00
CPU 0x13 in proximity domain 0x00
CPU 0x21 in proximity domain 0x01
CPU 0x23 in proximity domain 0x01
CPU 0x31 in proximity domain 0x01
CPU 0x33 in proximity domain 0x01
Memory range 0x0 to 0xE0000 (type 0x1) in proximity domain 0x00 enabled
Memory range 0x100000 to 0x220000 (type 0x1) in proximity domain 0x00 enabled
Memory range 0x220000 to 0x320000 (type 0x1) in proximity domain 0x01 enabled
acpi20_parse_srat: Entry length value is zero; can't parse any further!
pxm bitmap: 03 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
Number of logical nodes in system = 2
Number of memory chunks in system = 3
chunk 0 nid 0 start_pfn 00000000 end_pfn 000e0000
chunk 1 nid 0 start_pfn 00100000 end_pfn 00220000
chunk 2 nid 1 start_pfn 00220000 end_pfn 00320000
Reserving 11776 pages of KVA for lmem_map of node 1
Shrinking node 1 from 3276800 pages to 3265024 pages
Reserving total of 11776 pages for numa KVA remap
11904MB HIGHMEM available.
850MB LOWMEM available.
min_low_pfn = 1445, max_low_pfn = 217600, highstart_pfn = 229376
Low memory ends at vaddr f5200000
node 0 will remap to vaddr f8000000 - f8000000
node 1 will remap to vaddr f5200000 - f8000000
High memory starts at vaddr f8000000
ACPI: S3 and PAE do not like each other for now, S3 disabled.
found SMP MP-table at 0009dd40
hm, page 0009d000 reserved twice.
hm, page 0009e000 reserved twice.
hm, page 0009e000 reserved twice.
hm, page 0009f000 reserved twice.
On node 0 totalpages: 2097152
DMA zone: 4096 pages, LIFO batch:1
Normal zone: 213504 pages, LIFO batch:16
HighMem zone: 1879552 pages, LIFO batch:16
BUG: wrong zone alignment, it will crash
On node 1 totalpages: 1036800
DMA zone: 0 pages, LIFO batch:1
Normal zone: 0 pages, LIFO batch:1
HighMem zone: 1036800 pages, LIFO batch:16
DMI 2.3 present.
IBM machine detected. Enabling interrupts during APM calls.
IBM machine detected. Disabling SMBus accesses.
IBM eserver xSeries 440 detected: force use of acpi=ht
ACPI: RSDP (v000 IBM ) @ 0x000fdba0
ACPI: RSDT (v001 IBM SERVIGIL 0x00001000 IBM 0x45444f43) @ 0xdffbf780
ACPI: FADT (v001 IBM SERVIGIL 0x00001000 IBM 0x45444f43) @ 0xdffbf700
ACPI: MADT (v001 IBM SERVIGIL 0x00001000 IBM 0x45444f43) @ 0xdffbf580
ACPI: SRAT (v001 IBM SERVIGIL 0x00001000 IBM 0x45444f43) @ 0xdffbf3c0
ACPI: DSDT (v001 IBM SERVIGIL 0x00001000 INTL 0x02002025) @ 0x00000000
ACPI: Local APIC address 0xfee00000
ACPI: LAPIC (acpi_id[0x00] lapic_id[0x00] enabled)
Processor #0 15:1 APIC version 20
ACPI: LAPIC (acpi_id[0x01] lapic_id[0x02] enabled)
Processor #2 15:1 APIC version 20
ACPI: LAPIC (acpi_id[0x02] lapic_id[0x10] enabled)
Processor #16 15:1 APIC version 20
ACPI: LAPIC (acpi_id[0x03] lapic_id[0x12] enabled)
Processor #18 15:1 APIC version 20
ACPI: LAPIC (acpi_id[0x04] lapic_id[0x20] enabled)
Processor #32 15:1 APIC version 20
ACPI: LAPIC (acpi_id[0x05] lapic_id[0x22] enabled)
Processor #34 15:1 APIC version 20
ACPI: LAPIC (acpi_id[0x06] lapic_id[0x30] enabled)
Processor #48 15:1 APIC version 20
ACPI: LAPIC (acpi_id[0x07] lapic_id[0x32] enabled)
Processor #50 15:1 APIC version 20
ACPI: LAPIC (acpi_id[0x08] lapic_id[0x01] enabled)
Processor #1 15:1 APIC version 20
ACPI: LAPIC (acpi_id[0x09] lapic_id[0x03] enabled)
Processor #3 15:1 APIC version 20
ACPI: LAPIC (acpi_id[0x0a] lapic_id[0x11] enabled)
Processor #17 15:1 APIC version 20
ACPI: LAPIC (acpi_id[0x0b] lapic_id[0x13] enabled)
Processor #19 15:1 APIC version 20
ACPI: LAPIC (acpi_id[0x0c] lapic_id[0x21] enabled)
Processor #33 15:1 APIC version 20
ACPI: LAPIC (acpi_id[0x0d] lapic_id[0x23] enabled)
Processor #35 15:1 APIC version 20
ACPI: LAPIC (acpi_id[0x0e] lapic_id[0x31] enabled)
Processor #49 15:1 APIC version 20
ACPI: LAPIC (acpi_id[0x0f] lapic_id[0x33] enabled)
Processor #51 15:1 APIC version 20
ACPI: LAPIC_NMI (acpi_id[0x00] polarity[0x0] trigger[0x0] lint[0x1])
ACPI: LAPIC_NMI (acpi_id[0x01] polarity[0x0] trigger[0x0] lint[0x1])
ACPI: LAPIC_NMI (acpi_id[0x02] polarity[0x0] trigger[0x0] lint[0x1])
ACPI: LAPIC_NMI (acpi_id[0x03] polarity[0x0] trigger[0x0] lint[0x1])
ACPI: LAPIC_NMI (acpi_id[0x04] polarity[0x0] trigger[0x0] lint[0x1])
ACPI: LAPIC_NMI (acpi_id[0x05] polarity[0x0] trigger[0x0] lint[0x1])
ACPI: LAPIC_NMI (acpi_id[0x06] polarity[0x0] trigger[0x0] lint[0x1])
ACPI: LAPIC_NMI (acpi_id[0x07] polarity[0x0] trigger[0x0] lint[0x1])
ACPI: LAPIC_NMI (acpi_id[0x08] polarity[0x0] trigger[0x0] lint[0x1])
ACPI: LAPIC_NMI (acpi_id[0x09] polarity[0x0] trigger[0x0] lint[0x1])
ACPI: LAPIC_NMI (acpi_id[0x0a] polarity[0x0] trigger[0x0] lint[0x1])
ACPI: LAPIC_NMI (acpi_id[0x0b] polarity[0x0] trigger[0x0] lint[0x1])
ACPI: LAPIC_NMI (acpi_id[0x0c] polarity[0x0] trigger[0x0] lint[0x1])
ACPI: LAPIC_NMI (acpi_id[0x0d] polarity[0x0] trigger[0x0] lint[0x1])
ACPI: LAPIC_NMI (acpi_id[0x0e] polarity[0x0] trigger[0x0] lint[0x1])
ACPI: LAPIC_NMI (acpi_id[0x0f] polarity[0x0] trigger[0x0] lint[0x1])
Using ACPI for processor (LAPIC) configuration information
Intel MultiProcessor Specification v1.4
Virtual Wire compatibility mode.
OEM ID: IBM ENSW Product ID: VIGIL SMP APIC at: 0xFEE00000
I/O APIC #14 Version 17 at 0xFEC00000.
I/O APIC #13 Version 17 at 0xFEC01000.
Enabling APIC mode: Summit. Using 2 I/O APICs
Processors: 16
Building zonelist for node : 0
Building zonelist for node : 1
Kernel command line: ro root=/dev/sda7 console=ttyS0,38400n8
Initializing CPU#0
PID hash table entries: 4096 (order 12: 32768 bytes)
Summit chipset: Starting Cyclone Counter.
Detected 1498.538 MHz processor.
Console: colour VGA+ 80x25
Calibrating delay loop... 193.02 BogoMIPS
Initializing highpages for node 0
Initializing highpages for node 1
Memory: 12431384k/13107200k available (3113k kernel code, 102620k reserved, 1120k data, 204k init, 11665112k highmem)
Dentry cache hash table entries: 1048576 (order: 10, 4194304 bytes)
Inode-cache hash table entries: 1048576 (order: 10, 4194304 bytes)
Mount-cache hash table entries: 512 (order: 0, 4096 bytes)
-> /dev
-> /dev/console
-> /root
CPU: After generic identify, caps: 3febfbff 00000000 00000000 00000000
CPU: After vendor identify, caps: 3febfbff 00000000 00000000 00000000
CPU: Trace cache: 12K uops, L1 D cache: 8K
CPU: L2 cache: 256K
CPU: L3 cache: 512K
CPU: Physical Processor ID: 0
CPU: After all inits, caps: 3febfbff 00000000 00000000 00000080
Intel machine check architecture supported.
Intel machine check reporting enabled on CPU#0.
CPU#0: Intel P4/Xeon Extended MCE MSRs (12) available
CPU#0: Thermal monitoring enabled
Enabling fast FPU save and restore... done.
Enabling unmasked SIMD FPU exception support... done.
Checking 'hlt' instruction... OK.
POSIX conformance testing by UNIFIX
CPU0: Intel(R) Genuine CPU 1.50GHz stepping 01
per-CPU timeslice cutoff: 731.48 usecs.
task migration cache decay timeout: 1 msecs.
enabled ExtINT on CPU#0
Leaving ESR disabled.
Mapping cpu 0 to node 0
smp_boot_cpus() bit: 0
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 1
Booting processor 1/2 eip 2000
Initializing CPU#1
masked ExtINT on CPU#1
Leaving ESR disabled.
Mapping cpu 1 to node 0
Calibrating delay loop... 199.16 BogoMIPS
CPU: After generic identify, caps: 3febfbff 00000000 00000000 00000000
CPU: After vendor identify, caps: 3febfbff 00000000 00000000 00000000
CPU: Trace cache: 12K uops, L1 D cache: 8K
CPU: L2 cache: 256K
CPU: L3 cache: 512K
CPU: Physical Processor ID: 1
CPU: After all inits, caps: 3febfbff 00000000 00000000 00000080
Intel machine check architecture supported.
Intel machine check reporting enabled on CPU#1.
CPU#1: Intel P4/Xeon Extended MCE MSRs (12) available
CPU#1: Thermal monitoring enabled
CPU1: Intel(R) Xeon(TM) CPU 1.50GHz stepping 01
smp_boot_cpus() bit: 2
Booting processor 2/16 eip 2000
Initializing CPU#2
masked ExtINT on CPU#2
Leaving ESR disabled.
Mapping cpu 2 to node 0
Calibrating delay loop... 199.16 BogoMIPS
CPU: After generic identify, caps: 3febfbff 00000000 00000000 00000000
CPU: After vendor identify, caps: 3febfbff 00000000 00000000 00000000
CPU: Trace cache: 12K uops, L1 D cache: 8K
CPU: L2 cache: 256K
CPU: L3 cache: 512K
CPU: Physical Processor ID: 2
CPU: After all inits, caps: 3febfbff 00000000 00000000 00000080
Intel machine check architecture supported.
Intel machine check reporting enabled on CPU#2.
CPU#2: Intel P4/Xeon Extended MCE MSRs (12) available
CPU#2: Thermal monitoring enabled
CPU2: Intel(R) Xeon(TM) CPU 1.50GHz stepping 01
smp_boot_cpus() bit: 3
Booting processor 3/18 eip 2000
Initializing CPU#3
masked ExtINT on CPU#3
Leaving ESR disabled.
Mapping cpu 3 to node 0
Calibrating delay loop... 199.16 BogoMIPS
CPU: After generic identify, caps: 3febfbff 00000000 00000000 00000000
CPU: After vendor identify, caps: 3febfbff 00000000 00000000 00000000
CPU: Trace cache: 12K uops, L1 D cache: 8K
CPU: L2 cache: 256K
CPU: L3 cache: 512K
CPU: Physical Processor ID: 3
CPU: After all inits, caps: 3febfbff 00000000 00000000 00000080
Intel machine check architecture supported.
Intel machine check reporting enabled on CPU#3.
CPU#3: Intel P4/Xeon Extended MCE MSRs (12) available
CPU#3: Thermal monitoring enabled
CPU3: Intel(R) Xeon(TM) CPU 1.50GHz stepping 01
smp_boot_cpus() bit: 4
Booting processor 4/32 eip 2000
Initializing CPU#4
masked ExtINT on CPU#4
Leaving ESR disabled.
Mapping cpu 4 to node 1
Calibrating delay loop... 199.16 BogoMIPS
CPU: After generic identify, caps: 3febfbff 00000000 00000000 00000000
CPU: After vendor identify, caps: 3febfbff 00000000 00000000 00000000
CPU: Trace cache: 12K uops, L1 D cache: 8K
CPU: L2 cache: 256K
CPU: L3 cache: 512K
CPU: Physical Processor ID: 8
CPU: After all inits, caps: 3febfbff 00000000 00000000 00000080
Intel machine check architecture supported.
Intel machine check reporting enabled on CPU#4.
CPU#4: Intel P4/Xeon Extended MCE MSRs (12) available
CPU#4: Thermal monitoring enabled
CPU4: Intel(R) Genuine CPU 1.50GHz stepping 01
smp_boot_cpus() bit: 5
Booting processor 5/34 eip 2000
Initializing CPU#5
masked ExtINT on CPU#5
Leaving ESR disabled.
Mapping cpu 5 to node 1
Calibrating delay loop... 198.65 BogoMIPS
CPU: After generic identify, caps: 3febfbff 00000000 00000000 00000000
CPU: After vendor identify, caps: 3febfbff 00000000 00000000 00000000
CPU: Trace cache: 12K uops, L1 D cache: 8K
CPU: L2 cache: 256K
CPU: L3 cache: 512K
CPU: Physical Processor ID: 9
CPU: After all inits, caps: 3febfbff 00000000 00000000 00000080
Intel machine check architecture supported.
Intel machine check reporting enabled on CPU#5.
CPU#5: Intel P4/Xeon Extended MCE MSRs (12) available
CPU#5: Thermal monitoring enabled
CPU5: Intel(R) Xeon(TM) CPU 1.50GHz stepping 01
smp_boot_cpus() bit: 6
Booting processor 6/48 eip 2000
Initializing CPU#6
masked ExtINT on CPU#6
Leaving ESR disabled.
Mapping cpu 6 to node 1
Calibrating delay loop... 199.16 BogoMIPS
CPU: After generic identify, caps: 3febfbff 00000000 00000000 00000000
CPU: After vendor identify, caps: 3febfbff 00000000 00000000 00000000
CPU: Trace cache: 12K uops, L1 D cache: 8K
CPU: L2 cache: 256K
CPU: L3 cache: 512K
CPU: Physical Processor ID: 10
CPU: After all inits, caps: 3febfbff 00000000 00000000 00000080
Intel machine check architecture supported.
Intel machine check reporting enabled on CPU#6.
CPU#6: Intel P4/Xeon Extended MCE MSRs (12) available
CPU#6: Thermal monitoring enabled
CPU6: Intel(R) Xeon(TM) CPU 1.50GHz stepping 01
smp_boot_cpus() bit: 7
Booting processor 7/50 eip 2000
Initializing CPU#7
masked ExtINT on CPU#7
Leaving ESR disabled.
Mapping cpu 7 to node 1
Calibrating delay loop... 198.65 BogoMIPS
CPU: After generic identify, caps: 3febfbff 00000000 00000000 00000000
CPU: After vendor identify, caps: 3febfbff 00000000 00000000 00000000
CPU: Trace cache: 12K uops, L1 D cache: 8K
CPU: L2 cache: 256K
CPU: L3 cache: 512K
CPU: Physical Processor ID: 11
CPU: After all inits, caps: 3febfbff 00000000 00000000 00000080
Intel machine check architecture supported.
Intel machine check reporting enabled on CPU#7.
CPU#7: Intel P4/Xeon Extended MCE MSRs (12) available
CPU#7: Thermal monitoring enabled
CPU7: Intel(R) Xeon(TM) CPU 1.50GHz stepping 01
smp_boot_cpus() bit: 8
Booting processor 8/1 eip 2000
Initializing CPU#8
masked ExtINT on CPU#8
Leaving ESR disabled.
Mapping cpu 8 to node 0
Calibrating delay loop... 199.16 BogoMIPS
CPU: After generic identify, caps: 3febfbff 00000000 00000000 00000000
CPU: After vendor identify, caps: 3febfbff 00000000 00000000 00000000
CPU: Trace cache: 12K uops, L1 D cache: 8K
CPU: L2 cache: 256K
CPU: L3 cache: 512K
CPU: Physical Processor ID: 0
CPU: After all inits, caps: 3febfbff 00000000 00000000 00000080
Intel machine check architecture supported.
Intel machine check reporting enabled on CPU#8.
CPU#8: Intel P4/Xeon Extended MCE MSRs (12) available
CPU#8: Thermal monitoring enabled
CPU8: Intel(R) Genuine CPU 1.50GHz stepping 01
smp_boot_cpus() bit: 9
Booting processor 9/3 eip 2000
Initializing CPU#9
masked ExtINT on CPU#9
Leaving ESR disabled.
Mapping cpu 9 to node 0
Calibrating delay loop... 199.16 BogoMIPS
CPU: After generic identify, caps: 3febfbff 00000000 00000000 00000000
CPU: After vendor identify, caps: 3febfbff 00000000 00000000 00000000
CPU: Trace cache: 12K uops, L1 D cache: 8K
CPU: L2 cache: 256K
CPU: L3 cache: 512K
CPU: Physical Processor ID: 1
CPU: After all inits, caps: 3febfbff 00000000 00000000 00000080
Intel machine check architecture supported.
Intel machine check reporting enabled on CPU#9.
CPU#9: Intel P4/Xeon Extended MCE MSRs (12) available
CPU#9: Thermal monitoring enabled
CPU9: Intel(R) Xeon(TM) CPU 1.50GHz stepping 01
smp_boot_cpus() bit: 10
Booting processor 10/17 eip 2000
Initializing CPU#10
masked ExtINT on CPU#10
Leaving ESR disabled.
Mapping cpu 10 to node 0
Calibrating delay loop... 199.16 BogoMIPS
CPU: After generic identify, caps: 3febfbff 00000000 00000000 00000000
CPU: After vendor identify, caps: 3febfbff 00000000 00000000 00000000
CPU: Trace cache: 12K uops, L1 D cache: 8K
CPU: L2 cache: 256K
CPU: L3 cache: 512K
CPU: Physical Processor ID: 2
CPU: After all inits, caps: 3febfbff 00000000 00000000 00000080
Intel machine check architecture supported.
Intel machine check reporting enabled on CPU#10.
CPU#10: Intel P4/Xeon Extended MCE MSRs (12) available
CPU#10: Thermal monitoring enabled
CPU10: Intel(R) Xeon(TM) CPU 1.50GHz stepping 01
smp_boot_cpus() bit: 11
Booting processor 11/19 eip 2000
Initializing CPU#11
masked ExtINT on CPU#11
Leaving ESR disabled.
Mapping cpu 11 to node 0
Calibrating delay loop... 199.16 BogoMIPS
CPU: After generic identify, caps: 3febfbff 00000000 00000000 00000000
CPU: After vendor identify, caps: 3febfbff 00000000 00000000 00000000
CPU: Trace cache: 12K uops, L1 D cache: 8K
CPU: L2 cache: 256K
CPU: L3 cache: 512K
CPU: Physical Processor ID: 3
CPU: After all inits, caps: 3febfbff 00000000 00000000 00000080
Intel machine check architecture supported.
Intel machine check reporting enabled on CPU#11.
CPU#11: Intel P4/Xeon Extended MCE MSRs (12) available
CPU#11: Thermal monitoring enabled
CPU11: Intel(R) Xeon(TM) CPU 1.50GHz stepping 01
smp_boot_cpus() bit: 12
Booting processor 12/33 eip 2000
Initializing CPU#12
masked ExtINT on CPU#12
Leaving ESR disabled.
Mapping cpu 12 to node 1
Calibrating delay loop... 198.65 BogoMIPS
CPU: After generic identify, caps: 3febfbff 00000000 00000000 00000000
CPU: After vendor identify, caps: 3febfbff 00000000 00000000 00000000
CPU: Trace cache: 12K uops, L1 D cache: 8K
CPU: L2 cache: 256K
CPU: L3 cache: 512K
CPU: Physical Processor ID: 8
CPU: After all inits, caps: 3febfbff 00000000 00000000 00000080
Intel machine check architecture supported.
Intel machine check reporting enabled on CPU#12.
CPU#12: Intel P4/Xeon Extended MCE MSRs (12) available
CPU#12: Thermal monitoring enabled
CPU12: Intel(R) Genuine CPU 1.50GHz stepping 01
smp_boot_cpus() bit: 13
Booting processor 13/35 eip 2000
Initializing CPU#13
masked ExtINT on CPU#13
Leaving ESR disabled.
Mapping cpu 13 to node 1
Calibrating delay loop... 198.65 BogoMIPS
CPU: After generic identify, caps: 3febfbff 00000000 00000000 00000000
CPU: After vendor identify, caps: 3febfbff 00000000 00000000 00000000
CPU: Trace cache: 12K uops, L1 D cache: 8K
CPU: L2 cache: 256K
CPU: L3 cache: 512K
CPU: Physical Processor ID: 9
CPU: After all inits, caps: 3febfbff 00000000 00000000 00000080
Intel machine check architecture supported.
Intel machine check reporting enabled on CPU#13.
CPU#13: Intel P4/Xeon Extended MCE MSRs (12) available
CPU#13: Thermal monitoring enabled
CPU13: Intel(R) Xeon(TM) CPU 1.50GHz stepping 01
smp_boot_cpus() bit: 14
Booting processor 14/49 eip 2000
Initializing CPU#14
masked ExtINT on CPU#14
Leaving ESR disabled.
Mapping cpu 14 to node 1
Calibrating delay loop... 198.65 BogoMIPS
CPU: After generic identify, caps: 3febfbff 00000000 00000000 00000000
CPU: After vendor identify, caps: 3febfbff 00000000 00000000 00000000
CPU: Trace cache: 12K uops, L1 D cache: 8K
CPU: L2 cache: 256K
CPU: L3 cache: 512K
CPU: Physical Processor ID: 10
CPU: After all inits, caps: 3febfbff 00000000 00000000 00000080
Intel machine check architecture supported.
Intel machine check reporting enabled on CPU#14.
CPU#14: Intel P4/Xeon Extended MCE MSRs (12) available
CPU#14: Thermal monitoring enabled
CPU14: Intel(R) Xeon(TM) CPU 1.50GHz stepping 01
smp_boot_cpus() bit: 15
Booting processor 15/51 eip 2000
Initializing CPU#15
masked ExtINT on CPU#15
Leaving ESR disabled.
Mapping cpu 15 to node 1
Calibrating delay loop... 199.16 BogoMIPS
CPU: After generic identify, caps: 3febfbff 00000000 00000000 00000000
CPU: After vendor identify, caps: 3febfbff 00000000 00000000 00000000
CPU: Trace cache: 12K uops, L1 D cache: 8K
CPU: L2 cache: 256K
CPU: L3 cache: 512K
CPU: Physical Processor ID: 11
CPU: After all inits, caps: 3febfbff 00000000 00000000 00000080
Intel machine check architecture supported.
Intel machine check reporting enabled on CPU#15.
CPU#15: Intel P4/Xeon Extended MCE MSRs (12) available
CPU#15: Thermal monitoring enabled
CPU15: Intel(R) Xeon(TM) CPU 1.50GHz stepping 01
Total of 16 processors activated (3177.98 BogoMIPS).
cpu_sibling_map[0] = 8
cpu_sibling_map[1] = 9
cpu_sibling_map[2] = 10
cpu_sibling_map[3] = 11
cpu_sibling_map[4] = 12
cpu_sibling_map[5] = 13
cpu_sibling_map[6] = 14
cpu_sibling_map[7] = 15
cpu_sibling_map[8] = 0
cpu_sibling_map[9] = 1
cpu_sibling_map[10] = 2
cpu_sibling_map[11] = 3
cpu_sibling_map[12] = 4
cpu_sibling_map[13] = 5
cpu_sibling_map[14] = 6
cpu_sibling_map[15] = 7
ENABLING IO-APIC IRQs
Setting 14 in the phys_id_present_map
...changing IO-APIC physical APIC ID to 14 ... ok.
Setting 13 in the phys_id_present_map
...changing IO-APIC physical APIC ID to 13 ... ok.
init IO_APIC IRQs
IO-APIC (apicid-pin) 14-2, 14-3, 14-5, 14-7, 14-9, 14-10, 14-11, 14-15, 14-17, 14-20, 14-21, 14-22, 14-23, 14-24, 14-25, 14-26, 14-27, 14-28, 14-29, 14-30, 14-31, 14-32, 14-33, 14-34, 14-35, 14-36, 14-37, 14-38, 14-43, 14-44, 14-45, 14-46, 14-47, 14-48, 14-49, 14-50, 13-24, 13-25, 13-26, 13-27, 13-28, 13-29, 13-30, 13-31, 13-32, 13-33, 13-34, 13-35, 13-36, 13-37, 13-38, 13-39, 13-40, 13-41, 13-42, 13-43, 13-44, 13-45, 13-46, 13-47, 13-48, 13-49, 13-50 not connected.
..TIMER: vector=0x31 pin1=0 pin2=-1
number of MP IRQ sources: 39.
number of IO-APIC #14 registers: 51.
number of IO-APIC #13 registers: 51.
testing the IO APIC.......................
IO APIC #14......
.... register #00: 0E000000
....... : physical APIC id: 0E
....... : Delivery Type: 0
....... : LTS : 0
.... register #01: 00320011
....... : max redirection entries: 0032
....... : PRQ implemented: 0
....... : IO APIC version: 0011
.... register #02: 00000000
....... : arbitration: 00
.... IRQ redirection table:
NR Log Phy Mask Trig IRR Pol Stat Dest Deli Vect:
00 0FF 0F 0 0 0 0 0 1 0 31
01 0FF 0F 0 0 0 0 0 1 0 39
02 000 00 1 0 0 0 0 0 0 00
03 000 00 1 0 0 0 0 0 0 00
04 0FF 0F 0 0 0 0 0 1 0 41
05 000 00 1 0 0 0 0 0 0 00
06 0FF 0F 0 0 0 0 0 1 0 49
07 000 00 1 0 0 0 0 0 0 00
08 0FF 0F 0 0 0 1 0 1 0 51
09 000 00 1 0 0 0 0 0 0 00
0a 000 00 1 0 0 0 0 0 0 00
0b 000 00 1 0 0 0 0 0 0 00
0c 0FF 0F 0 0 0 0 0 1 0 59
0d 0FF 0F 0 0 0 0 0 1 0 61
0e 0FF 0F 0 0 0 0 0 1 0 69
0f 000 00 1 0 0 0 0 0 0 00
10 0FF 0F 1 1 0 1 0 1 0 71
11 000 00 1 0 0 0 0 0 0 00
12 0FF 0F 1 1 0 1 0 1 0 79
13 0FF 0F 1 1 0 1 0 1 0 81
14 000 00 1 0 0 0 0 0 0 00
15 000 00 1 0 0 0 0 0 0 00
16 000 00 1 0 0 0 0 0 0 00
17 000 00 1 0 0 0 0 0 0 00
18 000 00 1 0 0 0 0 0 0 00
19 000 00 1 0 0 0 0 0 0 00
1a 000 00 1 0 0 0 0 0 0 00
1b 000 00 1 0 0 0 0 0 0 00
1c 000 00 1 0 0 0 0 0 0 00
1d 000 00 1 0 0 0 0 0 0 00
1e 000 00 1 0 0 0 0 0 0 00
1f 000 00 1 0 0 0 0 0 0 00
20 000 00 1 0 0 0 0 0 0 00
21 000 00 1 0 0 0 0 0 0 00
22 000 00 1 0 0 0 0 0 0 00
23 000 00 1 0 0 0 0 0 0 00
24 000 00 1 0 0 0 0 0 0 00
25 000 00 1 0 0 0 0 0 0 00
26 000 00 1 0 0 0 0 0 0 00
27 0FF 0F 1 1 0 1 0 1 0 89
28 0FF 0F 1 1 0 1 0 1 0 91
29 0FF 0F 1 1 0 1 0 1 0 99
2a 0FF 0F 1 1 0 1 0 1 0 A1
2b 000 00 1 0 0 0 0 0 0 00
2c 000 00 1 0 0 0 0 0 0 00
2d 000 00 1 0 0 0 0 0 0 00
2e 000 00 1 0 0 0 0 0 0 00
2f 000 00 1 0 0 0 0 0 0 00
30 000 00 1 0 0 0 0 0 0 00
31 000 00 1 0 0 0 0 0 0 00
32 000 00 1 0 0 0 0 0 0 00
IO APIC #13......
.... register #00: 0D000000
....... : physical APIC id: 0D
....... : Delivery Type: 0
....... : LTS : 0
.... register #01: 00320011
....... : max redirection entries: 0032
....... : PRQ implemented: 0
....... : IO APIC version: 0011
.... register #02: 00000000
....... : arbitration: 00
.... IRQ redirection table:
NR Log Phy Mask Trig IRR Pol Stat Dest Deli Vect:
00 0FF 0F 1 1 0 1 0 1 0 A9
01 0FF 0F 1 1 0 1 0 1 0 B1
02 0FF 0F 1 1 0 1 0 1 0 B9
03 0FF 0F 1 1 0 1 0 1 0 C1
04 0FF 0F 1 1 0 1 0 1 0 C9
05 0FF 0F 1 1 0 1 0 1 0 D1
06 0FF 0F 1 1 0 1 0 1 0 D9
07 0FF 0F 1 1 0 1 0 1 0 E1
08 0FF 0F 1 1 0 1 0 1 0 E9
09 0FF 0F 1 1 0 1 0 1 0 32
0a 0FF 0F 1 1 0 1 0 1 0 3A
0b 0FF 0F 1 1 0 1 0 1 0 42
0c 0FF 0F 1 1 0 1 0 1 0 4A
0d 0FF 0F 1 1 0 1 0 1 0 52
0e 0FF 0F 1 1 0 1 0 1 0 5A
0f 0FF 0F 1 1 0 1 0 1 0 62
10 0FF 0F 1 1 0 1 0 1 0 6A
11 0FF 0F 1 1 0 1 0 1 0 72
12 0FF 0F 1 1 0 1 0 1 0 7A
13 0FF 0F 1 1 0 1 0 1 0 82
14 0FF 0F 1 1 0 1 0 1 0 8A
15 0FF 0F 1 1 0 1 0 1 0 92
16 0FF 0F 1 1 0 1 0 1 0 9A
17 0FF 0F 1 1 0 1 0 1 0 A2
18 000 00 1 0 0 0 0 0 0 00
19 000 00 1 0 0 0 0 0 0 00
1a 000 00 1 0 0 0 0 0 0 00
1b 000 00 1 0 0 0 0 0 0 00
1c 000 00 1 0 0 0 0 0 0 00
1d 000 00 1 0 0 0 0 0 0 00
1e 000 00 1 0 0 0 0 0 0 00
1f 000 00 1 0 0 0 0 0 0 00
20 000 00 1 0 0 0 0 0 0 00
21 000 00 1 0 0 0 0 0 0 00
22 000 00 1 0 0 0 0 0 0 00
23 000 00 1 0 0 0 0 0 0 00
24 000 00 1 0 0 0 0 0 0 00
25 000 00 1 0 0 0 0 0 0 00
26 000 00 1 0 0 0 0 0 0 00
27 000 00 1 0 0 0 0 0 0 00
28 000 00 1 0 0 0 0 0 0 00
29 000 00 1 0 0 0 0 0 0 00
2a 000 00 1 0 0 0 0 0 0 00
2b 000 00 1 0 0 0 0 0 0 00
2c 000 00 1 0 0 0 0 0 0 00
2d 000 00 1 0 0 0 0 0 0 00
2e 000 00 1 0 0 0 0 0 0 00
2f 000 00 1 0 0 0 0 0 0 00
30 000 00 1 0 0 0 0 0 0 00
31 000 00 1 0 0 0 0 0 0 00
32 000 00 1 0 0 0 0 0 0 00
IRQ to pin mappings:
IRQ0 -> 0:0
IRQ1 -> 0:1
IRQ4 -> 0:4
IRQ6 -> 0:6
IRQ8 -> 0:8
IRQ12 -> 0:12
IRQ13 -> 0:13
IRQ14 -> 0:14
IRQ16 -> 0:16
IRQ18 -> 0:18
IRQ19 -> 0:19
IRQ39 -> 0:39
IRQ40 -> 0:40
IRQ41 -> 0:41
IRQ42 -> 0:42
IRQ51 -> 1:0
IRQ52 -> 1:1
IRQ53 -> 1:2
IRQ54 -> 1:3
IRQ55 -> 1:4
IRQ56 -> 1:5
IRQ57 -> 1:6
IRQ58 -> 1:7
IRQ59 -> 1:8
IRQ60 -> 1:9
IRQ61 -> 1:10
IRQ62 -> 1:11
IRQ63 -> 1:12
IRQ64 -> 1:13
IRQ65 -> 1:14
IRQ66 -> 1:15
IRQ67 -> 1:16
IRQ68 -> 1:17
IRQ69 -> 1:18
IRQ70 -> 1:19
IRQ71 -> 1:20
IRQ72 -> 1:21
IRQ73 -> 1:22
IRQ74 -> 1:23
.................................... done.
Using local APIC timer interrupts.
calibrating APIC timer ...
..... CPU clock speed is 1496.0636 MHz.
..... host bus clock speed is 99.0775 MHz.
checking TSC synchronization across 16 CPUs:
BIOS BUG: CPU#0 improperly initialized, has 7903467 usecs TSC skew! FIXED.
BIOS BUG: CPU#1 improperly initialized, has 7903467 usecs TSC skew! FIXED.
BIOS BUG: CPU#2 improperly initialized, has 7903473 usecs TSC skew! FIXED.
BIOS BUG: CPU#3 improperly initialized, has 7903467 usecs TSC skew! FIXED.
BIOS BUG: CPU#4 improperly initialized, has -7903467 usecs TSC skew! FIXED.
BIOS BUG: CPU#5 improperly initialized, has -7903467 usecs TSC skew! FIXED.
BIOS BUG: CPU#6 improperly initialized, has -7903468 usecs TSC skew! FIXED.
BIOS BUG: CPU#7 improperly initialized, has -7903468 usecs TSC skew! FIXED.
BIOS BUG: CPU#8 improperly initialized, has 7903467 usecs TSC skew! FIXED.
BIOS BUG: CPU#9 improperly initialized, has 7903467 usecs TSC skew! FIXED.
BIOS BUG: CPU#10 improperly initialized, has 7903468 usecs TSC skew! FIXED.
BIOS BUG: CPU#11 improperly initialized, has 7903467 usecs TSC skew! FIXED.
BIOS BUG: CPU#12 improperly initialized, has -7903467 usecs TSC skew! FIXED.
BIOS BUG: CPU#13 improperly initialized, has -7903470 usecs TSC skew! FIXED.
BIOS BUG: CPU#14 improperly initialized, has -7903468 usecs TSC skew! FIXED.
BIOS BUG: CPU#15 improperly initialized, has -7903468 usecs TSC skew! FIXED.
Starting migration thread for cpu 0
Bringing up 1
CPU 1 IS NOW UP!
Starting migration thread for cpu 1
Bringing up 2
CPU 2 IS NOW UP!
Starting migration thread for cpu 2
Bringing up 3
CPU 3 IS NOW UP!
Starting migration thread for cpu 3
Bringing up 4
CPU 4 IS NOW UP!
Starting migration thread for cpu 4
Bringing up 5
CPU 5 IS NOW UP!
Starting migration thread for cpu 5
Bringing up 6
CPU 6 IS NOW UP!
Starting migration thread for cpu 6
Bringing up 7
CPU 7 IS NOW UP!
Starting migration thread for cpu 7
Bringing up 8
CPU 8 IS NOW UP!
Starting migration thread for cpu 8
Bringing up 9
CPU 9 IS NOW UP!
Starting migration thread for cpu 9
Bringing up 10
CPU 10 IS NOW UP!
Starting migration thread for cpu 10
Bringing up 11
CPU 11 IS NOW UP!
Starting migration thread for cpu 11
Bringing up 12
CPU 12 IS NOW UP!
Starting migration thread for cpu 12
Bringing up 13
CPU 13 IS NOW UP!
Starting migration thread for cpu 13
Bringing up 14
CPU 14 IS NOW UP!
Starting migration thread for cpu 14
Bringing up 15
CPU 15 IS NOW UP!
Starting migration thread for cpu 15
CPUS done 32
PM: Adding info for No Bus:legacy
Initializing RT netlink socket
PCI: PCI BIOS revision 2.10 entry at 0xfd30d, last bus=11
PCI: Using configuration type 1
mtrr: v2.0 (20020519)
BIO: pool of 256 setup, 15Kb (60 bytes/bio)
biovec pool[0]: 1 bvecs: 256 entries (12 bytes)
biovec pool[1]: 4 bvecs: 256 entries (48 bytes)
biovec pool[2]: 16 bvecs: 256 entries (192 bytes)
biovec pool[3]: 64 bvecs: 256 entries (768 bytes)
biovec pool[4]: 128 bvecs: 256 entries (1536 bytes)
biovec pool[5]: 256 bvecs: 256 entries (3072 bytes)
ACPI: Subsystem revision 20030813
ACPI: Interpreter disabled.
Linux Plug and Play Support v0.97 (c) Adam Belay
SCSI subsystem initialized
Linux Kernel Card Services 3.1.22
options: [pci] [pm]
ACPI: ACPI tables contain no PCI IRQ routing entries
PCI: Invalid ACPI-PCI IRQ routing table
PCI: Probing PCI hardware
PCI: Probing PCI hardware (bus 00)
PM: Adding info for No Bus:pci0000:00
PM: Adding info for pci:0000:00:00.0
PM: Adding info for pci:0000:00:03.0
PM: Adding info for pci:0000:00:04.0
PM: Adding info for pci:0000:00:05.0
PM: Adding info for pci:0000:00:05.1
PM: Adding info for pci:0000:00:05.2
PM: Adding info for pci:0000:00:05.3
PM: Adding info for pci:0000:00:05.4
PCI: Discovered peer bus 01
PM: Adding info for No Bus:pci0000:01
PM: Adding info for pci:0000:01:00.0
PM: Adding info for pci:0000:01:03.0
PM: Adding info for pci:0000:01:03.1
PM: Adding info for pci:0000:01:04.0
PCI: Discovered peer bus 02
PM: Adding info for No Bus:pci0000:02
PM: Adding info for pci:0000:02:00.0
PCI: Discovered peer bus 05
PM: Adding info for No Bus:pci0000:05
PM: Adding info for pci:0000:05:00.0
PCI: Discovered peer bus 07
PM: Adding info for No Bus:pci0000:07
PM: Adding info for pci:0000:07:00.0
PCI: Discovered peer bus 09
PM: Adding info for No Bus:pci0000:09
PM: Adding info for pci:0000:09:00.0
PCI->APIC IRQ transform: (B0,I3,P0) -> 39
PCI->APIC IRQ transform: (B0,I4,P0) -> 16
PCI->APIC IRQ transform: (B0,I5,P3) -> 18
PCI->APIC IRQ transform: (B0,I5,P3) -> 18
PCI->APIC IRQ transform: (B1,I3,P0) -> 40
PCI->APIC IRQ transform: (B1,I3,P1) -> 41
PCI->APIC IRQ transform: (B1,I4,P0) -> 42
pty: 256 Unix98 ptys configured
Starting balanced_irq
Total HugeTLB memory allocated, 0
ikconfig 0.5 with /proc/ikconfig
highmem bounce pool size: 64 pages
Journalled Block Device driver loaded
Installing knfsd (copyright (C) 1996 okir@monad.swb.de).
udf: registering filesystem
SGI XFS for Linux with no debug enabled
PCI: Enabling Via external APIC routing
PCI: Via IRQ fixup for 0000:00:05.2, from 7 to 2
PCI: Via IRQ fixup for 0000:00:05.3, from 7 to 2
request_module: failed /sbin/modprobe -- parport_lowlevel. error = -16
lp: driver loaded but no devices found
Serial: 8250/16550 driver $Revision: 1.90 $ IRQ sharing disabled
ttyS0 at I/O 0x3f8 (irq = 4) is a 16550A
parport_pc: Via 686A parallel port disabled in BIOS
Using anticipatory scheduling elevator
Floppy drive(s): fd0 is 1.44M
reset set in interrupt, calling c0326f91
floppy0: no floppy controllers found
RAMDISK driver initialized: 16 RAM disks of 4096K size 1024 blocksize
loop: loaded (max 8 devices)
Intel(R) PRO/1000 Network Driver - version 5.1.13-k2
Copyright (c) 1999-2003 Intel Corporation.
tg3.c:v1.9 (August 3, 2003)
eth0: Tigon3 [partno(BCM95700A6) rev 7102 PHY(5401)] (PCI:66MHz:64-bit) 10/100/1000BaseT Ethernet 00:02:55:dc:0e:32
Uniform Multi-Platform E-IDE driver Revision: 7.00alpha2
ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx
hda: LG CD-ROM CRN-8245B, ATAPI CD/DVD-ROM drive
PM: Adding info for No Bus:ide0
ide0 at 0x1f0-0x1f7,0x3f6 on irq 14
PM: Adding info for ide:0.0
hda: ATAPI 24X CD-ROM drive, 128kB Cache
Uniform CD-ROM driver Revision: 3.12
scsi0 : Adaptec AIC7XXX EISA/VLB/PCI SCSI HBA DRIVER, Rev 6.2.35
<Adaptec aic7899 Ultra160 SCSI adapter>
aic7899: Ultra160 Wide Channel A, SCSI Id=7, 32/253 SCBs
PM: Adding info for No Bus:host0
scsi1 : Adaptec AIC7XXX EISA/VLB/PCI SCSI HBA DRIVER, Rev 6.2.35
<Adaptec aic7899 Ultra160 SCSI adapter>
aic7899: Ultra160 Wide Channel B, SCSI Id=7, 32/253 SCBs
PM: Adding info for No Bus:host1
(scsi1:A:12): 160.000MB/s transfers (80.000MHz DT, offset 63, 16bit)
Vendor: IBM Model: GNHv1 S2 Rev: 0
Type: Processor ANSI SCSI revision: 02
PM: Adding info for scsi:1:0:9:0
Vendor: IBM-PSG Model: DPSS-336950M M Rev: S9HA
Type: Direct-Access ANSI SCSI revision: 03
scsi1:A:12:0: Tagged Queuing enabled. Depth 64
PM: Adding info for scsi:1:0:12:0
SCSI device sda: 71096640 512-byte hdwr sectors (36401 MB)
SCSI device sda: drive cache: write through
sda: sda1 sda2 sda3 sda4 < sda5 sda6 sda7 sda8 sda9 sda10 >
Attached scsi disk sda at scsi1, channel 0, id 12, lun 0
Attached scsi generic sg0 at scsi1, channel 0, id 9, lun 0, type 3
Attached scsi generic sg1 at scsi1, channel 0, id 12, lun 0, type 0
mice: PS/2 mouse device common for all mice
input: ImPS/2 Logitech Wheel Mouse on isa0060/serio1
serio: i8042 AUX port at 0x60,0x64 irq 12
input: AT Set 2 keyboard on isa0060/serio0
serio: i8042 KBD port at 0x60,0x64 irq 1
NET4: Linux TCP/IP 1.0 for NET4.0
IP: routing cache hash table of 131072 buckets, 1024Kbytes
TCP: Hash tables configured (established 524288 bind 65536)
NET4: Unix domain sockets 1.0/SMP for Linux NET4.0.
BIOS EDD facility v0.09 2003-Jan-22, 1 devices found
found reiserfs format "3.6" with standard journal
Reiserfs journal params: device sda7, size 8192, journal first block 18, max trans len 1024, max batch 900, max commit age 30, max trans age 30
reiserfs: checking transaction log (sda7) for (sda7)
Using r5 hash to sort names
VFS: Mounted root (reiserfs filesystem) readonly.
Freeing unused kernel memory: 204k freed
Adding 2097136k swap on /dev/sda10. Priority:42 extents:1
kjournald starting. Commit interval 5 seconds
EXT3 FS on sda3, internal journal
EXT3-fs: mounted filesystem with ordered data mode.
kjournald starting. Commit interval 5 seconds
EXT3 FS on sda1, internal journal
EXT3-fs: mounted filesystem with ordered data mode.
kjournald starting. Commit interval 5 seconds
EXT3 FS on sda2, internal journal
EXT3-fs: mounted filesystem with ordered data mode.
tg3: eth0: Link is up at 100 Mbps, half duplex.
tg3: eth0: Flow control is off for TX and off for RX.
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: CPU boot problem on 2.6.0-test3-bk8
2003-08-21 15:56 ` Andrew Theurer
@ 2003-08-21 16:09 ` Dave Hansen
2003-08-21 17:02 ` Andrew Theurer
0 siblings, 1 reply; 19+ messages in thread
From: Dave Hansen @ 2003-08-21 16:09 UTC (permalink / raw)
To: Andrew Theurer
Cc: linux-kernel, William Lee Irwin III, Andrew Morton, Martin J. Bligh
On Thu, 2003-08-21 at 08:56, Andrew Theurer wrote:
> On Thursday 21 August 2003 09:58, Dave Hansen wrote:
> > On Thu, 2003-08-21 at 07:10, Andrew Theurer wrote:
> > > So we only loop for the actual number processors found in mpparse.c?
> > > This seems to work for me.
> >
> > I think there's a reason it was done that way. I think your patch
> > breaks the visws subarch, too.
> >
> > Could you mark up that loop a bit and printk a bit, so we can see which
> > continue you're missing?
> >
> > <pasting patch lazily in email because I can't be bothered to actually copy
> > it from the machine I"m working on> diff -urp
> > linux-2.6.0-test3-clean/arch/i386/kernel/smpboot.c
> > linux-2.6.0-test3-work/arch/i386/kernel/smpboot.c ---
> > linux-2.6.0-test3-clean/arch/i386/kernel/smpboot.c Wed Aug 20 19:54:29
> > 2003 +++ linux-2.6.0-test3-work/arch/i386/kernel/smpboot.c Wed Aug 20
> > 20:19:41 2003 @@ -1020,24 +1020,30 @@ static void __init
> > smp_boot_cpus(unsigne
> > Dprintk("CPU present map: %lx\n",
> > physids_coerce(phys_cpu_present_map));
> >
> > kicked = 1;
> > - for (bit = 0; kicked < NR_CPUS && bit < MAX_APICS; bit++) {
> > + for (bit = 0; kicked < NR_CPUS && bit < MAX_APICS; bit++, kicked++)
>
> This patch (plus your first one) seems to work. Perhaps the addition of
> kicked++ above helped? Attached is the boot log.
I missed that. But, it's incorrect. You're doubly incrementing kicked
in the case of CPUs that are booted correctly and getting to kicked >=
NR_CPUS a lot quicker. That's why you're booting correctly.
Secondly, we can actually boot up to NR_CPUS cpus, and we can *fail* to
boot a lot more than that. At least that's what the code is trying to
do. Whether it is "the right thing" is debatable.
--
Dave Hansen
haveblue@us.ibm.com
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: CPU boot problem on 2.6.0-test3-bk8
2003-08-21 16:09 ` Dave Hansen
@ 2003-08-21 17:02 ` Andrew Theurer
2003-08-21 21:13 ` William Lee Irwin III
` (2 more replies)
0 siblings, 3 replies; 19+ messages in thread
From: Andrew Theurer @ 2003-08-21 17:02 UTC (permalink / raw)
To: Dave Hansen
Cc: linux-kernel, William Lee Irwin III, Andrew Morton, Martin J. Bligh
[-- Attachment #1: Type: text/plain, Size: 1945 bytes --]
On Thursday 21 August 2003 11:09, Dave Hansen wrote:
> On Thu, 2003-08-21 at 08:56, Andrew Theurer wrote:
> > On Thursday 21 August 2003 09:58, Dave Hansen wrote:
> > > On Thu, 2003-08-21 at 07:10, Andrew Theurer wrote:
> > > > So we only loop for the actual number processors found in mpparse.c?
> > > > This seems to work for me.
> > >
> > > I think there's a reason it was done that way. I think your patch
> > > breaks the visws subarch, too.
> > >
> > > Could you mark up that loop a bit and printk a bit, so we can see which
> > > continue you're missing?
> > >
> > > <pasting patch lazily in email because I can't be bothered to actually
> > > copy it from the machine I"m working on> diff -urp
> > > linux-2.6.0-test3-clean/arch/i386/kernel/smpboot.c
> > > linux-2.6.0-test3-work/arch/i386/kernel/smpboot.c ---
> > > linux-2.6.0-test3-clean/arch/i386/kernel/smpboot.c Wed Aug 20 19:54:29
> > > 2003 +++ linux-2.6.0-test3-work/arch/i386/kernel/smpboot.c Wed Aug 20
> > > 20:19:41 2003 @@ -1020,24 +1020,30 @@ static void __init
> > > smp_boot_cpus(unsigne
> > > Dprintk("CPU present map: %lx\n",
> > > physids_coerce(phys_cpu_present_map));
> > >
> > > kicked = 1;
> > > - for (bit = 0; kicked < NR_CPUS && bit < MAX_APICS; bit++) {
> > > + for (bit = 0; kicked < NR_CPUS && bit < MAX_APICS; bit++,
> > > kicked++)
> >
> > This patch (plus your first one) seems to work. Perhaps the addition of
> > kicked++ above helped? Attached is the boot log.
>
> I missed that. But, it's incorrect. You're doubly incrementing kicked
> in the case of CPUs that are booted correctly and getting to kicked >=
> NR_CPUS a lot quicker. That's why you're booting correctly.
>
> Secondly, we can actually boot up to NR_CPUS cpus, and we can *fail* to
> boot a lot more than that. At least that's what the code is trying to
> do. Whether it is "the right thing" is debatable.
Boot log with extra kicked++ removed...
[-- Attachment #2: dmesg2 --]
[-- Type: text/plain, Size: 52978 bytes --]
Filesystem type is ext2fs, partition type 0x83
kernel /bzImage-2.6.0-test3-bk8 ro root=/dev/sda7 console=ttyS0,38400n8
[Linux-bzImage, setup=0xc00, size=0x1fc92d]
Linux version 2.6.0-test3-bk8 (root@x4408way2) (gcc version 3.2.2) #2 SMP Thu Aug 21 13:26:38 CDT 2003
Video mode to be used for restore is ffff
BIOS-provided physical RAM map:
BIOS-e820: 0000000000000000 - 000000000009dc00 (usable)
BIOS-e820: 000000000009dc00 - 00000000000a0000 (reserved)
BIOS-e820: 00000000000e0000 - 0000000000100000 (reserved)
BIOS-e820: 0000000000100000 - 00000000dffb6ec0 (usable)
BIOS-e820: 00000000dffb6ec0 - 00000000dffbf800 (ACPI data)
BIOS-e820: 00000000dffbf800 - 00000000e0000000 (reserved)
BIOS-e820: 00000000fec00000 - 0000000100000000 (reserved)
BIOS-e820: 0000000100000000 - 0000000320000000 (usable)
get_memcfg_from_srat: assigning address to rsdp
RSD PTR v0 [IBM ]
Begin table scan....
CPU 0x00 in proximity domain 0x00
CPU 0x02 in proximity domain 0x00
CPU 0x10 in proximity domain 0x00
CPU 0x12 in proximity domain 0x00
CPU 0x20 in proximity domain 0x01
CPU 0x22 in proximity domain 0x01
CPU 0x30 in proximity domain 0x01
CPU 0x32 in proximity domain 0x01
CPU 0x01 in proximity domain 0x00
CPU 0x03 in proximity domain 0x00
CPU 0x11 in proximity domain 0x00
CPU 0x13 in proximity domain 0x00
CPU 0x21 in proximity domain 0x01
CPU 0x23 in proximity domain 0x01
CPU 0x31 in proximity domain 0x01
CPU 0x33 in proximity domain 0x01
Memory range 0x0 to 0xE0000 (type 0x1) in proximity domain 0x00 enabled
Memory range 0x100000 to 0x220000 (type 0x1) in proximity domain 0x00 enabled
Memory range 0x220000 to 0x320000 (type 0x1) in proximity domain 0x01 enabled
acpi20_parse_srat: Entry length value is zero; can't parse any further!
pxm bitmap: 03 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
Number of logical nodes in system = 2
Number of memory chunks in system = 3
chunk 0 nid 0 start_pfn 00000000 end_pfn 000e0000
chunk 1 nid 0 start_pfn 00100000 end_pfn 00220000
chunk 2 nid 1 start_pfn 00220000 end_pfn 00320000
Reserving 11776 pages of KVA for lmem_map of node 1
Shrinking node 1 from 3276800 pages to 3265024 pages
Reserving total of 11776 pages for numa KVA remap
11904MB HIGHMEM available.
850MB LOWMEM available.
min_low_pfn = 1445, max_low_pfn = 217600, highstart_pfn = 229376
Low memory ends at vaddr f5200000
node 0 will remap to vaddr f8000000 - f8000000
node 1 will remap to vaddr f5200000 - f8000000
High memory starts at vaddr f8000000
ACPI: S3 and PAE do not like each other for now, S3 disabled.
found SMP MP-table at 0009dd40
hm, page 0009d000 reserved twice.
hm, page 0009e000 reserved twice.
hm, page 0009e000 reserved twice.
hm, page 0009f000 reserved twice.
On node 0 totalpages: 2097152
DMA zone: 4096 pages, LIFO batch:1
Normal zone: 213504 pages, LIFO batch:16
HighMem zone: 1879552 pages, LIFO batch:16
BUG: wrong zone alignment, it will crash
On node 1 totalpages: 1036800
DMA zone: 0 pages, LIFO batch:1
Normal zone: 0 pages, LIFO batch:1
HighMem zone: 1036800 pages, LIFO batch:16
DMI 2.3 present.
IBM machine detected. Enabling interrupts during APM calls.
IBM machine detected. Disabling SMBus accesses.
IBM eserver xSeries 440 detected: force use of acpi=ht
ACPI: RSDP (v000 IBM ) @ 0x000fdba0
ACPI: RSDT (v001 IBM SERVIGIL 0x00001000 IBM 0x45444f43) @ 0xdffbf780
ACPI: FADT (v001 IBM SERVIGIL 0x00001000 IBM 0x45444f43) @ 0xdffbf700
ACPI: MADT (v001 IBM SERVIGIL 0x00001000 IBM 0x45444f43) @ 0xdffbf580
ACPI: SRAT (v001 IBM SERVIGIL 0x00001000 IBM 0x45444f43) @ 0xdffbf3c0
ACPI: DSDT (v001 IBM SERVIGIL 0x00001000 INTL 0x02002025) @ 0x00000000
ACPI: Local APIC address 0xfee00000
ACPI: LAPIC (acpi_id[0x00] lapic_id[0x00] enabled)
Processor #0 15:1 APIC version 20
ACPI: LAPIC (acpi_id[0x01] lapic_id[0x02] enabled)
Processor #2 15:1 APIC version 20
ACPI: LAPIC (acpi_id[0x02] lapic_id[0x10] enabled)
Processor #16 15:1 APIC version 20
ACPI: LAPIC (acpi_id[0x03] lapic_id[0x12] enabled)
Processor #18 15:1 APIC version 20
ACPI: LAPIC (acpi_id[0x04] lapic_id[0x20] enabled)
Processor #32 15:1 APIC version 20
ACPI: LAPIC (acpi_id[0x05] lapic_id[0x22] enabled)
Processor #34 15:1 APIC version 20
ACPI: LAPIC (acpi_id[0x06] lapic_id[0x30] enabled)
Processor #48 15:1 APIC version 20
ACPI: LAPIC (acpi_id[0x07] lapic_id[0x32] enabled)
Processor #50 15:1 APIC version 20
ACPI: LAPIC (acpi_id[0x08] lapic_id[0x01] enabled)
Processor #1 15:1 APIC version 20
ACPI: LAPIC (acpi_id[0x09] lapic_id[0x03] enabled)
Processor #3 15:1 APIC version 20
ACPI: LAPIC (acpi_id[0x0a] lapic_id[0x11] enabled)
Processor #17 15:1 APIC version 20
ACPI: LAPIC (acpi_id[0x0b] lapic_id[0x13] enabled)
Processor #19 15:1 APIC version 20
ACPI: LAPIC (acpi_id[0x0c] lapic_id[0x21] enabled)
Processor #33 15:1 APIC version 20
ACPI: LAPIC (acpi_id[0x0d] lapic_id[0x23] enabled)
Processor #35 15:1 APIC version 20
ACPI: LAPIC (acpi_id[0x0e] lapic_id[0x31] enabled)
Processor #49 15:1 APIC version 20
ACPI: LAPIC (acpi_id[0x0f] lapic_id[0x33] enabled)
Processor #51 15:1 APIC version 20
ACPI: LAPIC_NMI (acpi_id[0x00] polarity[0x0] trigger[0x0] lint[0x1])
ACPI: LAPIC_NMI (acpi_id[0x01] polarity[0x0] trigger[0x0] lint[0x1])
ACPI: LAPIC_NMI (acpi_id[0x02] polarity[0x0] trigger[0x0] lint[0x1])
ACPI: LAPIC_NMI (acpi_id[0x03] polarity[0x0] trigger[0x0] lint[0x1])
ACPI: LAPIC_NMI (acpi_id[0x04] polarity[0x0] trigger[0x0] lint[0x1])
ACPI: LAPIC_NMI (acpi_id[0x05] polarity[0x0] trigger[0x0] lint[0x1])
ACPI: LAPIC_NMI (acpi_id[0x06] polarity[0x0] trigger[0x0] lint[0x1])
ACPI: LAPIC_NMI (acpi_id[0x07] polarity[0x0] trigger[0x0] lint[0x1])
ACPI: LAPIC_NMI (acpi_id[0x08] polarity[0x0] trigger[0x0] lint[0x1])
ACPI: LAPIC_NMI (acpi_id[0x09] polarity[0x0] trigger[0x0] lint[0x1])
ACPI: LAPIC_NMI (acpi_id[0x0a] polarity[0x0] trigger[0x0] lint[0x1])
ACPI: LAPIC_NMI (acpi_id[0x0b] polarity[0x0] trigger[0x0] lint[0x1])
ACPI: LAPIC_NMI (acpi_id[0x0c] polarity[0x0] trigger[0x0] lint[0x1])
ACPI: LAPIC_NMI (acpi_id[0x0d] polarity[0x0] trigger[0x0] lint[0x1])
ACPI: LAPIC_NMI (acpi_id[0x0e] polarity[0x0] trigger[0x0] lint[0x1])
ACPI: LAPIC_NMI (acpi_id[0x0f] polarity[0x0] trigger[0x0] lint[0x1])
Using ACPI for processor (LAPIC) configuration information
Intel MultiProcessor Specification v1.4
Virtual Wire compatibility mode.
OEM ID: IBM ENSW Product ID: VIGIL SMP APIC at: 0xFEE00000
I/O APIC #14 Version 17 at 0xFEC00000.
I/O APIC #13 Version 17 at 0xFEC01000.
Enabling APIC mode: Summit. Using 2 I/O APICs
Processors: 16
Building zonelist for node : 0
Building zonelist for node : 1
Kernel command line: ro root=/dev/sda7 console=ttyS0,38400n8
Initializing CPU#0
PID hash table entries: 4096 (order 12: 32768 bytes)
Summit chipset: Starting Cyclone Counter.
Detected 1498.432 MHz processor.
Console: colour VGA+ 80x25
Calibrating delay loop... 193.02 BogoMIPS
Initializing highpages for node 0
Initializing highpages for node 1
Memory: 12431384k/13107200k available (3113k kernel code, 102620k reserved, 1120k data, 204k init, 11665112k highmem)
Dentry cache hash table entries: 1048576 (order: 10, 4194304 bytes)
Inode-cache hash table entries: 1048576 (order: 10, 4194304 bytes)
Mount-cache hash table entries: 512 (order: 0, 4096 bytes)
-> /dev
-> /dev/console
-> /root
CPU: Trace cache: 12K uops, L1 D cache: 8K
CPU: L2 cache: 256K
CPU: L3 cache: 512K
CPU: Physical Processor ID: 0
Intel machine check architecture supported.
Intel machine check reporting enabled on CPU#0.
CPU#0: Intel P4/Xeon Extended MCE MSRs (12) available
CPU#0: Thermal monitoring enabled
Enabling fast FPU save and restore... done.
Enabling unmasked SIMD FPU exception support... done.
Checking 'hlt' instruction... OK.
POSIX conformance testing by UNIFIX
CPU0: Intel(R) Genuine CPU 1.50GHz stepping 01
per-CPU timeslice cutoff: 731.48 usecs.
task migration cache decay timeout: 1 msecs.
enabled ExtINT on CPU#0
Leaving ESR disabled.
Mapping cpu 0 to node 0
smp_boot_cpus() bit: 0
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 1
Booting processor 1/2 eip 2000
Initializing CPU#1
masked ExtINT on CPU#1
Leaving ESR disabled.
Mapping cpu 1 to node 0
Calibrating delay loop... 199.16 BogoMIPS
CPU: Trace cache: 12K uops, L1 D cache: 8K
CPU: L2 cache: 256K
CPU: L3 cache: 512K
CPU: Physical Processor ID: 1
Intel machine check architecture supported.
Intel machine check reporting enabled on CPU#1.
CPU#1: Intel P4/Xeon Extended MCE MSRs (12) available
CPU#1: Thermal monitoring enabled
CPU1: Intel(R) Xeon(TM) CPU 1.50GHz stepping 01
smp_boot_cpus() bit: 2
Booting processor 2/16 eip 2000
Initializing CPU#2
masked ExtINT on CPU#2
Leaving ESR disabled.
Mapping cpu 2 to node 0
Calibrating delay loop... 199.16 BogoMIPS
CPU: Trace cache: 12K uops, L1 D cache: 8K
CPU: L2 cache: 256K
CPU: L3 cache: 512K
CPU: Physical Processor ID: 2
Intel machine check architecture supported.
Intel machine check reporting enabled on CPU#2.
CPU#2: Intel P4/Xeon Extended MCE MSRs (12) available
CPU#2: Thermal monitoring enabled
CPU2: Intel(R) Xeon(TM) CPU 1.50GHz stepping 01
smp_boot_cpus() bit: 3
Booting processor 3/18 eip 2000
Initializing CPU#3
masked ExtINT on CPU#3
Leaving ESR disabled.
Mapping cpu 3 to node 0
Calibrating delay loop... 199.16 BogoMIPS
CPU: Trace cache: 12K uops, L1 D cache: 8K
CPU: L2 cache: 256K
CPU: L3 cache: 512K
CPU: Physical Processor ID: 3
Intel machine check architecture supported.
Intel machine check reporting enabled on CPU#3.
CPU#3: Intel P4/Xeon Extended MCE MSRs (12) available
CPU#3: Thermal monitoring enabled
CPU3: Intel(R) Xeon(TM) CPU 1.50GHz stepping 01
smp_boot_cpus() bit: 4
Booting processor 4/32 eip 2000
Initializing CPU#4
masked ExtINT on CPU#4
Leaving ESR disabled.
Mapping cpu 4 to node 1
Calibrating delay loop... 199.16 BogoMIPS
CPU: Trace cache: 12K uops, L1 D cache: 8K
CPU: L2 cache: 256K
CPU: L3 cache: 512K
CPU: Physical Processor ID: 8
Intel machine check architecture supported.
Intel machine check reporting enabled on CPU#4.
CPU#4: Intel P4/Xeon Extended MCE MSRs (12) available
CPU#4: Thermal monitoring enabled
CPU4: Intel(R) Genuine CPU 1.50GHz stepping 01
smp_boot_cpus() bit: 5
Booting processor 5/34 eip 2000
Initializing CPU#5
masked ExtINT on CPU#5
Leaving ESR disabled.
Mapping cpu 5 to node 1
Calibrating delay loop... 199.16 BogoMIPS
CPU: Trace cache: 12K uops, L1 D cache: 8K
CPU: L2 cache: 256K
CPU: L3 cache: 512K
CPU: Physical Processor ID: 9
Intel machine check architecture supported.
Intel machine check reporting enabled on CPU#5.
CPU#5: Intel P4/Xeon Extended MCE MSRs (12) available
CPU#5: Thermal monitoring enabled
CPU5: Intel(R) Xeon(TM) CPU 1.50GHz stepping 01
smp_boot_cpus() bit: 6
Booting processor 6/48 eip 2000
Initializing CPU#6
masked ExtINT on CPU#6
Leaving ESR disabled.
Mapping cpu 6 to node 1
Calibrating delay loop... 199.16 BogoMIPS
CPU: Trace cache: 12K uops, L1 D cache: 8K
CPU: L2 cache: 256K
CPU: L3 cache: 512K
CPU: Physical Processor ID: 10
Intel machine check architecture supported.
Intel machine check reporting enabled on CPU#6.
CPU#6: Intel P4/Xeon Extended MCE MSRs (12) available
CPU#6: Thermal monitoring enabled
CPU6: Intel(R) Xeon(TM) CPU 1.50GHz stepping 01
smp_boot_cpus() bit: 7
Booting processor 7/50 eip 2000
Initializing CPU#7
masked ExtINT on CPU#7
Leaving ESR disabled.
Mapping cpu 7 to node 1
Calibrating delay loop... 199.16 BogoMIPS
CPU: Trace cache: 12K uops, L1 D cache: 8K
CPU: L2 cache: 256K
CPU: L3 cache: 512K
CPU: Physical Processor ID: 11
Intel machine check architecture supported.
Intel machine check reporting enabled on CPU#7.
CPU#7: Intel P4/Xeon Extended MCE MSRs (12) available
CPU#7: Thermal monitoring enabled
CPU7: Intel(R) Xeon(TM) CPU 1.50GHz stepping 01
smp_boot_cpus() bit: 8
Booting processor 8/1 eip 2000
Initializing CPU#8
masked ExtINT on CPU#8
Leaving ESR disabled.
Mapping cpu 8 to node 0
Calibrating delay loop... 199.16 BogoMIPS
CPU: Trace cache: 12K uops, L1 D cache: 8K
CPU: L2 cache: 256K
CPU: L3 cache: 512K
CPU: Physical Processor ID: 0
Intel machine check architecture supported.
Intel machine check reporting enabled on CPU#8.
CPU#8: Intel P4/Xeon Extended MCE MSRs (12) available
CPU#8: Thermal monitoring enabled
CPU8: Intel(R) Genuine CPU 1.50GHz stepping 01
smp_boot_cpus() bit: 9
Booting processor 9/3 eip 2000
Initializing CPU#9
masked ExtINT on CPU#9
Leaving ESR disabled.
Mapping cpu 9 to node 0
Calibrating delay loop... 199.16 BogoMIPS
CPU: Trace cache: 12K uops, L1 D cache: 8K
CPU: L2 cache: 256K
CPU: L3 cache: 512K
CPU: Physical Processor ID: 1
Intel machine check architecture supported.
Intel machine check reporting enabled on CPU#9.
CPU#9: Intel P4/Xeon Extended MCE MSRs (12) available
CPU#9: Thermal monitoring enabled
CPU9: Intel(R) Xeon(TM) CPU 1.50GHz stepping 01
smp_boot_cpus() bit: 10
Booting processor 10/17 eip 2000
Initializing CPU#10
masked ExtINT on CPU#10
Leaving ESR disabled.
Mapping cpu 10 to node 0
Calibrating delay loop... 199.16 BogoMIPS
CPU: Trace cache: 12K uops, L1 D cache: 8K
CPU: L2 cache: 256K
CPU: L3 cache: 512K
CPU: Physical Processor ID: 2
Intel machine check architecture supported.
Intel machine check reporting enabled on CPU#10.
CPU#10: Intel P4/Xeon Extended MCE MSRs (12) available
CPU#10: Thermal monitoring enabled
CPU10: Intel(R) Xeon(TM) CPU 1.50GHz stepping 01
smp_boot_cpus() bit: 11
Booting processor 11/19 eip 2000
Initializing CPU#11
masked ExtINT on CPU#11
Leaving ESR disabled.
Mapping cpu 11 to node 0
Calibrating delay loop... 199.16 BogoMIPS
CPU: Trace cache: 12K uops, L1 D cache: 8K
CPU: L2 cache: 256K
CPU: L3 cache: 512K
CPU: Physical Processor ID: 3
Intel machine check architecture supported.
Intel machine check reporting enabled on CPU#11.
CPU#11: Intel P4/Xeon Extended MCE MSRs (12) available
CPU#11: Thermal monitoring enabled
CPU11: Intel(R) Xeon(TM) CPU 1.50GHz stepping 01
smp_boot_cpus() bit: 12
Booting processor 12/33 eip 2000
Initializing CPU#12
masked ExtINT on CPU#12
Leaving ESR disabled.
Mapping cpu 12 to node 1
Calibrating delay loop... 198.65 BogoMIPS
CPU: Trace cache: 12K uops, L1 D cache: 8K
CPU: L2 cache: 256K
CPU: L3 cache: 512K
CPU: Physical Processor ID: 8
Intel machine check architecture supported.
Intel machine check reporting enabled on CPU#12.
CPU#12: Intel P4/Xeon Extended MCE MSRs (12) available
CPU#12: Thermal monitoring enabled
CPU12: Intel(R) Genuine CPU 1.50GHz stepping 01
smp_boot_cpus() bit: 13
Booting processor 13/35 eip 2000
Initializing CPU#13
masked ExtINT on CPU#13
Leaving ESR disabled.
Mapping cpu 13 to node 1
Calibrating delay loop... 198.65 BogoMIPS
CPU: Trace cache: 12K uops, L1 D cache: 8K
CPU: L2 cache: 256K
CPU: L3 cache: 512K
CPU: Physical Processor ID: 9
Intel machine check architecture supported.
Intel machine check reporting enabled on CPU#13.
CPU#13: Intel P4/Xeon Extended MCE MSRs (12) available
CPU#13: Thermal monitoring enabled
CPU13: Intel(R) Xeon(TM) CPU 1.50GHz stepping 01
smp_boot_cpus() bit: 14
Booting processor 14/49 eip 2000
Initializing CPU#14
masked ExtINT on CPU#14
Leaving ESR disabled.
Mapping cpu 14 to node 1
Calibrating delay loop... 198.65 BogoMIPS
CPU: Trace cache: 12K uops, L1 D cache: 8K
CPU: L2 cache: 256K
CPU: L3 cache: 512K
CPU: Physical Processor ID: 10
Intel machine check architecture supported.
Intel machine check reporting enabled on CPU#14.
CPU#14: Intel P4/Xeon Extended MCE MSRs (12) available
CPU#14: Thermal monitoring enabled
CPU14: Intel(R) Xeon(TM) CPU 1.50GHz stepping 01
smp_boot_cpus() bit: 15
Booting processor 15/51 eip 2000
Initializing CPU#15
masked ExtINT on CPU#15
Leaving ESR disabled.
Mapping cpu 15 to node 1
Calibrating delay loop... 198.65 BogoMIPS
CPU: Trace cache: 12K uops, L1 D cache: 8K
CPU: L2 cache: 256K
CPU: L3 cache: 512K
CPU: Physical Processor ID: 11
Intel machine check architecture supported.
Intel machine check reporting enabled on CPU#15.
CPU#15: Intel P4/Xeon Extended MCE MSRs (12) available
CPU#15: Thermal monitoring enabled
CPU15: Intel(R) Xeon(TM) CPU 1.50GHz stepping 01
smp_boot_cpus() bit: 16
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 000000ff boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 17
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 000000ff boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 18
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 000000ff boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 19
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 000000ff boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 20
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 000000ff boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 21
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 000000ff boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 22
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 000000ff boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 23
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 000000ff boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 24
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 000000ff boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 25
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 000000ff boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 26
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 000000ff boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 27
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 000000ff boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 28
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 000000ff boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 29
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 000000ff boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 30
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 000000ff boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 31
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 000000ff boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 32
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 33
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 34
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 35
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 36
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 37
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 38
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 39
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 40
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 41
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 42
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 43
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 44
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 45
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 46
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 47
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 48
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 49
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 50
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 51
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 52
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 53
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 54
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 55
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 56
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 57
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 58
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 59
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 60
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 61
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 62
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 63
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 64
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 65
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 66
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 67
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 68
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 69
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 70
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 71
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 72
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 73
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 74
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 75
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 76
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 77
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 78
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 79
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 80
Booting processor 16/114 eip 2000
Not responding.
Unmapping cpu 16 from all nodes
CPU #114 not responding - cannot use it.
smp_boot_cpus() bit: 81
Booting processor 16/159 eip 2000
Not responding.
Unmapping cpu 16 from all nodes
CPU #159 not responding - cannot use it.
smp_boot_cpus() bit: 82
Booting processor 16/17 eip 2000
Initializing CPU#16
masked ExtINT on CPU#16
Leaving ESR disabled.
Mapping cpu 16 to node 0
Calibrating delay loop... 199.16 BogoMIPS
CPU: Trace cache: 12K uops, L1 D cache: 8K
CPU: L2 cache: 256K
CPU: L3 cache: 512K
CPU: Physical Processor ID: 2
Intel machine check architecture supported.
Intel machine check reporting enabled on CPU#16.
CPU#16: Intel P4/Xeon Extended MCE MSRs (12) available
CPU#16: Thermal monitoring enabled
CPU16: Intel(R) Xeon(TM) CPU 1.50GHz stepping 01
smp_boot_cpus() bit: 83
Booting processor 17/192 eip 2000
Not responding.
Unmapping cpu 17 from all nodes
CPU #192 not responding - cannot use it.
smp_boot_cpus() bit: 84
Booting processor 17/17 eip 2000
Initializing CPU#17
masked ExtINT on CPU#17
Leaving ESR disabled.
Mapping cpu 17 to node 0
Calibrating delay loop... 199.16 BogoMIPS
CPU: Trace cache: 12K uops, L1 D cache: 8K
CPU: L2 cache: 256K
CPU: L3 cache: 512K
CPU: Physical Processor ID: 2
Intel machine check architecture supported.
Intel machine check reporting enabled on CPU#17.
CPU#17: Intel P4/Xeon Extended MCE MSRs (12) available
CPU#17: Thermal monitoring enabled
CPU17: Intel(R) Xeon(TM) CPU 1.50GHz stepping 01
smp_boot_cpus() bit: 85
Booting processor 18/160 eip 2000
Not responding.
Unmapping cpu 18 from all nodes
CPU #160 not responding - cannot use it.
smp_boot_cpus() bit: 86
Booting processor 18/17 eip 2000
Initializing CPU#18
masked ExtINT on CPU#18
Leaving ESR disabled.
Mapping cpu 18 to node 0
Calibrating delay loop... 199.16 BogoMIPS
CPU: Trace cache: 12K uops, L1 D cache: 8K
CPU: L2 cache: 256K
CPU: L3 cache: 512K
CPU: Physical Processor ID: 2
Intel machine check architecture supported.
Intel machine check reporting enabled on CPU#18.
CPU#18: Intel P4/Xeon Extended MCE MSRs (12) available
CPU#18: Thermal monitoring enabled
CPU18: Intel(R) Xeon(TM) CPU 1.50GHz stepping 01
smp_boot_cpus() bit: 87
Booting processor 19/192 eip 2000
Not responding.
Unmapping cpu 19 from all nodes
CPU #192 not responding - cannot use it.
smp_boot_cpus() bit: 88
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 89
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 90
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 91
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 92
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 93
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 94
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 95
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 96
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 97
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 98
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 99
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 100
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 101
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 102
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 103
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 104
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 105
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 106
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 107
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 108
Booting processor 19/108 eip 2000
Not responding.
Unmapping cpu 19 from all nodes
CPU #108 not responding - cannot use it.
smp_boot_cpus() bit: 109
Booting processor 19/97 eip 2000
Not responding.
Unmapping cpu 19 from all nodes
CPU #97 not responding - cannot use it.
smp_boot_cpus() bit: 110
Booting processor 19/112 eip 2000
Not responding.
Unmapping cpu 19 from all nodes
CPU #112 not responding - cannot use it.
smp_boot_cpus() bit: 111
Booting processor 19/105 eip 2000
Not responding.
Unmapping cpu 19 from all nodes
CPU #105 not responding - cannot use it.
smp_boot_cpus() bit: 112
Booting processor 19/99 eip 2000
Not responding.
Unmapping cpu 19 from all nodes
CPU #99 not responding - cannot use it.
smp_boot_cpus() bit: 113
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 114
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 115
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 116
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 117
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 118
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 119
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 120
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 121
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 122
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 123
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 124
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 125
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 126
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 127
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 128
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 129
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 130
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 131
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 132
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 133
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 134
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 135
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 136
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 137
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 138
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 139
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 140
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 141
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 142
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 143
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 144
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 145
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 146
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 147
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 148
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 149
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 150
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 151
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 152
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 153
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 154
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 155
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 156
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 157
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 158
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 159
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 160
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 161
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 162
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 163
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 164
Booting processor 19/160 eip 2000
Not responding.
Unmapping cpu 19 from all nodes
CPU #160 not responding - cannot use it.
smp_boot_cpus() bit: 165
Booting processor 19/186 eip 2000
Not responding.
Unmapping cpu 19 from all nodes
CPU #186 not responding - cannot use it.
smp_boot_cpus() bit: 166
Booting processor 19/72 eip 2000
Not responding.
Unmapping cpu 19 from all nodes
CPU #72 not responding - cannot use it.
smp_boot_cpus() bit: 167
Booting processor 19/192 eip 2000
Not responding.
Unmapping cpu 19 from all nodes
CPU #192 not responding - cannot use it.
smp_boot_cpus() bit: 168
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 169
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 170
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 171
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 172
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 173
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 174
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 175
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 176
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 177
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 178
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 179
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 180
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 181
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 182
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 183
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 184
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 185
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 186
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 187
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 188
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 189
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 190
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 191
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 192
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 193
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 194
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 195
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 196
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 197
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 198
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 199
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 200
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 201
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 202
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 203
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 204
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 205
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 206
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 207
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 208
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 209
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 210
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 211
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 212
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 213
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 214
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 215
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 216
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 217
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 218
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 219
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 220
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 221
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 222
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 223
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 224
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 225
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 226
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 227
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 228
Booting processor 19/232 eip 2000
Not responding.
Unmapping cpu 19 from all nodes
CPU #232 not responding - cannot use it.
smp_boot_cpus() bit: 229
Booting processor 19/3 eip 2000
Initializing CPU#19
masked ExtINT on CPU#19
Leaving ESR disabled.
Mapping cpu 19 to node 0
Calibrating delay loop... 199.16 BogoMIPS
CPU: Trace cache: 12K uops, L1 D cache: 8K
CPU: L2 cache: 256K
CPU: L3 cache: 512K
CPU: Physical Processor ID: 1
Intel machine check architecture supported.
Intel machine check reporting enabled on CPU#19.
CPU#19: Intel P4/Xeon Extended MCE MSRs (12) available
CPU#19: Thermal monitoring enabled
CPU19: Intel(R) Xeon(TM) CPU 1.50GHz stepping 01
smp_boot_cpus() bit: 230
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 231
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 232
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 233
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 234
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 235
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 236
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 237
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 238
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 239
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 240
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 241
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 242
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 243
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 244
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 245
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 246
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 247
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 248
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 249
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 250
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 251
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 252
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 253
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 254
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
smp_boot_cpus() bit: 255
(apicid == boot_cpu_apicid) || (apicid == BAD_APICID)
apicid: 00000000 boot_cpu_apicid: 00000000 BAD_APICID: 000000ff
Total of 20 processors activated (3975.16 BogoMIPS).
cpu_sibling_map[0] = 8
cpu_sibling_map[1] = 9
cpu_sibling_map[2] = 10
cpu_sibling_map[3] = 11
cpu_sibling_map[4] = 12
cpu_sibling_map[5] = 13
cpu_sibling_map[6] = 14
cpu_sibling_map[7] = 15
cpu_sibling_map[8] = 0
cpu_sibling_map[9] = 1
cpu_sibling_map[10] = 2
cpu_sibling_map[11] = 3
cpu_sibling_map[12] = 4
cpu_sibling_map[13] = 5
cpu_sibling_map[14] = 6
cpu_sibling_map[15] = 7
cpu_sibling_map[16] = 2
cpu_sibling_map[17] = 2
cpu_sibling_map[18] = 2
cpu_sibling_map[19] = 1
ENABLING IO-APIC IRQs
Setting 14 in the phys_id_present_map
...changing IO-APIC physical APIC ID to 14 ... ok.
Setting 13 in the phys_id_present_map
...changing IO-APIC physical APIC ID to 13 ... ok.
..TIMER: vector=0x31 pin1=0 pin2=-1
testing the IO APIC.......................
.................................... done.
Using local APIC timer interrupts.
calibrating APIC timer ...
..... CPU clock speed is 1496.0819 MHz.
..... host bus clock speed is 99.0787 MHz.
checking TSC synchronization across 20 CPUs:
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: CPU boot problem on 2.6.0-test3-bk8
2003-08-21 15:28 ` Dave Hansen
@ 2003-08-21 21:04 ` William Lee Irwin III
0 siblings, 0 replies; 19+ messages in thread
From: William Lee Irwin III @ 2003-08-21 21:04 UTC (permalink / raw)
To: Dave Hansen; +Cc: Andrew Theurer, linux-kernel, Andrew Morton, Martin J. Bligh
On Thu, Aug 21, 2003 at 08:28:08AM -0700, Dave Hansen wrote:
> It looks like you booted 20 processors, successfully.
> You have 5 "Geniune" cpus and 16 "Xeon" cpus. Are you using plain
> summit, or generic arch support?
AFAICT the only way we can see that is if we kick the same ones twice.
Using max_cpus= the exact number of cpus you have or CONFIG_NR_CPUS=
the exact number of cpus you have will get testers able to boot until
it's fixed.
It shouldn't be too hard to find the faulty code; all 5 "Genuine"
entries are bogus and alias the entries we actually want (the Xeons).
-- wli
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: CPU boot problem on 2.6.0-test3-bk8
2003-08-21 17:02 ` Andrew Theurer
@ 2003-08-21 21:13 ` William Lee Irwin III
2003-08-21 21:33 ` William Lee Irwin III
2003-08-22 17:16 ` William Lee Irwin III
2 siblings, 0 replies; 19+ messages in thread
From: William Lee Irwin III @ 2003-08-21 21:13 UTC (permalink / raw)
To: Andrew Theurer; +Cc: Dave Hansen, linux-kernel, Andrew Morton, Martin J. Bligh
On Thu, Aug 21, 2003 at 12:02:02PM -0500, Andrew Theurer wrote:
>>> This patch (plus your first one) seems to work. Perhaps the addition of
>>> kicked++ above helped? Attached is the boot log.
No, it didn't. The reasons why it "worked" were:
(a) NR_CPUS is exactly twice the number of cpus you want
(b) all of the bogus entries appear _after_ the legitimate ones
-- wli
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: CPU boot problem on 2.6.0-test3-bk8
2003-08-21 17:02 ` Andrew Theurer
2003-08-21 21:13 ` William Lee Irwin III
@ 2003-08-21 21:33 ` William Lee Irwin III
2003-08-21 22:17 ` William Lee Irwin III
2003-08-22 17:16 ` William Lee Irwin III
2 siblings, 1 reply; 19+ messages in thread
From: William Lee Irwin III @ 2003-08-21 21:33 UTC (permalink / raw)
To: Andrew Theurer; +Cc: Dave Hansen, linux-kernel, Andrew Morton, Martin J. Bligh
On Thu, Aug 21, 2003 at 12:02:02PM -0500, Andrew Theurer wrote:
> smp_boot_cpus() bit: 80
> Booting processor 16/114 eip 2000
> Not responding.
> Unmapping cpu 16 from all nodes
> CPU #114 not responding - cannot use it.
cpu_present_to_apicid() needs a similar treatment to dhansen's prior
bits. diff incoming shortly.
-- wli
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: CPU boot problem on 2.6.0-test3-bk8
2003-08-21 21:33 ` William Lee Irwin III
@ 2003-08-21 22:17 ` William Lee Irwin III
2003-08-21 22:45 ` William Lee Irwin III
0 siblings, 1 reply; 19+ messages in thread
From: William Lee Irwin III @ 2003-08-21 22:17 UTC (permalink / raw)
To: Andrew Theurer, Dave Hansen, linux-kernel, Andrew Morton,
Martin J. Bligh
On Thu, Aug 21, 2003 at 12:02:02PM -0500, Andrew Theurer wrote:
>> smp_boot_cpus() bit: 80
>> Booting processor 16/114 eip 2000
>> Not responding.
>> Unmapping cpu 16 from all nodes
>> CPU #114 not responding - cannot use it.
On Thu, Aug 21, 2003 at 02:33:50PM -0700, William Lee Irwin III wrote:
> cpu_present_to_apicid() needs a similar treatment to dhansen's prior
> bits. diff incoming shortly.
Could one of you two try this out on a Summit machine in addition to
Dave's prior patch (or hook me up to one)?
Thanks.
-- wli
===== include/asm-i386/mach-bigsmp/mach_apic.h 1.16 vs edited =====
--- 1.16/include/asm-i386/mach-bigsmp/mach_apic.h Wed Aug 20 22:32:06 2003
+++ edited/include/asm-i386/mach-bigsmp/mach_apic.h Thu Aug 21 15:07:42 2003
@@ -86,7 +86,10 @@
static inline int cpu_present_to_apicid(int mps_cpu)
{
- return (int) bios_cpu_apicid[mps_cpu];
+ if (mps_cpu < NR_CPUS)
+ return (int)bios_cpu_apicid[mps_cpu];
+ else
+ return BAD_APICID;
}
static inline physid_mask_t apicid_to_cpu_present(int phys_apicid)
===== include/asm-i386/mach-default/mach_apic.h 1.27 vs edited =====
--- 1.27/include/asm-i386/mach-default/mach_apic.h Mon Aug 18 19:46:23 2003
+++ edited/include/asm-i386/mach-default/mach_apic.h Thu Aug 21 15:08:15 2003
@@ -83,7 +83,10 @@
static inline int cpu_present_to_apicid(int mps_cpu)
{
- return mps_cpu;
+ if (mps_cpu < NR_CPUS)
+ return mps_cpu;
+ else
+ return BAD_APICID;
}
static inline physid_mask_t apicid_to_cpu_present(int phys_apicid)
===== include/asm-i386/mach-es7000/mach_apic.h 1.3 vs edited =====
--- 1.3/include/asm-i386/mach-es7000/mach_apic.h Wed Aug 20 22:32:06 2003
+++ edited/include/asm-i386/mach-es7000/mach_apic.h Thu Aug 21 15:08:41 2003
@@ -106,8 +106,10 @@
{
if (!mps_cpu)
return boot_cpu_physical_apicid;
- else
+ else if (mps_cpu < NR_CPUS)
return (int) bios_cpu_apicid[mps_cpu];
+ else
+ return BAD_APICID;
}
static inline physid_mask_t apicid_to_cpu_present(int phys_apicid)
===== include/asm-i386/mach-numaq/mach_apic.h 1.22 vs edited =====
--- 1.22/include/asm-i386/mach-numaq/mach_apic.h Wed Aug 20 22:32:06 2003
+++ edited/include/asm-i386/mach-numaq/mach_apic.h Thu Aug 21 15:10:31 2003
@@ -65,9 +65,17 @@
return (int)cpu_2_logical_apicid[cpu];
}
+/*
+ * Supporting over 60 cpus on NUMA-Q requires a locality-dependent
+ * cpu to APIC ID relation to properly interact with the intelligent
+ * mode of the cluster controller.
+ */
static inline int cpu_present_to_apicid(int mps_cpu)
{
- return ((mps_cpu >> 2) << 4) | (1 << (mps_cpu & 0x3));
+ if (mps_cpu < 60)
+ return ((mps_cpu >> 2) << 4) | (1 << (mps_cpu & 0x3));
+ else
+ return BAD_APICID;
}
static inline int generate_logical_apicid(int quad, int phys_apicid)
===== include/asm-i386/mach-summit/mach_apic.h 1.31 vs edited =====
--- 1.31/include/asm-i386/mach-summit/mach_apic.h Wed Aug 20 22:32:06 2003
+++ edited/include/asm-i386/mach-summit/mach_apic.h Thu Aug 21 15:10:57 2003
@@ -87,7 +87,10 @@
static inline int cpu_present_to_apicid(int mps_cpu)
{
- return (int) bios_cpu_apicid[mps_cpu];
+ if (mps_cpu < NR_CPUS)
+ return (int)bios_cpu_apicid[mps_cpu];
+ else
+ return BAD_APICID;
}
static inline physid_mask_t ioapic_phys_id_map(physid_mask_t phys_id_map)
===== include/asm-i386/mach-visws/mach_apic.h 1.7 vs edited =====
--- 1.7/include/asm-i386/mach-visws/mach_apic.h Wed Aug 20 22:30:10 2003
+++ edited/include/asm-i386/mach-visws/mach_apic.h Thu Aug 21 15:11:16 2003
@@ -59,7 +59,10 @@
static inline int cpu_present_to_apicid(int mps_cpu)
{
- return mps_cpu;
+ if (mps_cpu < NR_CPUS)
+ return mps_cpu;
+ else
+ return BAD_APICID;
}
static inline physid_mask_t apicid_to_cpu_present(int apicid)
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: CPU boot problem on 2.6.0-test3-bk8
2003-08-21 22:17 ` William Lee Irwin III
@ 2003-08-21 22:45 ` William Lee Irwin III
2003-08-21 23:10 ` William Lee Irwin III
0 siblings, 1 reply; 19+ messages in thread
From: William Lee Irwin III @ 2003-08-21 22:45 UTC (permalink / raw)
To: Andrew Theurer, Dave Hansen, linux-kernel, Andrew Morton,
Martin J. Bligh
On Thu, Aug 21, 2003 at 02:33:50PM -0700, William Lee Irwin III wrote:
>> cpu_present_to_apicid() needs a similar treatment to dhansen's prior
>> bits. diff incoming shortly.
On Thu, Aug 21, 2003 at 03:17:44PM -0700, William Lee Irwin III wrote:
> Could one of you two try this out on a Summit machine in addition to
> Dave's prior patch (or hook me up to one)?
That broke sparse APIC ID's on several subarches. This is a bit less
indiscriminate about who it updates (and should replace the prior patch
wrt. sending anything upstream):
-- wli
===== include/asm-i386/mach-bigsmp/mach_apic.h 1.16 vs edited =====
--- 1.16/include/asm-i386/mach-bigsmp/mach_apic.h Wed Aug 20 22:32:06 2003
+++ edited/include/asm-i386/mach-bigsmp/mach_apic.h Thu Aug 21 15:07:42 2003
@@ -86,7 +86,10 @@
static inline int cpu_present_to_apicid(int mps_cpu)
{
- return (int) bios_cpu_apicid[mps_cpu];
+ if (mps_cpu < NR_CPUS)
+ return (int)bios_cpu_apicid[mps_cpu];
+ else
+ return BAD_APICID;
}
static inline physid_mask_t apicid_to_cpu_present(int phys_apicid)
===== include/asm-i386/mach-es7000/mach_apic.h 1.3 vs edited =====
--- 1.3/include/asm-i386/mach-es7000/mach_apic.h Wed Aug 20 22:32:06 2003
+++ edited/include/asm-i386/mach-es7000/mach_apic.h Thu Aug 21 15:08:41 2003
@@ -106,8 +106,10 @@
{
if (!mps_cpu)
return boot_cpu_physical_apicid;
- else
+ else if (mps_cpu < NR_CPUS)
return (int) bios_cpu_apicid[mps_cpu];
+ else
+ return BAD_APICID;
}
static inline physid_mask_t apicid_to_cpu_present(int phys_apicid)
===== include/asm-i386/mach-numaq/mach_apic.h 1.22 vs edited =====
--- 1.22/include/asm-i386/mach-numaq/mach_apic.h Wed Aug 20 22:32:06 2003
+++ edited/include/asm-i386/mach-numaq/mach_apic.h Thu Aug 21 15:10:31 2003
@@ -65,9 +65,17 @@
return (int)cpu_2_logical_apicid[cpu];
}
+/*
+ * Supporting over 60 cpus on NUMA-Q requires a locality-dependent
+ * cpu to APIC ID relation to properly interact with the intelligent
+ * mode of the cluster controller.
+ */
static inline int cpu_present_to_apicid(int mps_cpu)
{
- return ((mps_cpu >> 2) << 4) | (1 << (mps_cpu & 0x3));
+ if (mps_cpu < 60)
+ return ((mps_cpu >> 2) << 4) | (1 << (mps_cpu & 0x3));
+ else
+ return BAD_APICID;
}
static inline int generate_logical_apicid(int quad, int phys_apicid)
===== include/asm-i386/mach-summit/mach_apic.h 1.31 vs edited =====
--- 1.31/include/asm-i386/mach-summit/mach_apic.h Wed Aug 20 22:32:06 2003
+++ edited/include/asm-i386/mach-summit/mach_apic.h Thu Aug 21 15:10:57 2003
@@ -87,7 +87,10 @@
static inline int cpu_present_to_apicid(int mps_cpu)
{
- return (int) bios_cpu_apicid[mps_cpu];
+ if (mps_cpu < NR_CPUS)
+ return (int)bios_cpu_apicid[mps_cpu];
+ else
+ return BAD_APICID;
}
static inline physid_mask_t ioapic_phys_id_map(physid_mask_t phys_id_map)
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: CPU boot problem on 2.6.0-test3-bk8
2003-08-21 22:45 ` William Lee Irwin III
@ 2003-08-21 23:10 ` William Lee Irwin III
0 siblings, 0 replies; 19+ messages in thread
From: William Lee Irwin III @ 2003-08-21 23:10 UTC (permalink / raw)
To: torvalds
Cc: Andrew Theurer, Dave Hansen, linux-kernel, Andrew Morton,
Martin J. Bligh
On Thu, Aug 21, 2003 at 03:45:43PM -0700, William Lee Irwin III wrote:
> That broke sparse APIC ID's on several subarches. This is a bit less
> indiscriminate about who it updates (and should replace the prior patch
> wrt. sending anything upstream):
This must go in regardless; in the bios_cpu_apicid[] case, it would
walk off the end of bios_cpu_apicid[] and attempt to send APIC INIT
messages to garbage without this patch, and in the NUMA-Q case, it
would attempt to send NMI wakeups to destinations in the broadcast
cluster (which is harmless, but very poor form) without this patch.
vs. current bk as of 4:01PM PDT.
Linus, please apply.
-- wli
===== include/asm-i386/mach-bigsmp/mach_apic.h 1.16 vs edited =====
--- 1.16/include/asm-i386/mach-bigsmp/mach_apic.h Wed Aug 20 22:32:06 2003
+++ edited/include/asm-i386/mach-bigsmp/mach_apic.h Thu Aug 21 15:07:42 2003
@@ -86,7 +86,10 @@
static inline int cpu_present_to_apicid(int mps_cpu)
{
- return (int) bios_cpu_apicid[mps_cpu];
+ if (mps_cpu < NR_CPUS)
+ return (int)bios_cpu_apicid[mps_cpu];
+ else
+ return BAD_APICID;
}
static inline physid_mask_t apicid_to_cpu_present(int phys_apicid)
===== include/asm-i386/mach-es7000/mach_apic.h 1.3 vs edited =====
--- 1.3/include/asm-i386/mach-es7000/mach_apic.h Wed Aug 20 22:32:06 2003
+++ edited/include/asm-i386/mach-es7000/mach_apic.h Thu Aug 21 15:08:41 2003
@@ -106,8 +106,10 @@
{
if (!mps_cpu)
return boot_cpu_physical_apicid;
- else
+ else if (mps_cpu < NR_CPUS)
return (int) bios_cpu_apicid[mps_cpu];
+ else
+ return BAD_APICID;
}
static inline physid_mask_t apicid_to_cpu_present(int phys_apicid)
===== include/asm-i386/mach-numaq/mach_apic.h 1.22 vs edited =====
--- 1.22/include/asm-i386/mach-numaq/mach_apic.h Wed Aug 20 22:32:06 2003
+++ edited/include/asm-i386/mach-numaq/mach_apic.h Thu Aug 21 15:10:31 2003
@@ -65,9 +65,17 @@
return (int)cpu_2_logical_apicid[cpu];
}
+/*
+ * Supporting over 60 cpus on NUMA-Q requires a locality-dependent
+ * cpu to APIC ID relation to properly interact with the intelligent
+ * mode of the cluster controller.
+ */
static inline int cpu_present_to_apicid(int mps_cpu)
{
- return ((mps_cpu >> 2) << 4) | (1 << (mps_cpu & 0x3));
+ if (mps_cpu < 60)
+ return ((mps_cpu >> 2) << 4) | (1 << (mps_cpu & 0x3));
+ else
+ return BAD_APICID;
}
static inline int generate_logical_apicid(int quad, int phys_apicid)
===== include/asm-i386/mach-summit/mach_apic.h 1.31 vs edited =====
--- 1.31/include/asm-i386/mach-summit/mach_apic.h Wed Aug 20 22:32:06 2003
+++ edited/include/asm-i386/mach-summit/mach_apic.h Thu Aug 21 15:10:57 2003
@@ -87,7 +87,10 @@
static inline int cpu_present_to_apicid(int mps_cpu)
{
- return (int) bios_cpu_apicid[mps_cpu];
+ if (mps_cpu < NR_CPUS)
+ return (int)bios_cpu_apicid[mps_cpu];
+ else
+ return BAD_APICID;
}
static inline physid_mask_t ioapic_phys_id_map(physid_mask_t phys_id_map)
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: CPU boot problem on 2.6.0-test3-bk8
2003-08-21 17:02 ` Andrew Theurer
2003-08-21 21:13 ` William Lee Irwin III
2003-08-21 21:33 ` William Lee Irwin III
@ 2003-08-22 17:16 ` William Lee Irwin III
2003-08-22 18:16 ` Andrew Theurer
2003-08-22 19:11 ` Andrew Theurer
2 siblings, 2 replies; 19+ messages in thread
From: William Lee Irwin III @ 2003-08-22 17:16 UTC (permalink / raw)
To: Andrew Theurer; +Cc: Dave Hansen, linux-kernel, Andrew Morton, Martin J. Bligh
On Thu, Aug 21, 2003 at 12:02:02PM -0500, Andrew Theurer wrote:
> Boot log with extra kicked++ removed...
Say, could you try last night's bk snapshot and let me know how it's
doing? I threw in a necessary fix on top of Dave's last night, but I
don't know whether it's sufficient for your purposes yet.
-- wli
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: CPU boot problem on 2.6.0-test3-bk8
2003-08-22 17:16 ` William Lee Irwin III
@ 2003-08-22 18:16 ` Andrew Theurer
2003-08-22 19:11 ` Andrew Theurer
1 sibling, 0 replies; 19+ messages in thread
From: Andrew Theurer @ 2003-08-22 18:16 UTC (permalink / raw)
To: William Lee Irwin III
Cc: Dave Hansen, linux-kernel, Andrew Morton, Martin J. Bligh
On Friday 22 August 2003 12:16, William Lee Irwin III wrote:
> On Thu, Aug 21, 2003 at 12:02:02PM -0500, Andrew Theurer wrote:
> > Boot log with extra kicked++ removed...
>
> Say, could you try last night's bk snapshot and let me know how it's
> doing? I threw in a necessary fix on top of Dave's last night, but I
> don't know whether it's sufficient for your purposes yet.
Yes, should have it tested in a few, just backed up right now.
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: CPU boot problem on 2.6.0-test3-bk8
2003-08-22 17:16 ` William Lee Irwin III
2003-08-22 18:16 ` Andrew Theurer
@ 2003-08-22 19:11 ` Andrew Theurer
1 sibling, 0 replies; 19+ messages in thread
From: Andrew Theurer @ 2003-08-22 19:11 UTC (permalink / raw)
To: William Lee Irwin III
Cc: Dave Hansen, linux-kernel, Andrew Morton, Martin J. Bligh
On Friday 22 August 2003 12:16, William Lee Irwin III wrote:
> On Thu, Aug 21, 2003 at 12:02:02PM -0500, Andrew Theurer wrote:
> > Boot log with extra kicked++ removed...
>
> Say, could you try last night's bk snapshot and let me know how it's
> doing? I threw in a necessary fix on top of Dave's last night, but I
> don't know whether it's sufficient for your purposes yet.
OK, looks like it worked fine.
^ permalink raw reply [flat|nested] 19+ messages in thread
end of thread, other threads:[~2003-08-22 19:11 UTC | newest]
Thread overview: 19+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2003-08-20 21:58 CPU boot problem on 2.6.0-test3-bk8 Andrew Theurer
2003-08-21 1:02 ` Dave Hansen
2003-08-21 1:13 ` Andrew Theurer
2003-08-21 3:42 ` Dave Hansen
2003-08-21 14:10 ` Andrew Theurer
2003-08-21 14:58 ` Dave Hansen
2003-08-21 15:56 ` Andrew Theurer
2003-08-21 16:09 ` Dave Hansen
2003-08-21 17:02 ` Andrew Theurer
2003-08-21 21:13 ` William Lee Irwin III
2003-08-21 21:33 ` William Lee Irwin III
2003-08-21 22:17 ` William Lee Irwin III
2003-08-21 22:45 ` William Lee Irwin III
2003-08-21 23:10 ` William Lee Irwin III
2003-08-22 17:16 ` William Lee Irwin III
2003-08-22 18:16 ` Andrew Theurer
2003-08-22 19:11 ` Andrew Theurer
2003-08-21 15:28 ` Dave Hansen
2003-08-21 21:04 ` William Lee Irwin III
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