fsb of older cpu

fsb of older cpu

[Bjoern Schmidt]

Hello,
is there a way to measure/change the fsb of a PII/233/Tonga/440BX while running
linux? Google has no answer...

-- 
Greetings
Bjoern Schmidt

Re: fsb of older cpu

[Bernd Schubert]

On Monday 08 March 2004 11:38, Bjoern Schmidt wrote:
> Hello,
> is there a way to measure/change the fsb of a PII/233/Tonga/440BX while
> running linux? Google has no answer...

This is the only one I know about, but it has support for a few boards/pll's 
only.

http://home.iprimus.com.au/mccvals/mvpll/

Hope it helps,
	Bernd

Re: fsb of older cpu

[Bjoern Schmidt]

Bernd Schubert schrieb:
> On Monday 08 March 2004 11:38, Bjoern Schmidt wrote:
> 
>>Hello,
>>is there a way to measure/change the fsb of a PII/233/Tonga/440BX while
>>running linux? Google has no answer...
> 
> 
> This is the only one I know about, but it has support for a few boards/pll's 
> only.
> 
> http://home.iprimus.com.au/mccvals/mvpll/
> 
> Hope it helps,
> 	Bernd

Hello and thank you for your answer. I determined that this cpu has a fsb of
66MHz. The reason for my question was that i want to underclock the cpu.
I think it would be better to change the multiplier instead of changing the fsb.
Therefore i read the msr register 0x02ah, tilted bit 27 and wrote it back, but
the cpu clock is still the same. Why does that not work? Is it possible to
change the multiplier at runtime at all?

-- 
Mit freundlichen Gruessen
Bjoern Schmidt

Re: fsb of older cpu

[Zwane Mwaikambo]

On Mon, 8 Mar 2004, Bjoern Schmidt wrote:

> Hello and thank you for your answer. I determined that this cpu has a fsb of
> 66MHz. The reason for my question was that i want to underclock the cpu.
> I think it would be better to change the multiplier instead of changing the fsb.
> Therefore i read the msr register 0x02ah, tilted bit 27 and wrote it back, but
> the cpu clock is still the same. Why does that not work? Is it possible to
> change the multiplier at runtime at all?

No, the multiplier is locked, you'll have more luck fiddling with the
front side bus.

Re: fsb of older cpu

[Stefan Smietanowski]

Zwane Mwaikambo wrote:

> On Mon, 8 Mar 2004, Bjoern Schmidt wrote:
> 
> 
>>Hello and thank you for your answer. I determined that this cpu has a fsb of
>>66MHz. The reason for my question was that i want to underclock the cpu.
>>I think it would be better to change the multiplier instead of changing the fsb.
>>Therefore i read the msr register 0x02ah, tilted bit 27 and wrote it back, but
>>the cpu clock is still the same. Why does that not work? Is it possible to
>>change the multiplier at runtime at all?
> 
> 
> No, the multiplier is locked, you'll have more luck fiddling with the
> front side bus.

That would be the first P2/233 with a locked multiplier I've come
across. My P2's ranging from 233 to 350 were never multiplier locked
anyway. Celerons and P3's were multiplier locked however, maybe that's
what you're thinking about.

// Stefan

Re: fsb of older cpu

[Zwane Mwaikambo]

On Mon, 8 Mar 2004, Stefan Smietanowski wrote:

> > No, the multiplier is locked, you'll have more luck fiddling with the
> > front side bus.
>
> That would be the first P2/233 with a locked multiplier I've come
> across. My P2's ranging from 233 to 350 were never multiplier locked
> anyway. Celerons and P3's were multiplier locked however, maybe that's
> what you're thinking about.

There were lots of locked P1s for example, the last unlocked
pentium+ processor i came across was a 133, but i stopped caring/checking
after a while anyway.

Re: fsb of older cpu

[Stefan Smietanowski]

>>> Hello,
>>> is there a way to measure/change the fsb of a PII/233/Tonga/440BX while
>>> running linux? Google has no answer...
>>
>>
>>
>> This is the only one I know about, but it has support for a few 
>> boards/pll's only.
>>
>> http://home.iprimus.com.au/mccvals/mvpll/
>>
>> Hope it helps,
>>     Bernd
> 
> 
> Hello and thank you for your answer. I determined that this cpu has a 
> fsb of
> 66MHz. The reason for my question was that i want to underclock the cpu.
> I think it would be better to change the multiplier instead of changing 
> the fsb.
> Therefore i read the msr register 0x02ah, tilted bit 27 and wrote it 
> back, but
> the cpu clock is still the same. Why does that not work? Is it possible to
> change the multiplier at runtime at all?
> 

I'm no expert on the subject but as I recall the processor sets the
internal clock (derived from fsb+multiplier) on startup so no matter
what you do do the running cpu it won't change it.

// Stefan

Re: fsb of older cpu

[Bjoern Schmidt]

Stefan Smietanowski schrieb:
> I'm no expert on the subject but as I recall the processor sets the
> internal clock (derived from fsb+multiplier) on startup so no matter
> what you do do the running cpu it won't change it.

I think there must be a way. In the BIOS there ist an option "half processor
clock it is in idle". One time i have seen in /proc/cpuinfo" that the clock
was at ~118MHz, but that is 6 Month ago and i have this never seen again...
The problem is that with activated acpi the passive cooling does not seem to 
work although the cpu is very often in C2 and throttling mode is at 8. C1 is 
called extrem rarely (~1000 times per day), even if the system is under heavy
load for a long time. I believe that C2 is not really supported by the cpu.

-- 
Greetings
Bjoern Schmidt

Re: fsb of older cpu

[Len Brown]

C-states should be called Idle-states -- they're entered when the
processor is idle.  No instructions are executed when in a C-state > 0.

C1 is supported by all processors automatically with some carefully
placed insructions inside the idle loop.  Not all processors suport
higher C-states with more power savings in idle.  You'll be able to tell
what is supported and what is used by looking in /proc/acpi/CPU0/power. 
I'm not sure we update the counter to reflect entering C1...

Then there are P-states -- performance states.  These are used by the
various cpufreq drivers such as speed-step(tm;-).  These can modulate
both voltage and Mhz at the same time depending on load and are thus the
most effective and most desireable way to save cpu power w/ minimal
performance impact.

Thermal throttling is  something else.  This is invoked as the
passive-colling method of last resort when the processor is very hot
(busy).  The actual clock to the processor is modulated so that it slows
down and thus power is saved in proportion to how much it is slowed
down.  Throttling will noticeably slow down your system when you want it
fast the most -- heavy load.

Of course, then there is active cooling -- fan control...

cheers,
-Len

On Mon, 2004-03-08 at 16:53, Bjoern Schmidt wrote:
> Stefan Smietanowski schrieb:
> > I'm no expert on the subject but as I recall the processor sets the
> > internal clock (derived from fsb+multiplier) on startup so no matter
> > what you do do the running cpu it won't change it.
> 
> I think there must be a way. In the BIOS there ist an option "half
> processor
> clock it is in idle". One time i have seen in /proc/cpuinfo" that the
> clock
> was at ~118MHz, but that is 6 Month ago and i have this never seen
> again...
> The problem is that with activated acpi the passive cooling does not
> seem to 
> work although the cpu is very often in C2 and throttling mode is at 8.
> C1 is 
> called extrem rarely (~1000 times per day), even if the system is
> under heavy
> load for a long time. I believe that C2 is not really supported by the
> cpu.
> 
> -- 
> Greetings
> Bjoern Schmidt
> 
> 
> -
> To unsubscribe from this list: send the line "unsubscribe
> linux-kernel" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> Please read the FAQ at  http://www.tux.org/lkml/
> 

Re: fsb of older cpu

[Bjoern Schmidt]

Hello Len,

> C-states should be called Idle-states -- they're entered when the
> processor is idle.  No instructions are executed when in a C-state > 0.

i know about the acpi spec ;)

> 
> C1 is supported by all processors automatically with some carefully
> placed insructions inside the idle loop.  Not all processors suport
> higher C-states with more power savings in idle.  You'll be able to tell
> what is supported and what is used by looking in /proc/acpi/CPU0/power. 
> I'm not sure we update the counter to reflect entering C1...

The supported modes are:

root@kilobyte:/proc/acpi/processor/C097# cat power
active state:        C2
default state:       C1
bus master activity: 00000000
states:
     C1:              promotion[C2] demotion[--] latency[000] usage[00000240]
    *C2:              promotion[--] demotion[C1] latency[100] usage[169083068]
     C3:              <not supported>

Do you know a little program to visualize the fadt flags in a human
readable way?

> 
> Then there are P-states -- performance states.  These are used by the
> various cpufreq drivers such as speed-step(tm;-).  These can modulate
> both voltage and Mhz at the same time depending on load and are thus the
> most effective and most desireable way to save cpu power w/ minimal
> performance impact.

In the BIOS there is an option to half the core freq in idle, is
it possible to create a proc interface to set it statically to
the half?

In the System Programming Guide i can read that i can reprogram the
clock multiplier by setting RESET# to low and A20M#, IGNNE#, LINT[1]
and LINT[0] to 1111 for 1/2. Unfortunately i dont know how to
program this in assembler code, i can several programming
languages, but not yet asm :(
Can you recommend a good online book?

> 
> Thermal throttling is  something else.  This is invoked as the
> passive-colling method of last resort when the processor is very hot
> (busy).  The actual clock to the processor is modulated so that it slows
> down and thus power is saved in proportion to how much it is slowed
> down.  Throttling will noticeably slow down your system when you want it
> fast the most -- heavy load.

On my system the passive cooling is always active, but i am sure
that it does not work or at least not correctly.

root@kilobyte:/tmp# cat /proc/acpi/processor/C097/throttling
state count:             8
active state:            T7
states:
     T0:                  00%
     T1:                  12%
     T2:                  25%
     T3:                  37%
     T4:                  50%
     T5:                  62%
     T6:                  75%
    *T7:                  87%

T7 equals that only 13% of performance ist available,
but i cannot determine any slowdown on my system.

root@kilobyte:/tmp# cat /proc/acpi/thermal_zone/C105/*
cooling mode:            passive
<polling disabled>
state:                   passive
temperature:             91 C
critical (S5):           95 C
passive:                 48 C: tc1=1 tc2=2 tsp=200 devices=0xc11dc6a8
active[0]:               94 C: devices=0xc11d5268
active[1]:               92 C: devices=0xc11d4be8

If throttling is active, how is it possible that the temperature
is so high? The current load average is 0.00, 0.04, 0.07.
The system is only under heavy load every day 6:40am for one
hour.

The trip_points are usually 95:0:48:70:65. I set them to these
high values to test how hot the cpu can get with activated
passive cooling and without fan-cooling.

> 
> Of course, then there is active cooling -- fan control...

I prefer passive cooling because i want to avoid that
the fan will ever be turned on.


-- 
Mit freundlichen Gruessen
Bjoern Schmidt

Re: fsb of older cpu

[Stefan Smietanowski]

Hi Bjoern.

> In the System Programming Guide i can read that i can reprogram the
> clock multiplier by setting RESET# to low and A20M#, IGNNE#, LINT[1]
> and LINT[0] to 1111 for 1/2. Unfortunately i dont know how to
> program this in assembler code, i can several programming
> languages, but not yet asm :(
> Can you recommend a good online book?

Think for a moment what happens when you pull RESET# low :)

It... resets the chip thereby resetting the computer.

It also (as far as I know) can't be pulled low by software.

Neither can the other pins.

// Stefan

Re: fsb of older cpu

[Bjoern Schmidt]

Stefan Smietanowski schrieb:
> Hi Bjoern.
> 
>> In the System Programming Guide i can read that i can reprogram the
>> clock multiplier by setting RESET# to low and A20M#, IGNNE#, LINT[1]
>> and LINT[0] to 1111 for 1/2. Unfortunately i dont know how to
>> program this in assembler code, i can several programming
>> languages, but not yet asm :(
>> Can you recommend a good online book?
> 
> 
> Think for a moment what happens when you pull RESET# low :)
> 
> It... resets the chip thereby resetting the computer.

Ooops, you are right. I should better read the whole manual.
Sorry for asking stupid questions...


Greetings
Bjoern Schmidt

Re: fsb of older cpu

[Len Brown]

> root@kilobyte:/proc/acpi/processor/C097# cat power
> active state:        C2
> default state:       C1
> bus master activity: 00000000
> states:
>      C1:              promotion[C2] demotion[--] latency[000] usage[00000240]
>     *C2:              promotion[--] demotion[C1] latency[100] usage[169083068]
>      C3:              <not supported>

latency is in microseconds.  100 is the highest latency C2 can have w/o
being disabled entirely.  (eg. my laptop has C2 latency of 1, and C3
latency of 85)  Though it is not uncommon for desktop chips to not
support C2 at all...


> Do you know a little program to visualize the fadt flags in a human
> readable way?

# cat /proc/acpi/fadt | ~lenb/bin/acpitbl
where acpitbl is a script in pmtools:

http://ftp.kernel.org/pub/linux/kernel/people/lenb/acpi/utils/


will print something like this, which depending on the human, is
readable;-)

Signature:        FACP
Length:           132
Revision:         0x02
Checksum:         0x58
OEMID:            TOSHIB
OEM Table ID:     750
OEM Revision:     0x20030101
Creator ID:       TASM
Creator Revision: 0x04010000
FIRMWARE_CTRL:    0x000eee00
DSDT:             0x1ffd0114
INT_MODEL:        0x00
SCI_INT:          9
SMI_CMD:          0x000000b2
ACPI_ENABLE:      0x71
ACPI_DISABLE:     0x70
S4BIOS_REQ:       0x72
PM1a_EVT_BLK:     0x0000d800
PM1b_EVT_BLK:     0x00000000
PM1a_CNT_BLK:     0x0000d804
PM1b_CNT_BLK:     0x00000000
PM2_CNT_BLK:      0x0000d820
PM_TMR_BLK:       0x0000d808
GPE0_BLK:         0x0000d828
GPE1_BLK:         0x00000000
PM1_EVT_LEN:      4
PM1_CNT_LEN:      2
PM2_CNT_LEN:      1
PM_TM_LEN:        4
GPE0_BLK_LEN:     8
GPE1_BLK_LEN:     0
GPE1_BASE:        0
P_LVL2_LAT:       1
P_LVL3_LAT:       85
FLUSH_SIZE:       0
FLUSH_STRIDE:     0
DUTY_OFFSET:      1
DUTY_WIDTH:       0
DAY_ALRM:         0x0d
MON_ALRM:         0x7e
CENTURY:          0x00
Flags:            0x000004a5