Re: [PATCH] Define wc_wmb, a write barrier for PCI write combining

From: Benjamin LaHaise <bcrl@kvack.org>
To: "Bryan O'Sullivan" <bos@pathscale.com>
Cc: Andrew Morton <akpm@osdl.org>, Andi Kleen <ak@suse.de>,
	linux-kernel <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH] Define wc_wmb, a write barrier for PCI write combining
Date: Tue, 28 Feb 2006 12:58:38 -0500	[thread overview]
Message-ID: <20060228175838.GD24306@kvack.org> (raw)
In-Reply-To: <1141149009.24103.8.camel@camp4.serpentine.com>

On Tue, Feb 28, 2006 at 09:50:08AM -0800, Bryan O'Sullivan wrote:
> The last 32-bit write triggers the chip to put the packet on the wire.
> We make sure it happens after the earlier bulk write using a barrier.

The barrier you're looking for is wmb() in asm/system.h, which is defined 
on both SMP and UP.  On x86 you do not need the sfence as writes will show 
up on the bus in program order, but you do need wmb() to prevent gcc from 
reordering your code.  Adding a new primative only makes things slower as 
the sfence isn't necessary most of the time (it rightly has a dependancy on 
CONFIG_UNORDERED_IO, which the jury is still out on).

		-ben
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