[PATCH 0/8] x86: cacheinfo: cache_disable fixes/cleanup

[PATCH 0/8] x86: cacheinfo: cache_disable fixes/cleanup

[Andreas Herrmann]

These patches primarily split up Mark's latest patch

  [PATCH][retry 6] Conform L3 Cache Index Disable to Linux Standards
  (see http://marc.info/?l=linux-kernel&m=123922420925908&w=2)

into smaller pieces. I prefer to revert the last two patches on
tip/x86/cpu to get a cleaner changelog for the following fixes.

Patches are against tip/x86/cpu as of today.

Please apply.


Thanks,

Andreas

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[PATCH 1/8] Revert "x86, cpu: intel_cacheinfo.c: use cpumask_first(to_cpumask())"

[Andreas Herrmann]

revert "x86, cpu: intel_cacheinfo.c: use cpumask_first(to_cpumask())"
and "x86, cpu: conform L3 Cache Index Disable to Linux standards"

in order to incrementally fix the L3 Cache index disable feature

This reverts commit d42c33ef0a236c6874c748438500c78edfaa1187.

Signed-off-by: Andreas Herrmann <andreas.herrmann3@amd.com>

---
 arch/x86/kernel/cpu/intel_cacheinfo.c |    6 ++----
 1 files changed, 2 insertions(+), 4 deletions(-)

diff --git a/arch/x86/kernel/cpu/intel_cacheinfo.c b/arch/x86/kernel/cpu/intel_cacheinfo.c
index 6f4d2a3..b728325 100644
--- a/arch/x86/kernel/cpu/intel_cacheinfo.c
+++ b/arch/x86/kernel/cpu/intel_cacheinfo.c
@@ -643,8 +643,7 @@ static ssize_t show_##file_name						\
 static ssize_t show_cache_disable(struct _cpuid4_info *this_leaf, char *buf,
 		 unsigned int index)
 {
-	int cpu = cpumask_first(to_cpumask(this_leaf->shared_cpu_map));
-	int node = cpu_to_node(cpu);
+	int node = cpu_to_node(first_cpu(this_leaf->shared_cpu_map));
 	struct pci_dev *dev = k8_northbridges[node];
 	unsigned int reg = 0;
 
@@ -666,8 +665,7 @@ static ssize_t
 store_cache_disable(struct _cpuid4_info *this_leaf, const char *buf,
 		 size_t count, unsigned int index)
 {
-	int cpu = cpumask_first(to_cpumask(this_leaf->shared_cpu_map));
-	int node = cpu_to_node(cpu);
+	int node = cpu_to_node(first_cpu(this_leaf->shared_cpu_map));
 	struct pci_dev *dev = k8_northbridges[node];
 	unsigned long val = 0;
 	unsigned int scrubber = 0;
-- 
1.6.2

[PATCH 2/8] Revert "x86, cpu: conform L3 Cache Index Disable to Linux standards"

[Andreas Herrmann]

revert "x86, cpu: intel_cacheinfo.c: use cpumask_first(to_cpumask())"
and "x86, cpu: conform L3 Cache Index Disable to Linux standards"

in order to incrementally fix the L3 Cache index disable feature

This reverts commit 45ca863a40306ccc99c68d13421b6577240760ca.

CC: Mark Langsdorf <mark.langsdorf@amd.com>
Signed-off-by: Andreas Herrmann <andreas.herrmann3@amd.com>
---
 arch/x86/include/asm/k8.h             |    4 -
 arch/x86/kernel/cpu/intel_cacheinfo.c |  180 +++++++++++++++++++--------------
 2 files changed, 102 insertions(+), 82 deletions(-)

diff --git a/arch/x86/include/asm/k8.h b/arch/x86/include/asm/k8.h
index 0d619c3..54c8cc5 100644
--- a/arch/x86/include/asm/k8.h
+++ b/arch/x86/include/asm/k8.h
@@ -6,11 +6,7 @@
 extern struct pci_device_id k8_nb_ids[];
 
 extern int early_is_k8_nb(u32 value);
-#ifdef CONFIG_K8_NB
 extern struct pci_dev **k8_northbridges;
-#else
-struct pci_dev **k8_northbridges;
-#endif
 extern int num_k8_northbridges;
 extern int cache_k8_northbridges(void);
 extern void k8_flush_garts(void);
diff --git a/arch/x86/kernel/cpu/intel_cacheinfo.c b/arch/x86/kernel/cpu/intel_cacheinfo.c
index b728325..c471eb1 100644
--- a/arch/x86/kernel/cpu/intel_cacheinfo.c
+++ b/arch/x86/kernel/cpu/intel_cacheinfo.c
@@ -18,9 +18,6 @@
 #include <asm/processor.h>
 #include <asm/smp.h>
 
-#include <linux/pci.h>
-#include <asm/k8.h>
-
 #define LVL_1_INST	1
 #define LVL_1_DATA	2
 #define LVL_2		3
@@ -162,6 +159,14 @@ struct _cpuid4_info_regs {
 	unsigned long can_disable;
 };
 
+#ifdef CONFIG_PCI
+static struct pci_device_id k8_nb_id[] = {
+	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, 0x1103) },
+	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, 0x1203) },
+	{}
+};
+#endif
+
 unsigned short			num_cache_leaves;
 
 /* AMD doesn't have CPUID4. Emulate it here to report the same
@@ -286,12 +291,6 @@ amd_check_l3_disable(int index, struct _cpuid4_info_regs *this_leaf)
 {
 	if (index < 3)
 		return;
-	if (boot_cpu_data.x86 == 0x11)
-		return;
-
-	if ((boot_cpu_data.x86 == 0x10) && (boot_cpu_data.x86_model < 0x8))
-		return;
-
 	this_leaf->can_disable = 1;
 }
 
@@ -640,68 +639,6 @@ static ssize_t show_##file_name						\
 	return sprintf (buf, "%lu\n", (unsigned long)this_leaf->object + val); \
 }
 
-static ssize_t show_cache_disable(struct _cpuid4_info *this_leaf, char *buf,
-		 unsigned int index)
-{
-	int node = cpu_to_node(first_cpu(this_leaf->shared_cpu_map));
-	struct pci_dev *dev = k8_northbridges[node];
-	unsigned int reg = 0;
-
-	if (!this_leaf->can_disable)
-		return -EINVAL;
-
-	pci_read_config_dword(dev, 0x1BC + index * 4, &reg);
-	return sprintf(buf, "%x\n", reg);
-}
-
-#define SHOW_CACHE_DISABLE(index)					\
-static ssize_t								\
-show_cache_disable_##index(struct _cpuid4_info *this_leaf, char *buf)  	\
-{									\
-	return show_cache_disable(this_leaf, buf, index);		\
-}
-
-static ssize_t
-store_cache_disable(struct _cpuid4_info *this_leaf, const char *buf,
-		 size_t count, unsigned int index)
-{
-	int node = cpu_to_node(first_cpu(this_leaf->shared_cpu_map));
-	struct pci_dev *dev = k8_northbridges[node];
-	unsigned long val = 0;
-	unsigned int scrubber = 0;
-
-	if (!this_leaf->can_disable)
-		return -EINVAL;
-
-	if (!capable(CAP_SYS_ADMIN))
-		return -EPERM;
-
-	if (strict_strtoul(buf, 10, &val) < 0)
-		return -EINVAL;
-
-	val |= 0xc0000000;
-	pci_read_config_dword(dev, 0x58, &scrubber);
-	scrubber &= ~0x0f800000;
-	pci_write_config_dword(dev, 0x58, scrubber);
-	pci_write_config_dword(dev, 0x1BC + index * 4, val & ~0x40000000);
-	wbinvd();
-	pci_write_config_dword(dev, 0x1BC + index * 4, val);
-	return count;
-}
-
-#define STORE_CACHE_DISABLE(index)					\
-static ssize_t								\
-store_cache_disable_##index(struct _cpuid4_info *this_leaf,	     	\
-		 const char *buf, size_t count)			     	\
-{									\
-	return store_cache_disable(this_leaf, buf, count, index);	\
-}
-
-SHOW_CACHE_DISABLE(0)
-STORE_CACHE_DISABLE(0)
-SHOW_CACHE_DISABLE(1)
-STORE_CACHE_DISABLE(1)
-
 show_one_plus(level, eax.split.level, 0);
 show_one_plus(coherency_line_size, ebx.split.coherency_line_size, 1);
 show_one_plus(physical_line_partition, ebx.split.physical_line_partition, 1);
@@ -759,6 +696,98 @@ static ssize_t show_type(struct _cpuid4_info *this_leaf, char *buf)
 #define to_object(k)	container_of(k, struct _index_kobject, kobj)
 #define to_attr(a)	container_of(a, struct _cache_attr, attr)
 
+#ifdef CONFIG_PCI
+static struct pci_dev *get_k8_northbridge(int node)
+{
+	struct pci_dev *dev = NULL;
+	int i;
+
+	for (i = 0; i <= node; i++) {
+		do {
+			dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev);
+			if (!dev)
+				break;
+		} while (!pci_match_id(&k8_nb_id[0], dev));
+		if (!dev)
+			break;
+	}
+	return dev;
+}
+#else
+static struct pci_dev *get_k8_northbridge(int node)
+{
+	return NULL;
+}
+#endif
+
+static ssize_t show_cache_disable(struct _cpuid4_info *this_leaf, char *buf)
+{
+	const struct cpumask *mask = to_cpumask(this_leaf->shared_cpu_map);
+	int node = cpu_to_node(cpumask_first(mask));
+	struct pci_dev *dev = NULL;
+	ssize_t ret = 0;
+	int i;
+
+	if (!this_leaf->can_disable)
+		return sprintf(buf, "Feature not enabled\n");
+
+	dev = get_k8_northbridge(node);
+	if (!dev) {
+		printk(KERN_ERR "Attempting AMD northbridge operation on a system with no northbridge\n");
+		return -EINVAL;
+	}
+
+	for (i = 0; i < 2; i++) {
+		unsigned int reg;
+
+		pci_read_config_dword(dev, 0x1BC + i * 4, &reg);
+
+		ret += sprintf(buf, "%sEntry: %d\n", buf, i);
+		ret += sprintf(buf, "%sReads:  %s\tNew Entries: %s\n",  
+			buf,
+			reg & 0x80000000 ? "Disabled" : "Allowed",
+			reg & 0x40000000 ? "Disabled" : "Allowed");
+		ret += sprintf(buf, "%sSubCache: %x\tIndex: %x\n",
+			buf, (reg & 0x30000) >> 16, reg & 0xfff);
+	}
+	return ret;
+}
+
+static ssize_t
+store_cache_disable(struct _cpuid4_info *this_leaf, const char *buf,
+		    size_t count)
+{
+	const struct cpumask *mask = to_cpumask(this_leaf->shared_cpu_map);
+	int node = cpu_to_node(cpumask_first(mask));
+	struct pci_dev *dev = NULL;
+	unsigned int ret, index, val;
+
+	if (!this_leaf->can_disable)
+		return 0;
+
+	if (strlen(buf) > 15)
+		return -EINVAL;
+
+	ret = sscanf(buf, "%x %x", &index, &val);
+	if (ret != 2)
+		return -EINVAL;
+	if (index > 1)
+		return -EINVAL;
+
+	val |= 0xc0000000;
+	dev = get_k8_northbridge(node);
+	if (!dev) {
+		printk(KERN_ERR "Attempting AMD northbridge operation on a system with no northbridge\n");
+		return -EINVAL;
+	}
+
+	pci_write_config_dword(dev, 0x1BC + index * 4, val & ~0x40000000);
+	wbinvd();
+	pci_write_config_dword(dev, 0x1BC + index * 4, val);
+
+	return 1;
+}
+
 struct _cache_attr {
 	struct attribute attr;
 	ssize_t (*show)(struct _cpuid4_info *, char *);
@@ -779,11 +808,7 @@ define_one_ro(size);
 define_one_ro(shared_cpu_map);
 define_one_ro(shared_cpu_list);
 
-static struct _cache_attr cache_disable_0 = __ATTR(cache_disable_0, 0644,
-		 show_cache_disable_0, store_cache_disable_0);
-static struct _cache_attr cache_disable_1 = __ATTR(cache_disable_1, 0644,
-		 show_cache_disable_1, store_cache_disable_1);
-
+static struct _cache_attr cache_disable = __ATTR(cache_disable, 0644, show_cache_disable, store_cache_disable);
 
 static struct attribute * default_attrs[] = {
 	&type.attr,
@@ -795,8 +820,7 @@ static struct attribute * default_attrs[] = {
 	&size.attr,
 	&shared_cpu_map.attr,
 	&shared_cpu_list.attr,
-	&cache_disable_0.attr,
-	&cache_disable_1.attr,
+	&cache_disable.attr,
 	NULL
 };
 
-- 
1.6.2

[PATCH 3/8] x86: cacheinfo: use L3 cache index disable feature only for CPUs that support it

[Andreas Herrmann]

AMD family 0x11 CPU doesn't support the feature.

Some AMD family 0x10 CPUs do not support it or have an erratum, see
erratum #382 in "Revision Guide for AMD Family 10h Processors, 41322
Rev. 3.40 February 2009".

CC: Mark Langsdorf <mark.langsdorf@amd.com>
Signed-off-by: Andreas Herrmann <andreas.herrmann3@amd.com>
---
 arch/x86/kernel/cpu/intel_cacheinfo.c |    8 ++++++++
 1 files changed, 8 insertions(+), 0 deletions(-)

diff --git a/arch/x86/kernel/cpu/intel_cacheinfo.c b/arch/x86/kernel/cpu/intel_cacheinfo.c
index c471eb1..3973506 100644
--- a/arch/x86/kernel/cpu/intel_cacheinfo.c
+++ b/arch/x86/kernel/cpu/intel_cacheinfo.c
@@ -291,6 +291,14 @@ amd_check_l3_disable(int index, struct _cpuid4_info_regs *this_leaf)
 {
 	if (index < 3)
 		return;
+
+	if (boot_cpu_data.x86 == 0x11)
+		return;
+
+	/* see erratum #382 */
+	if ((boot_cpu_data.x86 == 0x10) && (boot_cpu_data.x86_model < 0x8))
+		return;
+
 	this_leaf->can_disable = 1;
 }
 
-- 
1.6.2

[PATCH 4/8] x86: cacheinfo: correct return value when cache_disable feature is not active

[Andreas Herrmann]

Impact: bug fix

If user writes to "cache_disable" attribute on a CPU that does not support
this feature, the process hangs due to an invalid return value in
store_cache_disable().

CC: Mark Langsdorf <mark.langsdorf@amd.com>
Signed-off-by: Andreas Herrmann <andreas.herrmann3@amd.com>
---
 arch/x86/kernel/cpu/intel_cacheinfo.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/x86/kernel/cpu/intel_cacheinfo.c b/arch/x86/kernel/cpu/intel_cacheinfo.c
index 3973506..9dac235 100644
--- a/arch/x86/kernel/cpu/intel_cacheinfo.c
+++ b/arch/x86/kernel/cpu/intel_cacheinfo.c
@@ -771,7 +771,7 @@ store_cache_disable(struct _cpuid4_info *this_leaf, const char *buf,
 	unsigned int ret, index, val;
 
 	if (!this_leaf->can_disable)
-		return 0;
+		return -EINVAL;
 
 	if (strlen(buf) > 15)
 		return -EINVAL;
-- 
1.6.2

[PATCH 5/8] x86: cacheinfo: use cached K8 NB_MISC devices instead of scanning for it

[Andreas Herrmann]

Impact: avoid code duplication

CC: Mark Langsdorf <mark.langsdorf@amd.com>
Signed-off-by: Andreas Herrmann <andreas.herrmann3@amd.com>
---
 arch/x86/include/asm/k8.h             |    8 +++++++
 arch/x86/kernel/cpu/intel_cacheinfo.c |   37 ++------------------------------
 2 files changed, 11 insertions(+), 34 deletions(-)

Ingo,

you have asked for a function to replace the exported
k8_northbridges array.

Actually this is a good idea and I'll look at it.
But this also requires additional changes in pci-gart_64.c
And I don't like to mix such changes with this cache_disable stuff.

For the time beeing I provide a small macro to access the array.

Regards,
Andreas


diff --git a/arch/x86/include/asm/k8.h b/arch/x86/include/asm/k8.h
index 54c8cc5..c23b3d1 100644
--- a/arch/x86/include/asm/k8.h
+++ b/arch/x86/include/asm/k8.h
@@ -12,4 +12,12 @@ extern int cache_k8_northbridges(void);
 extern void k8_flush_garts(void);
 extern int k8_scan_nodes(unsigned long start, unsigned long end);
 
+#ifdef CONFIG_K8_NB
+#define node_to_k8_nb_misc(node) \
+	(node < num_k8_northbridges) ? k8_northbridges[node] : NULL
+#else
+#define node_to_k8_nb_misc(node) NULL
+#endif
+
+
 #endif /* _ASM_X86_K8_H */
diff --git a/arch/x86/kernel/cpu/intel_cacheinfo.c b/arch/x86/kernel/cpu/intel_cacheinfo.c
index 9dac235..50f7b88 100644
--- a/arch/x86/kernel/cpu/intel_cacheinfo.c
+++ b/arch/x86/kernel/cpu/intel_cacheinfo.c
@@ -17,6 +17,7 @@
 
 #include <asm/processor.h>
 #include <asm/smp.h>
+#include <asm/k8.h>
 
 #define LVL_1_INST	1
 #define LVL_1_DATA	2
@@ -159,14 +160,6 @@ struct _cpuid4_info_regs {
 	unsigned long can_disable;
 };
 
-#ifdef CONFIG_PCI
-static struct pci_device_id k8_nb_id[] = {
-	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, 0x1103) },
-	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, 0x1203) },
-	{}
-};
-#endif
-
 unsigned short			num_cache_leaves;
 
 /* AMD doesn't have CPUID4. Emulate it here to report the same
@@ -704,30 +697,6 @@ static ssize_t show_type(struct _cpuid4_info *this_leaf, char *buf)
 #define to_object(k)	container_of(k, struct _index_kobject, kobj)
 #define to_attr(a)	container_of(a, struct _cache_attr, attr)
 
-#ifdef CONFIG_PCI
-static struct pci_dev *get_k8_northbridge(int node)
-{
-	struct pci_dev *dev = NULL;
-	int i;
-
-	for (i = 0; i <= node; i++) {
-		do {
-			dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev);
-			if (!dev)
-				break;
-		} while (!pci_match_id(&k8_nb_id[0], dev));
-		if (!dev)
-			break;
-	}
-	return dev;
-}
-#else
-static struct pci_dev *get_k8_northbridge(int node)
-{
-	return NULL;
-}
-#endif
-
 static ssize_t show_cache_disable(struct _cpuid4_info *this_leaf, char *buf)
 {
 	const struct cpumask *mask = to_cpumask(this_leaf->shared_cpu_map);
@@ -739,7 +708,7 @@ static ssize_t show_cache_disable(struct _cpuid4_info *this_leaf, char *buf)
 	if (!this_leaf->can_disable)
 		return sprintf(buf, "Feature not enabled\n");
 
-	dev = get_k8_northbridge(node);
+	dev = node_to_k8_nb_misc(node);
 	if (!dev) {
 		printk(KERN_ERR "Attempting AMD northbridge operation on a system with no northbridge\n");
 		return -EINVAL;
@@ -783,7 +752,7 @@ store_cache_disable(struct _cpuid4_info *this_leaf, const char *buf,
 		return -EINVAL;
 
 	val |= 0xc0000000;
-	dev = get_k8_northbridge(node);
+	dev = node_to_k8_nb_misc(node);
 	if (!dev) {
 		printk(KERN_ERR "Attempting AMD northbridge operation on a system with no northbridge\n");
 		return -EINVAL;
-- 
1.6.2

[PATCH 6/8] x86: cacheinfo: replace sysfs interface for cache_disable feature

[Andreas Herrmann]

From: Mark Langsdorf <mark.langsdorf@amd.com>

Impact: replace sysfs attribute

Current interface violates against "one-value-per-sysfs-attribute
rule". This patch replaces current attribute with two attributes --
one for each L3 Cache Index Disable register.

Signed-off-by: Mark Langsdorf <mark.langsdorf@amd.com>
Signed-off-by: Andreas Herrmann <andreas.herrmann3@amd.com>
---
 arch/x86/kernel/cpu/intel_cacheinfo.c |   90 ++++++++++++++++----------------
 1 files changed, 45 insertions(+), 45 deletions(-)

diff --git a/arch/x86/kernel/cpu/intel_cacheinfo.c b/arch/x86/kernel/cpu/intel_cacheinfo.c
index 50f7b88..55d134f 100644
--- a/arch/x86/kernel/cpu/intel_cacheinfo.c
+++ b/arch/x86/kernel/cpu/intel_cacheinfo.c
@@ -697,73 +697,69 @@ static ssize_t show_type(struct _cpuid4_info *this_leaf, char *buf)
 #define to_object(k)	container_of(k, struct _index_kobject, kobj)
 #define to_attr(a)	container_of(a, struct _cache_attr, attr)
 
-static ssize_t show_cache_disable(struct _cpuid4_info *this_leaf, char *buf)
+static ssize_t show_cache_disable(struct _cpuid4_info *this_leaf, char *buf,
+				  unsigned int index)
 {
-	const struct cpumask *mask = to_cpumask(this_leaf->shared_cpu_map);
-	int node = cpu_to_node(cpumask_first(mask));
-	struct pci_dev *dev = NULL;
-	ssize_t ret = 0;
-	int i;
+	int cpu = cpumask_first(to_cpumask(this_leaf->shared_cpu_map));
+	int node = cpu_to_node(cpu);
+	struct pci_dev *dev = node_to_k8_nb_misc(node);
+	unsigned int reg = 0;
 
 	if (!this_leaf->can_disable)
-		return sprintf(buf, "Feature not enabled\n");
-
-	dev = node_to_k8_nb_misc(node);
-	if (!dev) {
-		printk(KERN_ERR "Attempting AMD northbridge operation on a system with no northbridge\n");
 		return -EINVAL;
-	}
 
-	for (i = 0; i < 2; i++) {
-		unsigned int reg;
+	if (!dev)
+		return -EINVAL;
 
-		pci_read_config_dword(dev, 0x1BC + i * 4, &reg);
+	pci_read_config_dword(dev, 0x1BC + index * 4, &reg);
+	return sprintf(buf, "%x\n", reg);
+}
 
-		ret += sprintf(buf, "%sEntry: %d\n", buf, i);
-		ret += sprintf(buf, "%sReads:  %s\tNew Entries: %s\n",  
-			buf,
-			reg & 0x80000000 ? "Disabled" : "Allowed",
-			reg & 0x40000000 ? "Disabled" : "Allowed");
-		ret += sprintf(buf, "%sSubCache: %x\tIndex: %x\n",
-			buf, (reg & 0x30000) >> 16, reg & 0xfff);
-	}
-	return ret;
+#define SHOW_CACHE_DISABLE(index)					\
+static ssize_t								\
+show_cache_disable_##index(struct _cpuid4_info *this_leaf, char *buf)  	\
+{									\
+	return show_cache_disable(this_leaf, buf, index);		\
 }
+SHOW_CACHE_DISABLE(0)
+SHOW_CACHE_DISABLE(1)
 
-static ssize_t
-store_cache_disable(struct _cpuid4_info *this_leaf, const char *buf,
-		    size_t count)
+static ssize_t store_cache_disable(struct _cpuid4_info *this_leaf,
+	const char *buf, size_t count, unsigned int index)
 {
-	const struct cpumask *mask = to_cpumask(this_leaf->shared_cpu_map);
-	int node = cpu_to_node(cpumask_first(mask));
-	struct pci_dev *dev = NULL;
-	unsigned int ret, index, val;
+	int cpu = cpumask_first(to_cpumask(this_leaf->shared_cpu_map));
+	int node = cpu_to_node(cpu);
+	struct pci_dev *dev = node_to_k8_nb_misc(node);
+	unsigned long val = 0;
 
 	if (!this_leaf->can_disable)
 		return -EINVAL;
 
-	if (strlen(buf) > 15)
-		return -EINVAL;
+	if (!capable(CAP_SYS_ADMIN))
+		return -EPERM;
 
-	ret = sscanf(buf, "%x %x", &index, &val);
-	if (ret != 2)
-		return -EINVAL;
-	if (index > 1)
+	if (!dev)
 		return -EINVAL;
 
-	val |= 0xc0000000;
-	dev = node_to_k8_nb_misc(node);
-	if (!dev) {
-		printk(KERN_ERR "Attempting AMD northbridge operation on a system with no northbridge\n");
+	if (strict_strtoul(buf, 10, &val) < 0)
 		return -EINVAL;
-	}
 
+	val |= 0xc0000000;
 	pci_write_config_dword(dev, 0x1BC + index * 4, val & ~0x40000000);
 	wbinvd();
 	pci_write_config_dword(dev, 0x1BC + index * 4, val);
+	return count;
+}
 
-	return 1;
+#define STORE_CACHE_DISABLE(index)					\
+static ssize_t								\
+store_cache_disable_##index(struct _cpuid4_info *this_leaf,	     	\
+			    const char *buf, size_t count)		\
+{									\
+	return store_cache_disable(this_leaf, buf, count, index);	\
 }
+STORE_CACHE_DISABLE(0)
+STORE_CACHE_DISABLE(1)
 
 struct _cache_attr {
 	struct attribute attr;
@@ -785,7 +781,10 @@ define_one_ro(size);
 define_one_ro(shared_cpu_map);
 define_one_ro(shared_cpu_list);
 
-static struct _cache_attr cache_disable = __ATTR(cache_disable, 0644, show_cache_disable, store_cache_disable);
+static struct _cache_attr cache_disable_0 = __ATTR(cache_disable_0, 0644,
+		show_cache_disable_0, store_cache_disable_0);
+static struct _cache_attr cache_disable_1 = __ATTR(cache_disable_1, 0644,
+		show_cache_disable_1, store_cache_disable_1);
 
 static struct attribute * default_attrs[] = {
 	&type.attr,
@@ -797,7 +796,8 @@ static struct attribute * default_attrs[] = {
 	&size.attr,
 	&shared_cpu_map.attr,
 	&shared_cpu_list.attr,
-	&cache_disable.attr,
+	&cache_disable_0.attr,
+	&cache_disable_1.attr,
 	NULL
 };
 
-- 
1.6.2

[PATCH 7/8] x86: cacheinfo: disable L3 ECC scrubbing when L3 cache index is disabled

[Andreas Herrmann]

From: Mark Langsdorf <mark.langsdorf@amd.com>

x86: cacheinfo: disable L3 ECC scrubbing when L3 cache index is disabled

(Use correct mask to zero out bits 24-28 by Andreas)

Signed-off-by: Mark Langsdorf <mark.langsdorf@amd.com>
Signed-off-by: Andreas Herrmann <andreas.herrmann3@amd.com>
---
 arch/x86/kernel/cpu/intel_cacheinfo.c |    6 ++++++
 1 files changed, 6 insertions(+), 0 deletions(-)

diff --git a/arch/x86/kernel/cpu/intel_cacheinfo.c b/arch/x86/kernel/cpu/intel_cacheinfo.c
index 55d134f..47e4fb4 100644
--- a/arch/x86/kernel/cpu/intel_cacheinfo.c
+++ b/arch/x86/kernel/cpu/intel_cacheinfo.c
@@ -731,6 +731,7 @@ static ssize_t store_cache_disable(struct _cpuid4_info *this_leaf,
 	int node = cpu_to_node(cpu);
 	struct pci_dev *dev = node_to_k8_nb_misc(node);
 	unsigned long val = 0;
+	unsigned int scrubber = 0;
 
 	if (!this_leaf->can_disable)
 		return -EINVAL;
@@ -745,6 +746,11 @@ static ssize_t store_cache_disable(struct _cpuid4_info *this_leaf,
 		return -EINVAL;
 
 	val |= 0xc0000000;
+
+	pci_read_config_dword(dev, 0x58, &scrubber);
+	scrubber &= ~0x1f000000;
+	pci_write_config_dword(dev, 0x58, scrubber);
+
 	pci_write_config_dword(dev, 0x1BC + index * 4, val & ~0x40000000);
 	wbinvd();
 	pci_write_config_dword(dev, 0x1BC + index * 4, val);
-- 
1.6.2

[PATCH 8/8] x86/docs: add description for cache_disable sysfs interface

[Andreas Herrmann]

From: Mark Langsdorf <mark.langsdorf@amd.com>

Signed-off-by: Mark Langsdorf <mark.langsdorf@amd.com>
Signed-off-by: Andreas Herrmann <andreas.herrmann3@amd.com>
---
 .../ABI/testing/sysfs-devices-cache_disable        |   18 ++++++++++++++++++
 1 files changed, 18 insertions(+), 0 deletions(-)
 create mode 100644 Documentation/ABI/testing/sysfs-devices-cache_disable

Oops, shouldn't Date and KernelVersion be adapted to reflect 2.6.30
and say June 2009.

I don't know.

Regards,
Andreas


diff --git a/Documentation/ABI/testing/sysfs-devices-cache_disable b/Documentation/ABI/testing/sysfs-devices-cache_disable
new file mode 100644
index 0000000..175bb4f
--- /dev/null
+++ b/Documentation/ABI/testing/sysfs-devices-cache_disable
@@ -0,0 +1,18 @@
+What:      /sys/devices/system/cpu/cpu*/cache/index*/cache_disable_X
+Date:      August 2008
+KernelVersion:	2.6.27
+Contact:	mark.langsdorf@amd.com
+Description:	These files exist in every cpu's cache index directories.
+		There are currently 2 cache_disable_# files in each
+		directory.  Reading from these files on a supported
+		processor will return that cache disable index value
+		for that processor and node.  Writing to one of these
+		files will cause the specificed cache index to be disabled.
+
+		Currently, only AMD Family 10h Processors support cache index
+		disable, and only for their L3 caches.  See the BIOS and
+		Kernel Developer's Guide at
+		http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/31116-Public-GH-BKDG_3.20_2-4-09.pdf
+		for formatting information and other details on the
+		cache index disable.
+Users:    joachim.deguara@amd.com
-- 
1.6.2

Re: [PATCH 0/8] x86: cacheinfo: cache_disable fixes/cleanup

[Ingo Molnar]

* Andreas Herrmann <andreas.herrmann3@amd.com> wrote:

> These patches primarily split up Mark's latest patch
> 
>   [PATCH][retry 6] Conform L3 Cache Index Disable to Linux Standards
>   (see http://marc.info/?l=linux-kernel&m=123922420925908&w=2)
> 
> into smaller pieces. I prefer to revert the last two patches on
> tip/x86/cpu to get a cleaner changelog for the following fixes.
> 
> Patches are against tip/x86/cpu as of today.
> 
> Please apply.

thanks, applied - this series looks much nicer!

I rebased the topic to get rid of the double revert sequence, and 
have started testing it.

Thanks,

	Ingo

[tip:x86/cpu] x86: cacheinfo: use L3 cache index disable feature only for CPUs that support it

[Andreas Herrmann]

Commit-ID:  bda869c614c937c318547c3ee1d65a316b693c21
Gitweb:     http://git.kernel.org/tip/bda869c614c937c318547c3ee1d65a316b693c21
Author:     Andreas Herrmann <andreas.herrmann3@amd.com>
AuthorDate: Thu, 9 Apr 2009 15:05:10 +0200
Committer:  Ingo Molnar <mingo@elte.hu>
CommitDate: Fri, 10 Apr 2009 14:21:40 +0200

x86: cacheinfo: use L3 cache index disable feature only for CPUs that support it

AMD family 0x11 CPU doesn't support the feature.

Some AMD family 0x10 CPUs do not support it or have an erratum, see
erratum #382 in "Revision Guide for AMD Family 10h Processors, 41322
Rev. 3.40 February 2009".

Signed-off-by: Andreas Herrmann <andreas.herrmann3@amd.com>
CC: Mark Langsdorf <mark.langsdorf@amd.com>
Cc: Andrew Morton <akpm@linux-foundation.org>
LKML-Reference: <20090409130510.GG31527@alberich.amd.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>


---
 arch/x86/kernel/cpu/intel_cacheinfo.c |    8 ++++++++
 1 files changed, 8 insertions(+), 0 deletions(-)

diff --git a/arch/x86/kernel/cpu/intel_cacheinfo.c b/arch/x86/kernel/cpu/intel_cacheinfo.c
index 483eda9..7240126 100644
--- a/arch/x86/kernel/cpu/intel_cacheinfo.c
+++ b/arch/x86/kernel/cpu/intel_cacheinfo.c
@@ -291,6 +291,14 @@ amd_check_l3_disable(int index, struct _cpuid4_info_regs *this_leaf)
 {
 	if (index < 3)
 		return;
+
+	if (boot_cpu_data.x86 == 0x11)
+		return;
+
+	/* see erratum #382 */
+	if ((boot_cpu_data.x86 == 0x10) && (boot_cpu_data.x86_model < 0x8))
+		return;
+
 	this_leaf->can_disable = 1;
 }
 

[tip:x86/cpu] x86: cacheinfo: correct return value when cache_disable feature is not active

[Andreas Herrmann]

Commit-ID:  845d8c761ec763871936c62b837c4a9ea6d0fbdb
Gitweb:     http://git.kernel.org/tip/845d8c761ec763871936c62b837c4a9ea6d0fbdb
Author:     Andreas Herrmann <andreas.herrmann3@amd.com>
AuthorDate: Thu, 9 Apr 2009 15:07:29 +0200
Committer:  Ingo Molnar <mingo@elte.hu>
CommitDate: Fri, 10 Apr 2009 14:21:42 +0200

x86: cacheinfo: correct return value when cache_disable feature is not active

Impact: bug fix

If user writes to "cache_disable" attribute on a CPU that does not support
this feature, the process hangs due to an invalid return value in
store_cache_disable().

Signed-off-by: Andreas Herrmann <andreas.herrmann3@amd.com>
Cc: Andrew Morton <akpm@linux-foundation.org>
Cc: Mark Langsdorf <mark.langsdorf@amd.com>
LKML-Reference: <20090409130729.GH31527@alberich.amd.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>


---
 arch/x86/kernel/cpu/intel_cacheinfo.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/x86/kernel/cpu/intel_cacheinfo.c b/arch/x86/kernel/cpu/intel_cacheinfo.c
index 7240126..1ab46e0 100644
--- a/arch/x86/kernel/cpu/intel_cacheinfo.c
+++ b/arch/x86/kernel/cpu/intel_cacheinfo.c
@@ -771,7 +771,7 @@ store_cache_disable(struct _cpuid4_info *this_leaf, const char *buf,
 	unsigned int ret, index, val;
 
 	if (!this_leaf->can_disable)
-		return 0;
+		return -EINVAL;
 
 	if (strlen(buf) > 15)
 		return -EINVAL;

[tip:x86/cpu] x86: cacheinfo: use cached K8 NB_MISC devices instead of scanning for it

[Andreas Herrmann]

Commit-ID:  afd9fceec55225d33be878927056a548c2eef26c
Gitweb:     http://git.kernel.org/tip/afd9fceec55225d33be878927056a548c2eef26c
Author:     Andreas Herrmann <andreas.herrmann3@amd.com>
AuthorDate: Thu, 9 Apr 2009 15:16:17 +0200
Committer:  Ingo Molnar <mingo@elte.hu>
CommitDate: Fri, 10 Apr 2009 14:21:49 +0200

x86: cacheinfo: use cached K8 NB_MISC devices instead of scanning for it

Impact: avoid code duplication

Signed-off-by: Andreas Herrmann <andreas.herrmann3@amd.com>
Cc: Andrew Morton <akpm@linux-foundation.org>
Cc: Mark Langsdorf <mark.langsdorf@amd.com>
LKML-Reference: <20090409131617.GI31527@alberich.amd.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>


---
 arch/x86/include/asm/k8.h             |    8 +++++++
 arch/x86/kernel/cpu/intel_cacheinfo.c |   37 ++------------------------------
 2 files changed, 11 insertions(+), 34 deletions(-)

diff --git a/arch/x86/include/asm/k8.h b/arch/x86/include/asm/k8.h
index 54c8cc5..c23b3d1 100644
--- a/arch/x86/include/asm/k8.h
+++ b/arch/x86/include/asm/k8.h
@@ -12,4 +12,12 @@ extern int cache_k8_northbridges(void);
 extern void k8_flush_garts(void);
 extern int k8_scan_nodes(unsigned long start, unsigned long end);
 
+#ifdef CONFIG_K8_NB
+#define node_to_k8_nb_misc(node) \
+	(node < num_k8_northbridges) ? k8_northbridges[node] : NULL
+#else
+#define node_to_k8_nb_misc(node) NULL
+#endif
+
+
 #endif /* _ASM_X86_K8_H */
diff --git a/arch/x86/kernel/cpu/intel_cacheinfo.c b/arch/x86/kernel/cpu/intel_cacheinfo.c
index 1ab46e0..0cde071 100644
--- a/arch/x86/kernel/cpu/intel_cacheinfo.c
+++ b/arch/x86/kernel/cpu/intel_cacheinfo.c
@@ -17,6 +17,7 @@
 
 #include <asm/processor.h>
 #include <asm/smp.h>
+#include <asm/k8.h>
 
 #define LVL_1_INST	1
 #define LVL_1_DATA	2
@@ -159,14 +160,6 @@ struct _cpuid4_info_regs {
 	unsigned long can_disable;
 };
 
-#if defined(CONFIG_PCI) && defined(CONFIG_SYSFS)
-static struct pci_device_id k8_nb_id[] = {
-	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, 0x1103) },
-	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, 0x1203) },
-	{}
-};
-#endif
-
 unsigned short			num_cache_leaves;
 
 /* AMD doesn't have CPUID4. Emulate it here to report the same
@@ -704,30 +697,6 @@ static ssize_t show_type(struct _cpuid4_info *this_leaf, char *buf)
 #define to_object(k)	container_of(k, struct _index_kobject, kobj)
 #define to_attr(a)	container_of(a, struct _cache_attr, attr)
 
-#ifdef CONFIG_PCI
-static struct pci_dev *get_k8_northbridge(int node)
-{
-	struct pci_dev *dev = NULL;
-	int i;
-
-	for (i = 0; i <= node; i++) {
-		do {
-			dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev);
-			if (!dev)
-				break;
-		} while (!pci_match_id(&k8_nb_id[0], dev));
-		if (!dev)
-			break;
-	}
-	return dev;
-}
-#else
-static struct pci_dev *get_k8_northbridge(int node)
-{
-	return NULL;
-}
-#endif
-
 static ssize_t show_cache_disable(struct _cpuid4_info *this_leaf, char *buf)
 {
 	const struct cpumask *mask = to_cpumask(this_leaf->shared_cpu_map);
@@ -739,7 +708,7 @@ static ssize_t show_cache_disable(struct _cpuid4_info *this_leaf, char *buf)
 	if (!this_leaf->can_disable)
 		return sprintf(buf, "Feature not enabled\n");
 
-	dev = get_k8_northbridge(node);
+	dev = node_to_k8_nb_misc(node);
 	if (!dev) {
 		printk(KERN_ERR "Attempting AMD northbridge operation on a system with no northbridge\n");
 		return -EINVAL;
@@ -783,7 +752,7 @@ store_cache_disable(struct _cpuid4_info *this_leaf, const char *buf,
 		return -EINVAL;
 
 	val |= 0xc0000000;
-	dev = get_k8_northbridge(node);
+	dev = node_to_k8_nb_misc(node);
 	if (!dev) {
 		printk(KERN_ERR "Attempting AMD northbridge operation on a system with no northbridge\n");
 		return -EINVAL;

[tip:x86/cpu] x86: cacheinfo: replace sysfs interface for cache_disable feature

[Mark Langsdorf]

Commit-ID:  f8b201fc7110c3673437254e8ba02451461ece0b
Gitweb:     http://git.kernel.org/tip/f8b201fc7110c3673437254e8ba02451461ece0b
Author:     Mark Langsdorf <mark.langsdorf@amd.com>
AuthorDate: Thu, 9 Apr 2009 15:18:49 +0200
Committer:  Ingo Molnar <mingo@elte.hu>
CommitDate: Fri, 10 Apr 2009 14:21:53 +0200

x86: cacheinfo: replace sysfs interface for cache_disable feature

Impact: replace sysfs attribute

Current interface violates against "one-value-per-sysfs-attribute
rule". This patch replaces current attribute with two attributes --
one for each L3 Cache Index Disable register.

Signed-off-by: Mark Langsdorf <mark.langsdorf@amd.com>
Signed-off-by: Andreas Herrmann <andreas.herrmann3@amd.com>
Cc: Andrew Morton <akpm@linux-foundation.org>
LKML-Reference: <20090409131849.GJ31527@alberich.amd.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>


---
 arch/x86/kernel/cpu/intel_cacheinfo.c |   90 ++++++++++++++++----------------
 1 files changed, 45 insertions(+), 45 deletions(-)

diff --git a/arch/x86/kernel/cpu/intel_cacheinfo.c b/arch/x86/kernel/cpu/intel_cacheinfo.c
index 0cde071..fc28291 100644
--- a/arch/x86/kernel/cpu/intel_cacheinfo.c
+++ b/arch/x86/kernel/cpu/intel_cacheinfo.c
@@ -697,73 +697,69 @@ static ssize_t show_type(struct _cpuid4_info *this_leaf, char *buf)
 #define to_object(k)	container_of(k, struct _index_kobject, kobj)
 #define to_attr(a)	container_of(a, struct _cache_attr, attr)
 
-static ssize_t show_cache_disable(struct _cpuid4_info *this_leaf, char *buf)
+static ssize_t show_cache_disable(struct _cpuid4_info *this_leaf, char *buf,
+				  unsigned int index)
 {
-	const struct cpumask *mask = to_cpumask(this_leaf->shared_cpu_map);
-	int node = cpu_to_node(cpumask_first(mask));
-	struct pci_dev *dev = NULL;
-	ssize_t ret = 0;
-	int i;
+	int cpu = cpumask_first(to_cpumask(this_leaf->shared_cpu_map));
+	int node = cpu_to_node(cpu);
+	struct pci_dev *dev = node_to_k8_nb_misc(node);
+	unsigned int reg = 0;
 
 	if (!this_leaf->can_disable)
-		return sprintf(buf, "Feature not enabled\n");
-
-	dev = node_to_k8_nb_misc(node);
-	if (!dev) {
-		printk(KERN_ERR "Attempting AMD northbridge operation on a system with no northbridge\n");
 		return -EINVAL;
-	}
 
-	for (i = 0; i < 2; i++) {
-		unsigned int reg;
+	if (!dev)
+		return -EINVAL;
 
-		pci_read_config_dword(dev, 0x1BC + i * 4, &reg);
+	pci_read_config_dword(dev, 0x1BC + index * 4, &reg);
+	return sprintf(buf, "%x\n", reg);
+}
 
-		ret += sprintf(buf, "%sEntry: %d\n", buf, i);
-		ret += sprintf(buf, "%sReads:  %s\tNew Entries: %s\n",  
-			buf,
-			reg & 0x80000000 ? "Disabled" : "Allowed",
-			reg & 0x40000000 ? "Disabled" : "Allowed");
-		ret += sprintf(buf, "%sSubCache: %x\tIndex: %x\n",
-			buf, (reg & 0x30000) >> 16, reg & 0xfff);
-	}
-	return ret;
+#define SHOW_CACHE_DISABLE(index)					\
+static ssize_t								\
+show_cache_disable_##index(struct _cpuid4_info *this_leaf, char *buf)  	\
+{									\
+	return show_cache_disable(this_leaf, buf, index);		\
 }
+SHOW_CACHE_DISABLE(0)
+SHOW_CACHE_DISABLE(1)
 
-static ssize_t
-store_cache_disable(struct _cpuid4_info *this_leaf, const char *buf,
-		    size_t count)
+static ssize_t store_cache_disable(struct _cpuid4_info *this_leaf,
+	const char *buf, size_t count, unsigned int index)
 {
-	const struct cpumask *mask = to_cpumask(this_leaf->shared_cpu_map);
-	int node = cpu_to_node(cpumask_first(mask));
-	struct pci_dev *dev = NULL;
-	unsigned int ret, index, val;
+	int cpu = cpumask_first(to_cpumask(this_leaf->shared_cpu_map));
+	int node = cpu_to_node(cpu);
+	struct pci_dev *dev = node_to_k8_nb_misc(node);
+	unsigned long val = 0;
 
 	if (!this_leaf->can_disable)
 		return -EINVAL;
 
-	if (strlen(buf) > 15)
-		return -EINVAL;
+	if (!capable(CAP_SYS_ADMIN))
+		return -EPERM;
 
-	ret = sscanf(buf, "%x %x", &index, &val);
-	if (ret != 2)
-		return -EINVAL;
-	if (index > 1)
+	if (!dev)
 		return -EINVAL;
 
-	val |= 0xc0000000;
-	dev = node_to_k8_nb_misc(node);
-	if (!dev) {
-		printk(KERN_ERR "Attempting AMD northbridge operation on a system with no northbridge\n");
+	if (strict_strtoul(buf, 10, &val) < 0)
 		return -EINVAL;
-	}
 
+	val |= 0xc0000000;
 	pci_write_config_dword(dev, 0x1BC + index * 4, val & ~0x40000000);
 	wbinvd();
 	pci_write_config_dword(dev, 0x1BC + index * 4, val);
+	return count;
+}
 
-	return 1;
+#define STORE_CACHE_DISABLE(index)					\
+static ssize_t								\
+store_cache_disable_##index(struct _cpuid4_info *this_leaf,	     	\
+			    const char *buf, size_t count)		\
+{									\
+	return store_cache_disable(this_leaf, buf, count, index);	\
 }
+STORE_CACHE_DISABLE(0)
+STORE_CACHE_DISABLE(1)
 
 struct _cache_attr {
 	struct attribute attr;
@@ -785,7 +781,10 @@ define_one_ro(size);
 define_one_ro(shared_cpu_map);
 define_one_ro(shared_cpu_list);
 
-static struct _cache_attr cache_disable = __ATTR(cache_disable, 0644, show_cache_disable, store_cache_disable);
+static struct _cache_attr cache_disable_0 = __ATTR(cache_disable_0, 0644,
+		show_cache_disable_0, store_cache_disable_0);
+static struct _cache_attr cache_disable_1 = __ATTR(cache_disable_1, 0644,
+		show_cache_disable_1, store_cache_disable_1);
 
 static struct attribute * default_attrs[] = {
 	&type.attr,
@@ -797,7 +796,8 @@ static struct attribute * default_attrs[] = {
 	&size.attr,
 	&shared_cpu_map.attr,
 	&shared_cpu_list.attr,
-	&cache_disable.attr,
+	&cache_disable_0.attr,
+	&cache_disable_1.attr,
 	NULL
 };
 

[tip:x86/cpu] x86: cacheinfo: disable L3 ECC scrubbing when L3 cache index is disabled

[Mark Langsdorf]

Commit-ID:  ba518bea2db21c72d44a6cbfd825b026ef9cdcb6
Gitweb:     http://git.kernel.org/tip/ba518bea2db21c72d44a6cbfd825b026ef9cdcb6
Author:     Mark Langsdorf <mark.langsdorf@amd.com>
AuthorDate: Thu, 9 Apr 2009 15:24:06 +0200
Committer:  Ingo Molnar <mingo@elte.hu>
CommitDate: Fri, 10 Apr 2009 14:22:34 +0200

x86: cacheinfo: disable L3 ECC scrubbing when L3 cache index is disabled

(Use correct mask to zero out bits 24-28 by Andreas)

Signed-off-by: Mark Langsdorf <mark.langsdorf@amd.com>
Signed-off-by: Andreas Herrmann <andreas.herrmann3@amd.com>
Cc: Andrew Morton <akpm@linux-foundation.org>
LKML-Reference: <20090409132406.GK31527@alberich.amd.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>


---
 arch/x86/kernel/cpu/intel_cacheinfo.c |    6 ++++++
 1 files changed, 6 insertions(+), 0 deletions(-)

diff --git a/arch/x86/kernel/cpu/intel_cacheinfo.c b/arch/x86/kernel/cpu/intel_cacheinfo.c
index fc28291..d46a849 100644
--- a/arch/x86/kernel/cpu/intel_cacheinfo.c
+++ b/arch/x86/kernel/cpu/intel_cacheinfo.c
@@ -731,6 +731,7 @@ static ssize_t store_cache_disable(struct _cpuid4_info *this_leaf,
 	int node = cpu_to_node(cpu);
 	struct pci_dev *dev = node_to_k8_nb_misc(node);
 	unsigned long val = 0;
+	unsigned int scrubber = 0;
 
 	if (!this_leaf->can_disable)
 		return -EINVAL;
@@ -745,6 +746,11 @@ static ssize_t store_cache_disable(struct _cpuid4_info *this_leaf,
 		return -EINVAL;
 
 	val |= 0xc0000000;
+
+	pci_read_config_dword(dev, 0x58, &scrubber);
+	scrubber &= ~0x1f000000;
+	pci_write_config_dword(dev, 0x58, scrubber);
+
 	pci_write_config_dword(dev, 0x1BC + index * 4, val & ~0x40000000);
 	wbinvd();
 	pci_write_config_dword(dev, 0x1BC + index * 4, val);

[tip:x86/cpu] x86/docs: add description for cache_disable sysfs interface

[Mark Langsdorf]

Commit-ID:  2fad2d9bb8310889f3261035b594b4e068b6eb8b
Gitweb:     http://git.kernel.org/tip/2fad2d9bb8310889f3261035b594b4e068b6eb8b
Author:     Mark Langsdorf <mark.langsdorf@amd.com>
AuthorDate: Thu, 9 Apr 2009 15:31:53 +0200
Committer:  Ingo Molnar <mingo@elte.hu>
CommitDate: Fri, 10 Apr 2009 14:22:40 +0200

x86/docs: add description for cache_disable sysfs interface

Signed-off-by: Mark Langsdorf <mark.langsdorf@amd.com>
Signed-off-by: Andreas Herrmann <andreas.herrmann3@amd.com>
Cc: Andrew Morton <akpm@linux-foundation.org>
LKML-Reference: <20090409133153.GL31527@alberich.amd.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>


---
 .../ABI/testing/sysfs-devices-cache_disable        |   18 ++++++++++++++++++
 1 files changed, 18 insertions(+), 0 deletions(-)

diff --git a/Documentation/ABI/testing/sysfs-devices-cache_disable b/Documentation/ABI/testing/sysfs-devices-cache_disable
new file mode 100644
index 0000000..175bb4f
--- /dev/null
+++ b/Documentation/ABI/testing/sysfs-devices-cache_disable
@@ -0,0 +1,18 @@
+What:      /sys/devices/system/cpu/cpu*/cache/index*/cache_disable_X
+Date:      August 2008
+KernelVersion:	2.6.27
+Contact:	mark.langsdorf@amd.com
+Description:	These files exist in every cpu's cache index directories.
+		There are currently 2 cache_disable_# files in each
+		directory.  Reading from these files on a supported
+		processor will return that cache disable index value
+		for that processor and node.  Writing to one of these
+		files will cause the specificed cache index to be disabled.
+
+		Currently, only AMD Family 10h Processors support cache index
+		disable, and only for their L3 caches.  See the BIOS and
+		Kernel Developer's Guide at
+		http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/31116-Public-GH-BKDG_3.20_2-4-09.pdf
+		for formatting information and other details on the
+		cache index disable.
+Users:    joachim.deguara@amd.com

Re: [tip:x86/cpu] x86: cacheinfo: replace sysfs interface for cache_disable feature

[Jaswinder Singh Rajput]

Hello Mark,

On Fri, 2009-04-10 at 12:37 +0000, Mark Langsdorf wrote:
> Commit-ID:  f8b201fc7110c3673437254e8ba02451461ece0b
> Gitweb:     http://git.kernel.org/tip/f8b201fc7110c3673437254e8ba02451461ece0b
> Author:     Mark Langsdorf <mark.langsdorf@amd.com>
> AuthorDate: Thu, 9 Apr 2009 15:18:49 +0200
> Committer:  Ingo Molnar <mingo@elte.hu>
> CommitDate: Fri, 10 Apr 2009 14:21:53 +0200
> 
> x86: cacheinfo: replace sysfs interface for cache_disable feature
> 
> Impact: replace sysfs attribute
> 
> Current interface violates against "one-value-per-sysfs-attribute
> rule". This patch replaces current attribute with two attributes --
> one for each L3 Cache Index Disable register.
> 
> Signed-off-by: Mark Langsdorf <mark.langsdorf@amd.com>
> Signed-off-by: Andreas Herrmann <andreas.herrmann3@amd.com>
> Cc: Andrew Morton <akpm@linux-foundation.org>
> LKML-Reference: <20090409131849.GJ31527@alberich.amd.com>
> Signed-off-by: Ingo Molnar <mingo@elte.hu>
> 
> 
> ---
>  arch/x86/kernel/cpu/intel_cacheinfo.c |   90 ++++++++++++++++----------------
>  1 files changed, 45 insertions(+), 45 deletions(-)
> 
> diff --git a/arch/x86/kernel/cpu/intel_cacheinfo.c b/arch/x86/kernel/cpu/intel_cacheinfo.c
> index 0cde071..fc28291 100644
> --- a/arch/x86/kernel/cpu/intel_cacheinfo.c
> +++ b/arch/x86/kernel/cpu/intel_cacheinfo.c
> @@ -697,73 +697,69 @@ static ssize_t show_type(struct _cpuid4_info *this_leaf, char *buf)
>  #define to_object(k)	container_of(k, struct _index_kobject, kobj)
>  #define to_attr(a)	container_of(a, struct _cache_attr, attr)
>  
> -static ssize_t show_cache_disable(struct _cpuid4_info *this_leaf, char *buf)
> +static ssize_t show_cache_disable(struct _cpuid4_info *this_leaf, char *buf,
> +				  unsigned int index)
>  {
> -	const struct cpumask *mask = to_cpumask(this_leaf->shared_cpu_map);
> -	int node = cpu_to_node(cpumask_first(mask));
> -	struct pci_dev *dev = NULL;
> -	ssize_t ret = 0;
> -	int i;
> +	int cpu = cpumask_first(to_cpumask(this_leaf->shared_cpu_map));
> +	int node = cpu_to_node(cpu);
> +	struct pci_dev *dev = node_to_k8_nb_misc(node);
> +	unsigned int reg = 0;

This leads to compilation warnings:
  CC      arch/x86/kernel/cpu/intel_cacheinfo.o
arch/x86/kernel/cpu/intel_cacheinfo.c: In function ‘show_cache_disable’:
arch/x86/kernel/cpu/intel_cacheinfo.c:712: warning: unused variable ‘node’

>  
> -static ssize_t
> -store_cache_disable(struct _cpuid4_info *this_leaf, const char *buf,
> -		    size_t count)
> +static ssize_t store_cache_disable(struct _cpuid4_info *this_leaf,
> +	const char *buf, size_t count, unsigned int index)
>  {
> -	const struct cpumask *mask = to_cpumask(this_leaf->shared_cpu_map);
> -	int node = cpu_to_node(cpumask_first(mask));
> -	struct pci_dev *dev = NULL;
> -	unsigned int ret, index, val;
> +	int cpu = cpumask_first(to_cpumask(this_leaf->shared_cpu_map));
> +	int node = cpu_to_node(cpu);
> +	struct pci_dev *dev = node_to_k8_nb_misc(node);
> +	unsigned long val = 0;
>  

  CC      arch/x86/kernel/cpu/intel_cacheinfo.o
arch/x86/kernel/cpu/intel_cacheinfo.c: In function ‘store_cache_disable’:
arch/x86/kernel/cpu/intel_cacheinfo.c:737: warning: unused variable ‘cpu’

Thanks,
--
JSR

Re: [tip:x86/cpu] x86: cacheinfo: replace sysfs interface for cache_disable feature

[Jaswinder Singh Rajput]

On Mon, 2009-04-13 at 10:22 +0530, Jaswinder Singh Rajput wrote:
> Hello Mark,
> 
> On Fri, 2009-04-10 at 12:37 +0000, Mark Langsdorf wrote:
> > Commit-ID:  f8b201fc7110c3673437254e8ba02451461ece0b
> > Gitweb:     http://git.kernel.org/tip/f8b201fc7110c3673437254e8ba02451461ece0b
> > Author:     Mark Langsdorf <mark.langsdorf@amd.com>
> > AuthorDate: Thu, 9 Apr 2009 15:18:49 +0200
> > Committer:  Ingo Molnar <mingo@elte.hu>
> > CommitDate: Fri, 10 Apr 2009 14:21:53 +0200
> > 
> > x86: cacheinfo: replace sysfs interface for cache_disable feature
> > 
> > Impact: replace sysfs attribute
> > 
> > Current interface violates against "one-value-per-sysfs-attribute
> > rule". This patch replaces current attribute with two attributes --
> > one for each L3 Cache Index Disable register.
> > 
> > Signed-off-by: Mark Langsdorf <mark.langsdorf@amd.com>
> > Signed-off-by: Andreas Herrmann <andreas.herrmann3@amd.com>
> > Cc: Andrew Morton <akpm@linux-foundation.org>
> > LKML-Reference: <20090409131849.GJ31527@alberich.amd.com>
> > Signed-off-by: Ingo Molnar <mingo@elte.hu>
> > 
> > 
> > ---
> >  arch/x86/kernel/cpu/intel_cacheinfo.c |   90 ++++++++++++++++----------------
> >  1 files changed, 45 insertions(+), 45 deletions(-)
> > 
> > diff --git a/arch/x86/kernel/cpu/intel_cacheinfo.c b/arch/x86/kernel/cpu/intel_cacheinfo.c
> > index 0cde071..fc28291 100644
> > --- a/arch/x86/kernel/cpu/intel_cacheinfo.c
> > +++ b/arch/x86/kernel/cpu/intel_cacheinfo.c
> > @@ -697,73 +697,69 @@ static ssize_t show_type(struct _cpuid4_info *this_leaf, char *buf)
> >  #define to_object(k)	container_of(k, struct _index_kobject, kobj)
> >  #define to_attr(a)	container_of(a, struct _cache_attr, attr)
> >  
> > -static ssize_t show_cache_disable(struct _cpuid4_info *this_leaf, char *buf)
> > +static ssize_t show_cache_disable(struct _cpuid4_info *this_leaf, char *buf,
> > +				  unsigned int index)
> >  {
> > -	const struct cpumask *mask = to_cpumask(this_leaf->shared_cpu_map);
> > -	int node = cpu_to_node(cpumask_first(mask));
> > -	struct pci_dev *dev = NULL;
> > -	ssize_t ret = 0;
> > -	int i;
> > +	int cpu = cpumask_first(to_cpumask(this_leaf->shared_cpu_map));
> > +	int node = cpu_to_node(cpu);
> > +	struct pci_dev *dev = node_to_k8_nb_misc(node);
> > +	unsigned int reg = 0;
> 
> This leads to compilation warnings:
>   CC      arch/x86/kernel/cpu/intel_cacheinfo.o
> arch/x86/kernel/cpu/intel_cacheinfo.c: In function ‘show_cache_disable’:
> arch/x86/kernel/cpu/intel_cacheinfo.c:712: warning: unused variable ‘node’
> 
> >  
> > -static ssize_t
> > -store_cache_disable(struct _cpuid4_info *this_leaf, const char *buf,
> > -		    size_t count)
> > +static ssize_t store_cache_disable(struct _cpuid4_info *this_leaf,
> > +	const char *buf, size_t count, unsigned int index)
> >  {
> > -	const struct cpumask *mask = to_cpumask(this_leaf->shared_cpu_map);
> > -	int node = cpu_to_node(cpumask_first(mask));
> > -	struct pci_dev *dev = NULL;
> > -	unsigned int ret, index, val;
> > +	int cpu = cpumask_first(to_cpumask(this_leaf->shared_cpu_map));
> > +	int node = cpu_to_node(cpu);
> > +	struct pci_dev *dev = node_to_k8_nb_misc(node);
> > +	unsigned long val = 0;
> >  
> 
>   CC      arch/x86/kernel/cpu/intel_cacheinfo.o
> arch/x86/kernel/cpu/intel_cacheinfo.c: In function ‘store_cache_disable’:
> arch/x86/kernel/cpu/intel_cacheinfo.c:737: warning: unused variable ‘cpu’

Oops it is also pointing to node:

arch/x86/kernel/cpu/intel_cacheinfo.c: In function ‘store_cache_disable’:
arch/x86/kernel/cpu/intel_cacheinfo.c:739: warning: unused variable ‘node’

--
JSR

Re: [tip:x86/cpu] x86: cacheinfo: replace sysfs interface for cache_disable feature

[Ingo Molnar]

* Jaswinder Singh Rajput <jaswinder@kernel.org> wrote:

> On Mon, 2009-04-13 at 10:22 +0530, Jaswinder Singh Rajput wrote:
> > Hello Mark,
> > 
> > On Fri, 2009-04-10 at 12:37 +0000, Mark Langsdorf wrote:
> > > Commit-ID:  f8b201fc7110c3673437254e8ba02451461ece0b
> > > Gitweb:     http://git.kernel.org/tip/f8b201fc7110c3673437254e8ba02451461ece0b
> > > Author:     Mark Langsdorf <mark.langsdorf@amd.com>
> > > AuthorDate: Thu, 9 Apr 2009 15:18:49 +0200
> > > Committer:  Ingo Molnar <mingo@elte.hu>
> > > CommitDate: Fri, 10 Apr 2009 14:21:53 +0200
> > > 
> > > x86: cacheinfo: replace sysfs interface for cache_disable feature
> > > 
> > > Impact: replace sysfs attribute
> > > 
> > > Current interface violates against "one-value-per-sysfs-attribute
> > > rule". This patch replaces current attribute with two attributes --
> > > one for each L3 Cache Index Disable register.
> > > 
> > > Signed-off-by: Mark Langsdorf <mark.langsdorf@amd.com>
> > > Signed-off-by: Andreas Herrmann <andreas.herrmann3@amd.com>
> > > Cc: Andrew Morton <akpm@linux-foundation.org>
> > > LKML-Reference: <20090409131849.GJ31527@alberich.amd.com>
> > > Signed-off-by: Ingo Molnar <mingo@elte.hu>
> > > 
> > > 
> > > ---
> > >  arch/x86/kernel/cpu/intel_cacheinfo.c |   90 ++++++++++++++++----------------
> > >  1 files changed, 45 insertions(+), 45 deletions(-)
> > > 
> > > diff --git a/arch/x86/kernel/cpu/intel_cacheinfo.c b/arch/x86/kernel/cpu/intel_cacheinfo.c
> > > index 0cde071..fc28291 100644
> > > --- a/arch/x86/kernel/cpu/intel_cacheinfo.c
> > > +++ b/arch/x86/kernel/cpu/intel_cacheinfo.c
> > > @@ -697,73 +697,69 @@ static ssize_t show_type(struct _cpuid4_info *this_leaf, char *buf)
> > >  #define to_object(k)	container_of(k, struct _index_kobject, kobj)
> > >  #define to_attr(a)	container_of(a, struct _cache_attr, attr)
> > >  
> > > -static ssize_t show_cache_disable(struct _cpuid4_info *this_leaf, char *buf)
> > > +static ssize_t show_cache_disable(struct _cpuid4_info *this_leaf, char *buf,
> > > +				  unsigned int index)
> > >  {
> > > -	const struct cpumask *mask = to_cpumask(this_leaf->shared_cpu_map);
> > > -	int node = cpu_to_node(cpumask_first(mask));
> > > -	struct pci_dev *dev = NULL;
> > > -	ssize_t ret = 0;
> > > -	int i;
> > > +	int cpu = cpumask_first(to_cpumask(this_leaf->shared_cpu_map));
> > > +	int node = cpu_to_node(cpu);
> > > +	struct pci_dev *dev = node_to_k8_nb_misc(node);
> > > +	unsigned int reg = 0;
> > 
> > This leads to compilation warnings:
> >   CC      arch/x86/kernel/cpu/intel_cacheinfo.o
> > arch/x86/kernel/cpu/intel_cacheinfo.c: In function ‘show_cache_disable’:
> > arch/x86/kernel/cpu/intel_cacheinfo.c:712: warning: unused variable ‘node’
> > 
> > >  
> > > -static ssize_t
> > > -store_cache_disable(struct _cpuid4_info *this_leaf, const char *buf,
> > > -		    size_t count)
> > > +static ssize_t store_cache_disable(struct _cpuid4_info *this_leaf,
> > > +	const char *buf, size_t count, unsigned int index)
> > >  {
> > > -	const struct cpumask *mask = to_cpumask(this_leaf->shared_cpu_map);
> > > -	int node = cpu_to_node(cpumask_first(mask));
> > > -	struct pci_dev *dev = NULL;
> > > -	unsigned int ret, index, val;
> > > +	int cpu = cpumask_first(to_cpumask(this_leaf->shared_cpu_map));
> > > +	int node = cpu_to_node(cpu);
> > > +	struct pci_dev *dev = node_to_k8_nb_misc(node);
> > > +	unsigned long val = 0;
> > >  
> > 
> >   CC      arch/x86/kernel/cpu/intel_cacheinfo.o
> > arch/x86/kernel/cpu/intel_cacheinfo.c: In function ‘store_cache_disable’:
> > arch/x86/kernel/cpu/intel_cacheinfo.c:737: warning: unused variable ‘cpu’
> 
> Oops it is also pointing to node:
> 
> arch/x86/kernel/cpu/intel_cacheinfo.c: In function ‘store_cache_disable’:
> arch/x86/kernel/cpu/intel_cacheinfo.c:739: warning: unused variable ‘node’

Mind sending a fix? We really dont want warnings noise in the x86 
tree.

I was also thinking about adopting the Sparc trick: adding -Werror 
to arch/x86/ files only, fixing all the fallout and ensuring no new 
warnings from a flag day on. Anyone interested in doing that?

	Ingo

Re: [tip:x86/cpu] x86: cacheinfo: replace sysfs interface for cache_disable feature

[Jaswinder Singh Rajput]

On Tue, 2009-04-14 at 13:58 +0200, Ingo Molnar wrote:
> * Jaswinder Singh Rajput <jaswinder@kernel.org> wrote:
> 
> > On Mon, 2009-04-13 at 10:22 +0530, Jaswinder Singh Rajput wrote:
> > > Hello Mark,
> > > 
> > > On Fri, 2009-04-10 at 12:37 +0000, Mark Langsdorf wrote:
> > > > Commit-ID:  f8b201fc7110c3673437254e8ba02451461ece0b
> > > > Gitweb:     http://git.kernel.org/tip/f8b201fc7110c3673437254e8ba02451461ece0b
> > > > Author:     Mark Langsdorf <mark.langsdorf@amd.com>
> > > > AuthorDate: Thu, 9 Apr 2009 15:18:49 +0200
> > > > Committer:  Ingo Molnar <mingo@elte.hu>
> > > > CommitDate: Fri, 10 Apr 2009 14:21:53 +0200
> > > > 
> > > > x86: cacheinfo: replace sysfs interface for cache_disable feature
> > > > 
> > > > Impact: replace sysfs attribute
> > > > 
> > > > Current interface violates against "one-value-per-sysfs-attribute
> > > > rule". This patch replaces current attribute with two attributes --
> > > > one for each L3 Cache Index Disable register.
> > > > 
> > > > Signed-off-by: Mark Langsdorf <mark.langsdorf@amd.com>
> > > > Signed-off-by: Andreas Herrmann <andreas.herrmann3@amd.com>
> > > > Cc: Andrew Morton <akpm@linux-foundation.org>
> > > > LKML-Reference: <20090409131849.GJ31527@alberich.amd.com>
> > > > Signed-off-by: Ingo Molnar <mingo@elte.hu>
> > > > 
> > > > 
> > > > ---
> > > >  arch/x86/kernel/cpu/intel_cacheinfo.c |   90 ++++++++++++++++----------------
> > > >  1 files changed, 45 insertions(+), 45 deletions(-)
> > > > 
> > > > diff --git a/arch/x86/kernel/cpu/intel_cacheinfo.c b/arch/x86/kernel/cpu/intel_cacheinfo.c
> > > > index 0cde071..fc28291 100644
> > > > --- a/arch/x86/kernel/cpu/intel_cacheinfo.c
> > > > +++ b/arch/x86/kernel/cpu/intel_cacheinfo.c
> > > > @@ -697,73 +697,69 @@ static ssize_t show_type(struct _cpuid4_info *this_leaf, char *buf)
> > > >  #define to_object(k)	container_of(k, struct _index_kobject, kobj)
> > > >  #define to_attr(a)	container_of(a, struct _cache_attr, attr)
> > > >  
> > > > -static ssize_t show_cache_disable(struct _cpuid4_info *this_leaf, char *buf)
> > > > +static ssize_t show_cache_disable(struct _cpuid4_info *this_leaf, char *buf,
> > > > +				  unsigned int index)
> > > >  {
> > > > -	const struct cpumask *mask = to_cpumask(this_leaf->shared_cpu_map);
> > > > -	int node = cpu_to_node(cpumask_first(mask));
> > > > -	struct pci_dev *dev = NULL;
> > > > -	ssize_t ret = 0;
> > > > -	int i;
> > > > +	int cpu = cpumask_first(to_cpumask(this_leaf->shared_cpu_map));
> > > > +	int node = cpu_to_node(cpu);
> > > > +	struct pci_dev *dev = node_to_k8_nb_misc(node);
> > > > +	unsigned int reg = 0;
> > > 
> > > This leads to compilation warnings:
> > >   CC      arch/x86/kernel/cpu/intel_cacheinfo.o
> > > arch/x86/kernel/cpu/intel_cacheinfo.c: In function ‘show_cache_disable’:
> > > arch/x86/kernel/cpu/intel_cacheinfo.c:712: warning: unused variable ‘node’
> > > 
> > > >  
> > > > -static ssize_t
> > > > -store_cache_disable(struct _cpuid4_info *this_leaf, const char *buf,
> > > > -		    size_t count)
> > > > +static ssize_t store_cache_disable(struct _cpuid4_info *this_leaf,
> > > > +	const char *buf, size_t count, unsigned int index)
> > > >  {
> > > > -	const struct cpumask *mask = to_cpumask(this_leaf->shared_cpu_map);
> > > > -	int node = cpu_to_node(cpumask_first(mask));
> > > > -	struct pci_dev *dev = NULL;
> > > > -	unsigned int ret, index, val;
> > > > +	int cpu = cpumask_first(to_cpumask(this_leaf->shared_cpu_map));
> > > > +	int node = cpu_to_node(cpu);
> > > > +	struct pci_dev *dev = node_to_k8_nb_misc(node);
> > > > +	unsigned long val = 0;
> > > >  
> > > 
> > >   CC      arch/x86/kernel/cpu/intel_cacheinfo.o
> > > arch/x86/kernel/cpu/intel_cacheinfo.c: In function ‘store_cache_disable’:
> > > arch/x86/kernel/cpu/intel_cacheinfo.c:737: warning: unused variable ‘cpu’
> > 
> > Oops it is also pointing to node:
> > 
> > arch/x86/kernel/cpu/intel_cacheinfo.c: In function ‘store_cache_disable’:
> > arch/x86/kernel/cpu/intel_cacheinfo.c:739: warning: unused variable ‘node’
> 
> Mind sending a fix? We really dont want warnings noise in the x86 
> tree.
> 

Ok I send it.

when I fixed node then it gives warnings for :
  arch/x86/kernel/cpu/intel_cacheinfo.c: In function ‘show_cache_disable’:
  arch/x86/kernel/cpu/intel_cacheinfo.c:713: warning: unused variable ‘cpu’

So I also fixed it.


> I was also thinking about adopting the Sparc trick: adding -Werror 
> to arch/x86/ files only, fixing all the fallout and ensuring no new 
> warnings from a flag day on. Anyone interested in doing that?
> 

Yes, this will be nice idea. Should I send patch for:
"adding -Werror to arch/x86/ files only"

Thanks,
--
JSR

Re: [tip:x86/cpu] x86: cacheinfo: replace sysfs interface for cache_disable feature

[Ingo Molnar]

* Jaswinder Singh Rajput <jaswinder@kernel.org> wrote:

> On Tue, 2009-04-14 at 13:58 +0200, Ingo Molnar wrote:
> > * Jaswinder Singh Rajput <jaswinder@kernel.org> wrote:
> > 
> > > On Mon, 2009-04-13 at 10:22 +0530, Jaswinder Singh Rajput wrote:
> > > > Hello Mark,
> > > > 
> > > > On Fri, 2009-04-10 at 12:37 +0000, Mark Langsdorf wrote:
> > > > > Commit-ID:  f8b201fc7110c3673437254e8ba02451461ece0b
> > > > > Gitweb:     http://git.kernel.org/tip/f8b201fc7110c3673437254e8ba02451461ece0b
> > > > > Author:     Mark Langsdorf <mark.langsdorf@amd.com>
> > > > > AuthorDate: Thu, 9 Apr 2009 15:18:49 +0200
> > > > > Committer:  Ingo Molnar <mingo@elte.hu>
> > > > > CommitDate: Fri, 10 Apr 2009 14:21:53 +0200
> > > > > 
> > > > > x86: cacheinfo: replace sysfs interface for cache_disable feature
> > > > > 
> > > > > Impact: replace sysfs attribute
> > > > > 
> > > > > Current interface violates against "one-value-per-sysfs-attribute
> > > > > rule". This patch replaces current attribute with two attributes --
> > > > > one for each L3 Cache Index Disable register.
> > > > > 
> > > > > Signed-off-by: Mark Langsdorf <mark.langsdorf@amd.com>
> > > > > Signed-off-by: Andreas Herrmann <andreas.herrmann3@amd.com>
> > > > > Cc: Andrew Morton <akpm@linux-foundation.org>
> > > > > LKML-Reference: <20090409131849.GJ31527@alberich.amd.com>
> > > > > Signed-off-by: Ingo Molnar <mingo@elte.hu>
> > > > > 
> > > > > 
> > > > > ---
> > > > >  arch/x86/kernel/cpu/intel_cacheinfo.c |   90 ++++++++++++++++----------------
> > > > >  1 files changed, 45 insertions(+), 45 deletions(-)
> > > > > 
> > > > > diff --git a/arch/x86/kernel/cpu/intel_cacheinfo.c b/arch/x86/kernel/cpu/intel_cacheinfo.c
> > > > > index 0cde071..fc28291 100644
> > > > > --- a/arch/x86/kernel/cpu/intel_cacheinfo.c
> > > > > +++ b/arch/x86/kernel/cpu/intel_cacheinfo.c
> > > > > @@ -697,73 +697,69 @@ static ssize_t show_type(struct _cpuid4_info *this_leaf, char *buf)
> > > > >  #define to_object(k)	container_of(k, struct _index_kobject, kobj)
> > > > >  #define to_attr(a)	container_of(a, struct _cache_attr, attr)
> > > > >  
> > > > > -static ssize_t show_cache_disable(struct _cpuid4_info *this_leaf, char *buf)
> > > > > +static ssize_t show_cache_disable(struct _cpuid4_info *this_leaf, char *buf,
> > > > > +				  unsigned int index)
> > > > >  {
> > > > > -	const struct cpumask *mask = to_cpumask(this_leaf->shared_cpu_map);
> > > > > -	int node = cpu_to_node(cpumask_first(mask));
> > > > > -	struct pci_dev *dev = NULL;
> > > > > -	ssize_t ret = 0;
> > > > > -	int i;
> > > > > +	int cpu = cpumask_first(to_cpumask(this_leaf->shared_cpu_map));
> > > > > +	int node = cpu_to_node(cpu);
> > > > > +	struct pci_dev *dev = node_to_k8_nb_misc(node);
> > > > > +	unsigned int reg = 0;
> > > > 
> > > > This leads to compilation warnings:
> > > >   CC      arch/x86/kernel/cpu/intel_cacheinfo.o
> > > > arch/x86/kernel/cpu/intel_cacheinfo.c: In function ‘show_cache_disable’:
> > > > arch/x86/kernel/cpu/intel_cacheinfo.c:712: warning: unused variable ‘node’
> > > > 
> > > > >  
> > > > > -static ssize_t
> > > > > -store_cache_disable(struct _cpuid4_info *this_leaf, const char *buf,
> > > > > -		    size_t count)
> > > > > +static ssize_t store_cache_disable(struct _cpuid4_info *this_leaf,
> > > > > +	const char *buf, size_t count, unsigned int index)
> > > > >  {
> > > > > -	const struct cpumask *mask = to_cpumask(this_leaf->shared_cpu_map);
> > > > > -	int node = cpu_to_node(cpumask_first(mask));
> > > > > -	struct pci_dev *dev = NULL;
> > > > > -	unsigned int ret, index, val;
> > > > > +	int cpu = cpumask_first(to_cpumask(this_leaf->shared_cpu_map));
> > > > > +	int node = cpu_to_node(cpu);
> > > > > +	struct pci_dev *dev = node_to_k8_nb_misc(node);
> > > > > +	unsigned long val = 0;
> > > > >  
> > > > 
> > > >   CC      arch/x86/kernel/cpu/intel_cacheinfo.o
> > > > arch/x86/kernel/cpu/intel_cacheinfo.c: In function ‘store_cache_disable’:
> > > > arch/x86/kernel/cpu/intel_cacheinfo.c:737: warning: unused variable ‘cpu’
> > > 
> > > Oops it is also pointing to node:
> > > 
> > > arch/x86/kernel/cpu/intel_cacheinfo.c: In function ‘store_cache_disable’:
> > > arch/x86/kernel/cpu/intel_cacheinfo.c:739: warning: unused variable ‘node’
> > 
> > Mind sending a fix? We really dont want warnings noise in the x86 
> > tree.
> > 
> 
> Ok I send it.
> 
> when I fixed node then it gives warnings for :
>   arch/x86/kernel/cpu/intel_cacheinfo.c: In function ‘show_cache_disable’:
>   arch/x86/kernel/cpu/intel_cacheinfo.c:713: warning: unused variable ‘cpu’
> 
> So I also fixed it.
> 
> 
> > I was also thinking about adopting the Sparc trick: adding -Werror 
> > to arch/x86/ files only, fixing all the fallout and ensuring no new 
> > warnings from a flag day on. Anyone interested in doing that?
> > 
> 
> Yes, this will be nice idea. Should I send patch for:
> "adding -Werror to arch/x86/ files only"

Yes, that would be nice. Perhaps also first fix all remaining 
warnings on 32-bit and 64-bit defconfig and allnoconfig. (i'll check 
allyesconfig - that takes a lot of time to build)

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