* [PATCH v2 1/8] ARM: tegra: export the chipid
2012-01-31 16:40 [PATCH v2 0/8] Add tegra30 support for secondary cores Peter De Schrijver
@ 2012-01-31 16:40 ` Peter De Schrijver
2012-02-01 7:26 ` Olof Johansson
2012-01-31 16:40 ` [PATCH v2 2/8] ARM: tegra: functions to access the flowcontroller Peter De Schrijver
` (7 subsequent siblings)
8 siblings, 1 reply; 20+ messages in thread
From: Peter De Schrijver @ 2012-01-31 16:40 UTC (permalink / raw)
To: Peter De Schrijver
Cc: Colin Cross, Olof Johansson, Stephen Warren, Russell King,
Gary King, Arnd Bergmann, linux-tegra, linux-arm-kernel,
linux-kernel
Export a variable containing the Tegra chipid. This will be used by the SMP
code to distinguish between Tegra variants. Also initialize the Tegra chipid
on Tegra30.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
---
arch/arm/mach-tegra/common.c | 1 +
arch/arm/mach-tegra/fuse.c | 18 +++++++++++-------
arch/arm/mach-tegra/fuse.h | 4 ++++
3 files changed, 16 insertions(+), 7 deletions(-)
diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c
index 1b1dee0..51dcbdff 100644
--- a/arch/arm/mach-tegra/common.c
+++ b/arch/arm/mach-tegra/common.c
@@ -122,6 +122,7 @@ void __init tegra20_init_early(void)
#ifdef CONFIG_ARCH_TEGRA_3x_SOC
void __init tegra30_init_early(void)
{
+ tegra_init_fuse();
tegra30_init_clocks();
tegra_init_cache(0x441, 0x551);
}
diff --git a/arch/arm/mach-tegra/fuse.c b/arch/arm/mach-tegra/fuse.c
index adfa429..3298880 100644
--- a/arch/arm/mach-tegra/fuse.c
+++ b/arch/arm/mach-tegra/fuse.c
@@ -34,6 +34,7 @@
int tegra_sku_id;
int tegra_cpu_process_id;
int tegra_core_process_id;
+int tegra_chip_id;
enum tegra_revision tegra_revision;
/* The BCT to use at boot is specified by board straps that can be read
@@ -66,12 +67,9 @@ static inline bool get_spare_fuse(int bit)
return tegra_fuse_readl(FUSE_SPARE_BIT + bit * 4);
}
-static enum tegra_revision tegra_get_revision(void)
+static enum tegra_revision tegra_get_revision(u32 id)
{
- void __iomem *chip_id = IO_ADDRESS(TEGRA_APB_MISC_BASE) + 0x804;
- u32 id = readl(chip_id);
u32 minor_rev = (id >> 16) & 0xf;
- u32 chipid = (id >> 8) & 0xff;
switch (minor_rev) {
case 1:
@@ -79,7 +77,8 @@ static enum tegra_revision tegra_get_revision(void)
case 2:
return TEGRA_REVISION_A02;
case 3:
- if (chipid == 0x20 && (get_spare_fuse(18) || get_spare_fuse(19)))
+ if (tegra_chip_id == TEGRA20 &&
+ (get_spare_fuse(18) || get_spare_fuse(19)))
return TEGRA_REVISION_A03p;
else
return TEGRA_REVISION_A03;
@@ -92,6 +91,8 @@ static enum tegra_revision tegra_get_revision(void)
void tegra_init_fuse(void)
{
+ u32 id;
+
u32 reg = readl(IO_TO_VIRT(TEGRA_CLK_RESET_BASE + 0x48));
reg |= 1 << 28;
writel(reg, IO_TO_VIRT(TEGRA_CLK_RESET_BASE + 0x48));
@@ -108,10 +109,13 @@ void tegra_init_fuse(void)
reg = tegra_apb_readl(TEGRA_APB_MISC_BASE + STRAP_OPT);
tegra_bct_strapping = (reg & RAM_ID_MASK) >> RAM_CODE_SHIFT;
- tegra_revision = tegra_get_revision();
+ id = readl_relaxed(IO_ADDRESS(TEGRA_APB_MISC_BASE) + 0x804);
+ tegra_chip_id = (id >> 8) & 0xff;
+
+ tegra_revision = tegra_get_revision(id);
pr_info("Tegra Revision: %s SKU: %d CPU Process: %d Core Process: %d\n",
- tegra_revision_name[tegra_get_revision()],
+ tegra_revision_name[tegra_revision],
tegra_sku_id, tegra_cpu_process_id,
tegra_core_process_id);
}
diff --git a/arch/arm/mach-tegra/fuse.h b/arch/arm/mach-tegra/fuse.h
index d65d2ab..d2107b2 100644
--- a/arch/arm/mach-tegra/fuse.h
+++ b/arch/arm/mach-tegra/fuse.h
@@ -35,9 +35,13 @@ enum tegra_revision {
#define SKU_ID_AP25E 27
#define SKU_ID_T25E 28
+#define TEGRA20 0x20
+#define TEGRA30 0x30
+
extern int tegra_sku_id;
extern int tegra_cpu_process_id;
extern int tegra_core_process_id;
+extern int tegra_chip_id;
extern enum tegra_revision tegra_revision;
extern int tegra_bct_strapping;
--
1.7.7.rc0.72.g4b5ea.dirty
^ permalink raw reply related [flat|nested] 20+ messages in thread* Re: [PATCH v2 1/8] ARM: tegra: export the chipid
2012-01-31 16:40 ` [PATCH v2 1/8] ARM: tegra: export the chipid Peter De Schrijver
@ 2012-02-01 7:26 ` Olof Johansson
0 siblings, 0 replies; 20+ messages in thread
From: Olof Johansson @ 2012-02-01 7:26 UTC (permalink / raw)
To: Peter De Schrijver
Cc: Colin Cross, Stephen Warren, Russell King, Gary King,
Arnd Bergmann, linux-tegra, linux-arm-kernel, linux-kernel
On Tue, Jan 31, 2012 at 06:40:39PM +0200, Peter De Schrijver wrote:
> Export a variable containing the Tegra chipid. This will be used by the SMP
> code to distinguish between Tegra variants. Also initialize the Tegra chipid
> on Tegra30.
>
> Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Ideally this patch should be split up in a couple of separate ones, first
cleanup, then the new functionality. But it's not a big deal, and I'll apply it
as it is now. Just something to keep in mind for the next time around.
-Olof
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v2 2/8] ARM: tegra: functions to access the flowcontroller
2012-01-31 16:40 [PATCH v2 0/8] Add tegra30 support for secondary cores Peter De Schrijver
2012-01-31 16:40 ` [PATCH v2 1/8] ARM: tegra: export the chipid Peter De Schrijver
@ 2012-01-31 16:40 ` Peter De Schrijver
2012-02-01 7:26 ` Olof Johansson
2012-01-31 16:40 ` [PATCH v2 3/8] ARM: tegra: rework Tegra secondary CPU core bringup Peter De Schrijver
` (6 subsequent siblings)
8 siblings, 1 reply; 20+ messages in thread
From: Peter De Schrijver @ 2012-01-31 16:40 UTC (permalink / raw)
To: Peter De Schrijver
Cc: Colin Cross, Olof Johansson, Stephen Warren, Russell King,
Gary King, Arnd Bergmann, linux-tegra, linux-arm-kernel,
linux-kernel
Introduce some functions to write to the flowcontroller registers.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
---
arch/arm/mach-tegra/Makefile | 1 +
arch/arm/mach-tegra/flowctrl.c | 62 ++++++++++++++++++++++++++++++++++++++++
arch/arm/mach-tegra/flowctrl.h | 5 +++
3 files changed, 68 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/mach-tegra/flowctrl.c
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index b78bda8..60c286e 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -6,6 +6,7 @@ obj-y += irq.o
obj-y += clock.o
obj-y += timer.o
obj-y += fuse.o
+obj-y += flowctrl.o
obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += powergate.o
obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra2_clocks.o
obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra2_emc.o
diff --git a/arch/arm/mach-tegra/flowctrl.c b/arch/arm/mach-tegra/flowctrl.c
new file mode 100644
index 0000000..fef66a7
--- /dev/null
+++ b/arch/arm/mach-tegra/flowctrl.c
@@ -0,0 +1,62 @@
+/*
+ * arch/arm/mach-tegra/flowctrl.c
+ *
+ * functions and macros to control the flowcontroller
+ *
+ * Copyright (c) 2010-2012, NVIDIA Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/io.h>
+
+#include <mach/iomap.h>
+
+#include "flowctrl.h"
+
+u8 flowctrl_offset_halt_cpu[] = {
+ FLOW_CTRL_HALT_CPU0_EVENTS,
+ FLOW_CTRL_HALT_CPU1_EVENTS,
+ FLOW_CTRL_HALT_CPU1_EVENTS + 8,
+ FLOW_CTRL_HALT_CPU1_EVENTS + 16,
+};
+
+u8 flowctrl_offset_cpu_csr[] = {
+ FLOW_CTRL_CPU0_CSR,
+ FLOW_CTRL_CPU1_CSR,
+ FLOW_CTRL_CPU1_CSR + 8,
+ FLOW_CTRL_CPU1_CSR + 16,
+};
+
+static void flowctrl_update(u8 offset, u32 value)
+{
+ void __iomem *addr = IO_ADDRESS(TEGRA_FLOW_CTRL_BASE) + offset;
+
+ writel(value, addr);
+
+ /* ensure the update has reached the flow controller */
+ wmb();
+ readl_relaxed(addr);
+}
+
+void flowctrl_write_cpu_csr(unsigned int cpuid, u32 value)
+{
+ return flowctrl_update(flowctrl_offset_halt_cpu[cpuid], value);
+}
+
+void flowctrl_write_cpu_halt(unsigned int cpuid, u32 value)
+{
+ return flowctrl_update(flowctrl_offset_cpu_csr[cpuid], value);
+}
diff --git a/arch/arm/mach-tegra/flowctrl.h b/arch/arm/mach-tegra/flowctrl.h
index 74c6efb..1942817 100644
--- a/arch/arm/mach-tegra/flowctrl.h
+++ b/arch/arm/mach-tegra/flowctrl.h
@@ -34,4 +34,9 @@
#define FLOW_CTRL_HALT_CPU1_EVENTS 0x14
#define FLOW_CTRL_CPU1_CSR 0x18
+#ifndef __ASSEMBLY__
+void flowctrl_write_cpu_csr(unsigned int cpuid, u32 value);
+void flowctrl_write_cpu_halt(unsigned int cpuid, u32 value);
+#endif
+
#endif
--
1.7.7.rc0.72.g4b5ea.dirty
^ permalink raw reply related [flat|nested] 20+ messages in thread* Re: [PATCH v2 2/8] ARM: tegra: functions to access the flowcontroller
2012-01-31 16:40 ` [PATCH v2 2/8] ARM: tegra: functions to access the flowcontroller Peter De Schrijver
@ 2012-02-01 7:26 ` Olof Johansson
0 siblings, 0 replies; 20+ messages in thread
From: Olof Johansson @ 2012-02-01 7:26 UTC (permalink / raw)
To: Peter De Schrijver
Cc: Colin Cross, Stephen Warren, Russell King, Gary King,
Arnd Bergmann, linux-tegra, linux-arm-kernel, linux-kernel
On Tue, Jan 31, 2012 at 06:40:40PM +0200, Peter De Schrijver wrote:
> Introduce some functions to write to the flowcontroller registers.
>
> Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
> ---
> arch/arm/mach-tegra/Makefile | 1 +
> arch/arm/mach-tegra/flowctrl.c | 62 ++++++++++++++++++++++++++++++++++++++++
> arch/arm/mach-tegra/flowctrl.h | 5 +++
> 3 files changed, 68 insertions(+), 0 deletions(-)
> create mode 100644 arch/arm/mach-tegra/flowctrl.c
>
> diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
> index b78bda8..60c286e 100644
> --- a/arch/arm/mach-tegra/Makefile
> +++ b/arch/arm/mach-tegra/Makefile
> @@ -6,6 +6,7 @@ obj-y += irq.o
> obj-y += clock.o
> obj-y += timer.o
> obj-y += fuse.o
> +obj-y += flowctrl.o
> obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += powergate.o
> obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra2_clocks.o
> obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra2_emc.o
> diff --git a/arch/arm/mach-tegra/flowctrl.c b/arch/arm/mach-tegra/flowctrl.c
> new file mode 100644
> index 0000000..fef66a7
> --- /dev/null
> +++ b/arch/arm/mach-tegra/flowctrl.c
> @@ -0,0 +1,62 @@
> +/*
> + * arch/arm/mach-tegra/flowctrl.c
> + *
> + * functions and macros to control the flowcontroller
Nit:
It would be more useful here to get one or two sentences about what the flow
controller unit is used for, etc.
-Olof
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v2 3/8] ARM: tegra: rework Tegra secondary CPU core bringup
2012-01-31 16:40 [PATCH v2 0/8] Add tegra30 support for secondary cores Peter De Schrijver
2012-01-31 16:40 ` [PATCH v2 1/8] ARM: tegra: export the chipid Peter De Schrijver
2012-01-31 16:40 ` [PATCH v2 2/8] ARM: tegra: functions to access the flowcontroller Peter De Schrijver
@ 2012-01-31 16:40 ` Peter De Schrijver
2012-01-31 22:50 ` Russell King - ARM Linux
2012-02-01 7:54 ` Olof Johansson
2012-01-31 16:40 ` [PATCH v2 4/8] ARM: tegra: prepare powergate.c for multiple variants Peter De Schrijver
` (5 subsequent siblings)
8 siblings, 2 replies; 20+ messages in thread
From: Peter De Schrijver @ 2012-01-31 16:40 UTC (permalink / raw)
To: Peter De Schrijver
Cc: Colin Cross, Olof Johansson, Stephen Warren, Russell King,
Gary King, Arnd Bergmann, linux-tegra, linux-arm-kernel,
linux-kernel
Prepare the Tegra secondary CPU core bringup code for other Tegra variants.
The reset handler is also generalized to allow for future introduction of
powersaving modes which turn off the CPU cores.
Based on work by:
Scott Williams <scwilliams@nvidia.com>
Chris Johnson <cwj@nvidia.com>
Colin Cross <ccross@android.com>
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
---
arch/arm/mach-tegra/Makefile | 1 +
arch/arm/mach-tegra/headsmp.S | 160 ++++++++++++++++++++++++++++--
arch/arm/mach-tegra/include/mach/iomap.h | 3 +
arch/arm/mach-tegra/platsmp.c | 97 ++++++++++---------
arch/arm/mach-tegra/reset.c | 84 ++++++++++++++++
arch/arm/mach-tegra/reset.h | 50 +++++++++
6 files changed, 342 insertions(+), 53 deletions(-)
create mode 100644 arch/arm/mach-tegra/reset.c
create mode 100644 arch/arm/mach-tegra/reset.h
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index 60c286e..a954654 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -13,6 +13,7 @@ obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra2_emc.o
obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += board-dt-tegra30.o
obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30_clocks.o
obj-$(CONFIG_SMP) += platsmp.o localtimer.o headsmp.o
+obj-$(CONFIG_SMP) += reset.o
obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
obj-$(CONFIG_TEGRA_SYSTEM_DMA) += dma.o apbio.o
obj-$(CONFIG_CPU_FREQ) += cpu-tegra.o
diff --git a/arch/arm/mach-tegra/headsmp.S b/arch/arm/mach-tegra/headsmp.S
index b5349b2..bb13e22 100644
--- a/arch/arm/mach-tegra/headsmp.S
+++ b/arch/arm/mach-tegra/headsmp.S
@@ -1,6 +1,31 @@
#include <linux/linkage.h>
#include <linux/init.h>
+#include <asm/cache.h>
+
+#include <mach/iomap.h>
+
+#include "flowctrl.h"
+#include "reset.h"
+
+#define DEBUG_CPU_RESET_HANDLER 0
+
+#define APB_MISC_GP_HIDREV 0x804
+#define PMC_SCRATCH41 0x140
+
+
+#define RESET_DATA(x) ((TEGRA_RESET_##x)*4)
+
+ .macro mov32, reg, val
+ movw \reg, #:lower16:\val
+ movt \reg, #:upper16:\val
+ .endm
+
+ .macro enable_coresight, reg
+ mov32 \reg, 0xC5ACCE55
+ mcr p14, 0, \reg, c7, c12, 6
+ .endm
+
.section ".text.head", "ax"
__CPUINIT
@@ -47,15 +72,134 @@ ENTRY(v7_invalidate_l1)
mov pc, lr
ENDPROC(v7_invalidate_l1)
+
ENTRY(tegra_secondary_startup)
- msr cpsr_fsxc, #0xd3
bl v7_invalidate_l1
- mrc p15, 0, r0, c0, c0, 5
- and r0, r0, #15
- ldr r1, =0x6000f100
- str r0, [r1]
-1: ldr r2, [r1]
- cmp r0, r2
- beq 1b
+ enable_coresight r0
b secondary_startup
ENDPROC(tegra_secondary_startup)
+
+ .align L1_CACHE_SHIFT
+ENTRY(__tegra_cpu_reset_handler_start)
+
+/*
+ * __tegra_cpu_reset_handler:
+ *
+ * Common handler for all CPU reset events.
+ *
+ * Register usage within the reset handler:
+ *
+ * R7 = CPU present (to the OS) mask
+ * R8 = CPU in LP1 state mask
+ * R9 = CPU in LP2 state mask
+ * R10 = CPU number
+ * R11 = CPU mask
+ * R12 = pointer to reset handler data
+ *
+ * NOTE: This code is copied to IRAM. All code and data accesses
+ * must be position-independent.
+ */
+
+ .align L1_CACHE_SHIFT
+ENTRY(__tegra_cpu_reset_handler)
+
+#if DEBUG_CPU_RESET_HANDLER
+ enable_coresight r0
+ b .
+#endif
+ cpsid aif, 0x13 @ SVC mode, interrupts disabled
+ mrc p15, 0, r0, c0, c0, 0 @ read main ID register
+ and r5, r0, #0x00f00000 @ variant
+ and r6, r0, #0x0000000f @ revision
+ orr r6, r6, r5, lsr #20-4 @ combine variant and revision
+#ifdef CONFIG_ARM_ERRATA_743622
+ teq r6, #0x20 @ present in r2p0
+ teqne r6, #0x21 @ present in r2p1
+ teqne r6, #0x22 @ present in r2p2
+ teqne r6, #0x27 @ present in r2p7
+ teqne r6, #0x29 @ present in r2p9
+ mrceq p15, 0, r10, c15, c0, 1 @ read diagnostic register
+ orreq r10, r10, #1 << 6 @ set bit #6
+ mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register
+#endif
+ mrc p15, 0, r10, c0, c0, 5 @ MPIDR
+ and r10, r10, #0x3 @ R10 = CPU number
+ mov r11, #1
+ mov r11, r11, lsl r10 @ R11 = CPU mask
+ adr r12, __tegra_cpu_reset_handler_data
+
+#ifdef CONFIG_SMP
+ /* Does the OS know about this CPU? */
+ ldr r7, [r12, #RESET_DATA(MASK_PRESENT)]
+ tst r7, r11 @ if !present
+ bleq __die @ CPU not present (to OS)
+#endif
+
+#ifdef CONFIG_ARCH_TEGRA_2x_SOC
+ /* Are we on Tegra20? */
+ mov32 r6, TEGRA_APB_MISC_BASE
+ ldr r0, [r6, #APB_MISC_GP_HIDREV]
+ and r0, r0, #0xff00
+ cmp r0, #(0x20 << 8)
+ bne 1f
+ /* If not CPU0, don't let CPU0 reset CPU1 now that CPU1 is coming up. */
+ mov32 r6, TEGRA_PMC_BASE
+ mov r0, #0
+ cmp r10, #0
+ strne r0, [r6, #PMC_SCRATCH41]
+1:
+#endif
+
+#ifdef CONFIG_SMP
+ /*
+ * Can only be secondary boot (initial or hotplug) but CPU 0
+ * cannot be here.
+ */
+ cmp r10, #0
+ bleq __die @ CPU0 cannot be here
+ ldr lr, [r12, #RESET_DATA(STARTUP_SECONDARY)]
+ cmp lr, #0
+ bleq __die @ no secondary startup handler
+ bx lr
+#endif
+
+/*
+ * We don't know why the CPU reset. Just kill it.
+ * The LR register will contain the address we died at + 4.
+ */
+
+__die:
+ sub lr, lr, #4
+ mov32 r7, TEGRA_PMC_BASE
+ str lr, [r7, #PMC_SCRATCH41]
+
+ mov32 r7, TEGRA_CLK_RESET_BASE
+
+ /* Are we on Tegra20? */
+ mov32 r6, TEGRA_APB_MISC_BASE
+ ldr r0, [r6, #APB_MISC_GP_HIDREV]
+ and r0, r0, #0xff00
+ cmp r0, #(0x20 << 8)
+ bne 1f
+
+#ifdef CONFIG_ARCH_TEGRA_2x_SOC
+ mov32 r0, 0x1111
+ mov r1, r0, lsl r10
+ str r1, [r7, #0x340] @ CLK_RST_CPU_CMPLX_SET
+#endif
+1:
+ /* If the CPU still isn't dead, just spin here. */
+ b .
+ENDPROC(__tegra_cpu_reset_handler)
+
+ .align L1_CACHE_SHIFT
+ .type __tegra_cpu_reset_handler_data, %object
+ .globl __tegra_cpu_reset_handler_data
+__tegra_cpu_reset_handler_data:
+ .rept TEGRA_RESET_DATA_SIZE
+ .long 0
+ .endr
+ .size __tegra_cpu_reset_handler_data, .-tegra_cpu_reset_handler_data
+ .align L1_CACHE_SHIFT
+
+ENTRY(__tegra_cpu_reset_handler_end)
diff --git a/arch/arm/mach-tegra/include/mach/iomap.h b/arch/arm/mach-tegra/include/mach/iomap.h
index 67644c9..cff672a 100644
--- a/arch/arm/mach-tegra/include/mach/iomap.h
+++ b/arch/arm/mach-tegra/include/mach/iomap.h
@@ -113,6 +113,9 @@
#define TEGRA_AHB_GIZMO_BASE 0x6000C004
#define TEGRA_AHB_GIZMO_SIZE 0x10C
+#define TEGRA_SB_BASE 0x6000C200
+#define TEGRA_SB_SIZE 256
+
#define TEGRA_STATMON_BASE 0x6000C400
#define TEGRA_STATMON_SIZE SZ_1K
diff --git a/arch/arm/mach-tegra/platsmp.c b/arch/arm/mach-tegra/platsmp.c
index 7d2b5d0..79a241a 100644
--- a/arch/arm/mach-tegra/platsmp.c
+++ b/arch/arm/mach-tegra/platsmp.c
@@ -26,18 +26,26 @@
#include <mach/iomap.h>
+#include "fuse.h"
+#include "flowctrl.h"
+#include "reset.h"
+
extern void tegra_secondary_startup(void);
-static DEFINE_SPINLOCK(boot_lock);
static void __iomem *scu_base = IO_ADDRESS(TEGRA_ARM_PERIF_BASE);
#define EVP_CPU_RESET_VECTOR \
(IO_ADDRESS(TEGRA_EXCEPTION_VECTORS_BASE) + 0x100)
#define CLK_RST_CONTROLLER_CLK_CPU_CMPLX \
(IO_ADDRESS(TEGRA_CLK_RESET_BASE) + 0x4c)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET \
+ (IO_ADDRESS(TEGRA_CLK_RESET_BASE) + 0x340)
#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR \
(IO_ADDRESS(TEGRA_CLK_RESET_BASE) + 0x344)
+#define CPU_CLOCK(cpu) (0x1<<(8+cpu))
+#define CPU_RESET(cpu) (0x1111ul<<(cpu))
+
void __cpuinit platform_secondary_init(unsigned int cpu)
{
/*
@@ -47,63 +55,62 @@ void __cpuinit platform_secondary_init(unsigned int cpu)
*/
gic_secondary_init(0);
- /*
- * Synchronise with the boot thread.
- */
- spin_lock(&boot_lock);
- spin_unlock(&boot_lock);
}
-int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
+static int tegra20_power_up_cpu(unsigned int cpu)
{
- unsigned long old_boot_vector;
- unsigned long boot_vector;
- unsigned long timeout;
u32 reg;
- /*
- * set synchronisation state between this boot processor
- * and the secondary one
- */
- spin_lock(&boot_lock);
-
-
- /* set the reset vector to point to the secondary_startup routine */
-
- boot_vector = virt_to_phys(tegra_secondary_startup);
- old_boot_vector = readl(EVP_CPU_RESET_VECTOR);
- writel(boot_vector, EVP_CPU_RESET_VECTOR);
-
- /* enable cpu clock on cpu1 */
+ /* Enable the CPU clock. */
+ reg = readl(CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
+ writel(reg & ~CPU_CLOCK(cpu), CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
+ barrier();
reg = readl(CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
- writel(reg & ~(1<<9), CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
-
- reg = (1<<13) | (1<<9) | (1<<5) | (1<<1);
- writel(reg, CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR);
- smp_wmb();
- flush_cache_all();
+ /* Clear flow controller CSR. */
+ flowctrl_write_cpu_csr(cpu, 0);
- /* unhalt the cpu */
- writel(0, IO_ADDRESS(TEGRA_FLOW_CTRL_BASE) + 0x14);
+ return 0;
+}
- timeout = jiffies + (1 * HZ);
- while (time_before(jiffies, timeout)) {
- if (readl(EVP_CPU_RESET_VECTOR) != boot_vector)
- break;
- udelay(10);
- }
+int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
+{
+ int status;
- /* put the old boot vector back */
- writel(old_boot_vector, EVP_CPU_RESET_VECTOR);
+ /* Force the CPU into reset. The CPU must remain in reset when the
+ * flow controller state is cleared (which will cause the flow
+ * controller to stop driving reset if the CPU has been power-gated
+ * via the flow controller). This will have no effect on first boot
+ * of the CPU since it should already be in reset.
+ */
+ writel(CPU_RESET(cpu), CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET);
+ dmb();
/*
- * now the secondary core is starting up let it run its
- * calibrations, then wait for it to finish
+ * Unhalt the CPU. If the flow controller was used to power-gate the
+ * CPU this will cause the flow controller to stop driving reset.
+ * The CPU will remain in reset because the clock and reset block
+ * is now driving reset.
*/
- spin_unlock(&boot_lock);
+ flowctrl_write_cpu_halt(cpu, 0);
+
+ switch (tegra_chip_id) {
+ case TEGRA20:
+ status = tegra20_power_up_cpu(cpu);
+ break;
+ default:
+ status = -EINVAL;
+ break;
+ }
- return 0;
+ if (status)
+ goto done;
+
+ /* Take the CPU out of reset. */
+ writel(CPU_RESET(cpu), CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR);
+ wmb();
+done:
+ return status;
}
/*
@@ -128,6 +135,6 @@ void __init smp_init_cpus(void)
void __init platform_smp_prepare_cpus(unsigned int max_cpus)
{
-
+ tegra_cpu_reset_handler_init();
scu_enable(scu_base);
}
diff --git a/arch/arm/mach-tegra/reset.c b/arch/arm/mach-tegra/reset.c
new file mode 100644
index 0000000..4d6a2ee
--- /dev/null
+++ b/arch/arm/mach-tegra/reset.c
@@ -0,0 +1,84 @@
+/*
+ * arch/arm/mach-tegra/reset.c
+ *
+ * Copyright (C) 2011,2012 NVIDIA Corporation.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/cpumask.h>
+#include <linux/bitops.h>
+
+#include <asm/cacheflush.h>
+#include <asm/hardware/cache-l2x0.h>
+
+#include <mach/iomap.h>
+#include <mach/irammap.h>
+
+#include "reset.h"
+#include "fuse.h"
+
+#define TEGRA_IRAM_RESET_BASE (TEGRA_IRAM_BASE + \
+ TEGRA_IRAM_RESET_HANDLER_OFFSET)
+
+static bool is_enabled;
+
+static void tegra_cpu_reset_handler_enable(void)
+{
+ void __iomem *iram_base = IO_ADDRESS(TEGRA_IRAM_RESET_BASE);
+ void __iomem *evp_cpu_reset =
+ IO_ADDRESS(TEGRA_EXCEPTION_VECTORS_BASE + 0x100);
+ void __iomem *sb_ctrl = IO_ADDRESS(TEGRA_SB_BASE);
+ u32 reg;
+
+ BUG_ON(is_enabled);
+ BUG_ON(tegra_cpu_reset_handler_size > TEGRA_IRAM_RESET_HANDLER_SIZE);
+
+ memcpy(iram_base, (void *)__tegra_cpu_reset_handler_start,
+ tegra_cpu_reset_handler_size);
+
+ /*
+ * NOTE: This must be the one and only write to the EVP CPU reset
+ * vector in the entire system.
+ */
+ writel(TEGRA_IRAM_RESET_BASE + tegra_cpu_reset_handler_offset,
+ evp_cpu_reset);
+ wmb();
+ reg = readl(evp_cpu_reset);
+
+ /*
+ * Prevent further modifications to the physical reset vector.
+ * NOTE: Has no effect on chips prior to Tegra30.
+ */
+ if (tegra_chip_id != TEGRA20) {
+ reg = readl(sb_ctrl);
+ reg |= 2;
+ writel(reg, sb_ctrl);
+ wmb();
+ }
+
+ is_enabled = true;
+}
+
+void __init tegra_cpu_reset_handler_init(void)
+{
+
+#ifdef CONFIG_SMP
+ __tegra_cpu_reset_handler_data[TEGRA_RESET_MASK_PRESENT] =
+ *((u32 *)cpu_present_mask);
+ __tegra_cpu_reset_handler_data[TEGRA_RESET_STARTUP_SECONDARY] =
+ virt_to_phys((void *)tegra_secondary_startup);
+#endif
+
+ tegra_cpu_reset_handler_enable();
+}
diff --git a/arch/arm/mach-tegra/reset.h b/arch/arm/mach-tegra/reset.h
new file mode 100644
index 0000000..de88bf8
--- /dev/null
+++ b/arch/arm/mach-tegra/reset.h
@@ -0,0 +1,50 @@
+/*
+ * arch/arm/mach-tegra/reset.h
+ *
+ * CPU reset dispatcher.
+ *
+ * Copyright (c) 2011, NVIDIA Corporation.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __MACH_TEGRA_RESET_H
+#define __MACH_TEGRA_RESET_H
+
+#define TEGRA_RESET_MASK_PRESENT 0
+#define TEGRA_RESET_MASK_LP1 1
+#define TEGRA_RESET_MASK_LP2 2
+#define TEGRA_RESET_STARTUP_SECONDARY 3
+#define TEGRA_RESET_STARTUP_LP2 4
+#define TEGRA_RESET_STARTUP_LP1 5
+#define TEGRA_RESET_DATA_SIZE 6
+
+#ifndef __ASSEMBLY__
+
+extern unsigned long __tegra_cpu_reset_handler_data[TEGRA_RESET_DATA_SIZE];
+
+void __tegra_cpu_reset_handler_start(void);
+void __tegra_cpu_reset_handler(void);
+void __tegra_cpu_reset_handler_end(void);
+void tegra_secondary_startup(void);
+
+#define tegra_cpu_reset_handler_offset \
+ ((u32)__tegra_cpu_reset_handler - \
+ (u32)__tegra_cpu_reset_handler_start)
+
+#define tegra_cpu_reset_handler_size \
+ (__tegra_cpu_reset_handler_end - \
+ __tegra_cpu_reset_handler_start)
+
+void __init tegra_cpu_reset_handler_init(void);
+
+#endif
+#endif
--
1.7.7.rc0.72.g4b5ea.dirty
^ permalink raw reply related [flat|nested] 20+ messages in thread* Re: [PATCH v2 3/8] ARM: tegra: rework Tegra secondary CPU core bringup
2012-01-31 16:40 ` [PATCH v2 3/8] ARM: tegra: rework Tegra secondary CPU core bringup Peter De Schrijver
@ 2012-01-31 22:50 ` Russell King - ARM Linux
2012-02-01 11:08 ` Will Deacon
2012-02-01 7:54 ` Olof Johansson
1 sibling, 1 reply; 20+ messages in thread
From: Russell King - ARM Linux @ 2012-01-31 22:50 UTC (permalink / raw)
To: Peter De Schrijver
Cc: Colin Cross, Olof Johansson, Stephen Warren, Gary King,
Arnd Bergmann, linux-tegra, linux-arm-kernel, linux-kernel
On Tue, Jan 31, 2012 at 06:40:41PM +0200, Peter De Schrijver wrote:
> +ENTRY(__tegra_cpu_reset_handler_start)
> +
> +/*
> + * __tegra_cpu_reset_handler:
> + *
> + * Common handler for all CPU reset events.
> + *
> + * Register usage within the reset handler:
> + *
> + * R7 = CPU present (to the OS) mask
> + * R8 = CPU in LP1 state mask
> + * R9 = CPU in LP2 state mask
> + * R10 = CPU number
> + * R11 = CPU mask
> + * R12 = pointer to reset handler data
> + *
> + * NOTE: This code is copied to IRAM. All code and data accesses
> + * must be position-independent.
> + */
> +
> + .align L1_CACHE_SHIFT
> +ENTRY(__tegra_cpu_reset_handler)
> +
> +#if DEBUG_CPU_RESET_HANDLER
> + enable_coresight r0
> + b .
> +#endif
> + cpsid aif, 0x13 @ SVC mode, interrupts disabled
> + mrc p15, 0, r0, c0, c0, 0 @ read main ID register
> + and r5, r0, #0x00f00000 @ variant
> + and r6, r0, #0x0000000f @ revision
> + orr r6, r6, r5, lsr #20-4 @ combine variant and revision
> +#ifdef CONFIG_ARM_ERRATA_743622
> + teq r6, #0x20 @ present in r2p0
> + teqne r6, #0x21 @ present in r2p1
> + teqne r6, #0x22 @ present in r2p2
> + teqne r6, #0x27 @ present in r2p7
> + teqne r6, #0x29 @ present in r2p9
Okay, so we have this errata in proc-v7.S, but only for p0..p2. If
it's also p7 and p9, then it shows that the errata in the kernel aren't
being actively maintained, and brings into question their worth.
Plus, of course, we don't want platforms re-implementing the errata
in their own code if we're already implementing it somewhere in the
kernel. So, that's something which needs to be thought about.
That's something that needs considering along side the whole 'what
to do about errata when running in non-secure mode' problem which
OMAP suffers from.
> + mrceq p15, 0, r10, c15, c0, 1 @ read diagnostic register
> + orreq r10, r10, #1 << 6 @ set bit #6
> + mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register
> +#endif
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v2 3/8] ARM: tegra: rework Tegra secondary CPU core bringup
2012-01-31 22:50 ` Russell King - ARM Linux
@ 2012-02-01 11:08 ` Will Deacon
0 siblings, 0 replies; 20+ messages in thread
From: Will Deacon @ 2012-02-01 11:08 UTC (permalink / raw)
To: Russell King - ARM Linux
Cc: Peter De Schrijver, Stephen Warren, Gary King, Arnd Bergmann,
linux-kernel, linux-tegra, Colin Cross, Olof Johansson,
linux-arm-kernel
On Tue, Jan 31, 2012 at 10:50:45PM +0000, Russell King - ARM Linux wrote:
> On Tue, Jan 31, 2012 at 06:40:41PM +0200, Peter De Schrijver wrote:
> > +#ifdef CONFIG_ARM_ERRATA_743622
> > + teq r6, #0x20 @ present in r2p0
> > + teqne r6, #0x21 @ present in r2p1
> > + teqne r6, #0x22 @ present in r2p2
> > + teqne r6, #0x27 @ present in r2p7
> > + teqne r6, #0x29 @ present in r2p9
>
> Okay, so we have this errata in proc-v7.S, but only for p0..p2. If
> it's also p7 and p9, then it shows that the errata in the kernel aren't
> being actively maintained, and brings into question their worth.
It looks like the errata document has been updated since I wrote the
workaround in proc-v7.S (and new r2p* versions of the A9 have been
released). The new document states that r2p* are affected, so we should
update the workaround.
> Plus, of course, we don't want platforms re-implementing the errata
> in their own code if we're already implementing it somewhere in the
> kernel. So, that's something which needs to be thought about.
Indeed, that could become extremely confusing, especially when they start
doing different things.
> That's something that needs considering along side the whole 'what
> to do about errata when running in non-secure mode' problem which
> OMAP suffers from.
My view is that the workarounds in the kernel are a good way to highlight
which errata we consider to be important from Linux's point-of-view and also
how to avoid them in practice. It's not always possible to apply them in the
kernel at runtime (due to security constraints) but I think it's important
to show what Linux expects.
I'll go back through the errata document and check if any others have been
updated besides this one.
Will
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v2 3/8] ARM: tegra: rework Tegra secondary CPU core bringup
2012-01-31 16:40 ` [PATCH v2 3/8] ARM: tegra: rework Tegra secondary CPU core bringup Peter De Schrijver
2012-01-31 22:50 ` Russell King - ARM Linux
@ 2012-02-01 7:54 ` Olof Johansson
2012-02-01 10:01 ` Peter De Schrijver
1 sibling, 1 reply; 20+ messages in thread
From: Olof Johansson @ 2012-02-01 7:54 UTC (permalink / raw)
To: Peter De Schrijver
Cc: Colin Cross, Stephen Warren, Russell King, Gary King,
Arnd Bergmann, linux-tegra, linux-arm-kernel, linux-kernel
On Tue, Jan 31, 2012 at 06:40:41PM +0200, Peter De Schrijver wrote:
> + .align L1_CACHE_SHIFT
> + .type __tegra_cpu_reset_handler_data, %object
> + .globl __tegra_cpu_reset_handler_data
> +__tegra_cpu_reset_handler_data:
> + .rept TEGRA_RESET_DATA_SIZE
> + .long 0
> + .endr
> + .size __tegra_cpu_reset_handler_data, .-tegra_cpu_reset_handler_data
> + .align L1_CACHE_SHIFT
> +
This doesn't build:
/tmp/ccPd4Pcj.s: Assembler messages:
/tmp/ccPd4Pcj.s: Error: .size expression for __tegra_cpu_reset_handler_data does not evaluate to a constant
Did you mean .-__tegra_cpu_reset_handler_data there?
-Olof
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v2 3/8] ARM: tegra: rework Tegra secondary CPU core bringup
2012-02-01 7:54 ` Olof Johansson
@ 2012-02-01 10:01 ` Peter De Schrijver
0 siblings, 0 replies; 20+ messages in thread
From: Peter De Schrijver @ 2012-02-01 10:01 UTC (permalink / raw)
To: Olof Johansson
Cc: Colin Cross, Stephen Warren, Russell King, Gary King,
Arnd Bergmann, linux-tegra, linux-arm-kernel, linux-kernel
On Wed, Feb 01, 2012 at 08:54:48AM +0100, Olof Johansson wrote:
> On Tue, Jan 31, 2012 at 06:40:41PM +0200, Peter De Schrijver wrote:
>
> > + .align L1_CACHE_SHIFT
> > + .type __tegra_cpu_reset_handler_data, %object
> > + .globl __tegra_cpu_reset_handler_data
> > +__tegra_cpu_reset_handler_data:
> > + .rept TEGRA_RESET_DATA_SIZE
> > + .long 0
> > + .endr
> > + .size __tegra_cpu_reset_handler_data, .-tegra_cpu_reset_handler_data
> > + .align L1_CACHE_SHIFT
> > +
>
> This doesn't build:
>
> /tmp/ccPd4Pcj.s: Assembler messages:
> /tmp/ccPd4Pcj.s: Error: .size expression for __tegra_cpu_reset_handler_data does not evaluate to a constant
>
> Did you mean .-__tegra_cpu_reset_handler_data there?
Yes. It's not used anywhere though :) So I will leave it out in the next version.
Cheers,
Peter.
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v2 4/8] ARM: tegra: prepare powergate.c for multiple variants
2012-01-31 16:40 [PATCH v2 0/8] Add tegra30 support for secondary cores Peter De Schrijver
` (2 preceding siblings ...)
2012-01-31 16:40 ` [PATCH v2 3/8] ARM: tegra: rework Tegra secondary CPU core bringup Peter De Schrijver
@ 2012-01-31 16:40 ` Peter De Schrijver
2012-01-31 16:40 ` [PATCH v2 5/8] ARM: tegra: export tegra_powergate_is_powered() Peter De Schrijver
` (4 subsequent siblings)
8 siblings, 0 replies; 20+ messages in thread
From: Peter De Schrijver @ 2012-01-31 16:40 UTC (permalink / raw)
To: Peter De Schrijver
Cc: Colin Cross, Olof Johansson, Stephen Warren, Russell King,
Gary King, Arnd Bergmann, linux-tegra, linux-arm-kernel,
linux-kernel
Prepare the powergating code for other Tegra variants which have a different
number of powerdomains.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
---
arch/arm/mach-tegra/include/mach/powergate.h | 1 -
arch/arm/mach-tegra/powergate.c | 33 +++++++++++++++++++++----
2 files changed, 27 insertions(+), 7 deletions(-)
diff --git a/arch/arm/mach-tegra/include/mach/powergate.h b/arch/arm/mach-tegra/include/mach/powergate.h
index 39c396d..36846dc 100644
--- a/arch/arm/mach-tegra/include/mach/powergate.h
+++ b/arch/arm/mach-tegra/include/mach/powergate.h
@@ -27,7 +27,6 @@
#define TEGRA_POWERGATE_VDEC 4
#define TEGRA_POWERGATE_L2 5
#define TEGRA_POWERGATE_MPE 6
-#define TEGRA_NUM_POWERGATE 7
int tegra_powergate_power_on(int id);
int tegra_powergate_power_off(int id);
diff --git a/arch/arm/mach-tegra/powergate.c b/arch/arm/mach-tegra/powergate.c
index 9483064..9b828f2 100644
--- a/arch/arm/mach-tegra/powergate.c
+++ b/arch/arm/mach-tegra/powergate.c
@@ -31,6 +31,8 @@
#include <mach/iomap.h>
#include <mach/powergate.h>
+#include "fuse.h"
+
#define PWRGATE_TOGGLE 0x30
#define PWRGATE_TOGGLE_START (1 << 8)
@@ -38,6 +40,8 @@
#define PWRGATE_STATUS 0x38
+static int tegra_num_powerdomains;
+
static DEFINE_SPINLOCK(tegra_powergate_lock);
static void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
@@ -75,7 +79,7 @@ static int tegra_powergate_set(int id, bool new_state)
int tegra_powergate_power_on(int id)
{
- if (id < 0 || id >= TEGRA_NUM_POWERGATE)
+ if (id < 0 || id >= tegra_num_powerdomains)
return -EINVAL;
return tegra_powergate_set(id, true);
@@ -83,17 +87,18 @@ int tegra_powergate_power_on(int id)
int tegra_powergate_power_off(int id)
{
- if (id < 0 || id >= TEGRA_NUM_POWERGATE)
+ if (id < 0 || id >= tegra_num_powerdomains)
return -EINVAL;
return tegra_powergate_set(id, false);
}
-static bool tegra_powergate_is_powered(int id)
+static int tegra_powergate_is_powered(int id)
{
u32 status;
- WARN_ON(id < 0 || id >= TEGRA_NUM_POWERGATE);
+ if (id < 0 || id >= tegra_num_powerdomains)
+ return -EINVAL;
status = pmc_read(PWRGATE_STATUS) & (1 << id);
return !!status;
@@ -103,7 +108,7 @@ int tegra_powergate_remove_clamping(int id)
{
u32 mask;
- if (id < 0 || id >= TEGRA_NUM_POWERGATE)
+ if (id < 0 || id >= tegra_num_powerdomains)
return -EINVAL;
/*
@@ -156,6 +161,22 @@ err_power:
return ret;
}
+int __init tegra_powergate_init(void)
+{
+ switch (tegra_chip_id) {
+ case TEGRA20:
+ tegra_num_powerdomains = 7;
+ break;
+ default:
+ /* Unknown Tegra variant. Disable powergating */
+ tegra_num_powerdomains = 0;
+ break;
+ }
+
+ return 0;
+}
+arch_initcall(tegra_powergate_init);
+
#ifdef CONFIG_DEBUG_FS
static const char * const powergate_name[] = {
@@ -175,7 +196,7 @@ static int powergate_show(struct seq_file *s, void *data)
seq_printf(s, " powergate powered\n");
seq_printf(s, "------------------\n");
- for (i = 0; i < TEGRA_NUM_POWERGATE; i++)
+ for (i = 0; i < tegra_num_powerdomains; i++)
seq_printf(s, " %9s %7s\n", powergate_name[i],
tegra_powergate_is_powered(i) ? "yes" : "no");
return 0;
--
1.7.7.rc0.72.g4b5ea.dirty
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH v2 5/8] ARM: tegra: export tegra_powergate_is_powered()
2012-01-31 16:40 [PATCH v2 0/8] Add tegra30 support for secondary cores Peter De Schrijver
` (3 preceding siblings ...)
2012-01-31 16:40 ` [PATCH v2 4/8] ARM: tegra: prepare powergate.c for multiple variants Peter De Schrijver
@ 2012-01-31 16:40 ` Peter De Schrijver
2012-01-31 16:40 ` [PATCH v2 6/8] ARM: tegra: add support for Tegra30 powerdomains Peter De Schrijver
` (3 subsequent siblings)
8 siblings, 0 replies; 20+ messages in thread
From: Peter De Schrijver @ 2012-01-31 16:40 UTC (permalink / raw)
To: Peter De Schrijver
Cc: Colin Cross, Olof Johansson, Stephen Warren, Russell King,
Gary King, Arnd Bergmann, linux-tegra, linux-arm-kernel,
linux-kernel
Export tegra_powergate_is_powered(). This function will be used by the Tegra30
code to bringup secondary CPU cores.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
---
arch/arm/mach-tegra/include/mach/powergate.h | 1 +
arch/arm/mach-tegra/powergate.c | 2 +-
2 files changed, 2 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mach-tegra/include/mach/powergate.h b/arch/arm/mach-tegra/include/mach/powergate.h
index 36846dc..0ec8ce1 100644
--- a/arch/arm/mach-tegra/include/mach/powergate.h
+++ b/arch/arm/mach-tegra/include/mach/powergate.h
@@ -28,6 +28,7 @@
#define TEGRA_POWERGATE_L2 5
#define TEGRA_POWERGATE_MPE 6
+int tegra_powergate_is_powered(int id);
int tegra_powergate_power_on(int id);
int tegra_powergate_power_off(int id);
int tegra_powergate_remove_clamping(int id);
diff --git a/arch/arm/mach-tegra/powergate.c b/arch/arm/mach-tegra/powergate.c
index 9b828f2..984bbdf 100644
--- a/arch/arm/mach-tegra/powergate.c
+++ b/arch/arm/mach-tegra/powergate.c
@@ -93,7 +93,7 @@ int tegra_powergate_power_off(int id)
return tegra_powergate_set(id, false);
}
-static int tegra_powergate_is_powered(int id)
+int tegra_powergate_is_powered(int id)
{
u32 status;
--
1.7.7.rc0.72.g4b5ea.dirty
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH v2 6/8] ARM: tegra: add support for Tegra30 powerdomains
2012-01-31 16:40 [PATCH v2 0/8] Add tegra30 support for secondary cores Peter De Schrijver
` (4 preceding siblings ...)
2012-01-31 16:40 ` [PATCH v2 5/8] ARM: tegra: export tegra_powergate_is_powered() Peter De Schrijver
@ 2012-01-31 16:40 ` Peter De Schrijver
2012-01-31 16:40 ` [PATCH v2 7/8] ARM: tegra: support for Tegra30 CPU powerdomains Peter De Schrijver
` (2 subsequent siblings)
8 siblings, 0 replies; 20+ messages in thread
From: Peter De Schrijver @ 2012-01-31 16:40 UTC (permalink / raw)
To: Peter De Schrijver
Cc: Colin Cross, Olof Johansson, Stephen Warren, Russell King,
Gary King, Arnd Bergmann, linux-tegra, linux-arm-kernel,
linux-kernel
Add support for the new powerdomains in Tegra30 such as extra CPU cores and
the SATA domain.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
---
arch/arm/mach-tegra/include/mach/powergate.h | 10 ++++++++++
arch/arm/mach-tegra/powergate.c | 3 +++
2 files changed, 13 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-tegra/include/mach/powergate.h b/arch/arm/mach-tegra/include/mach/powergate.h
index 0ec8ce1..ca41186 100644
--- a/arch/arm/mach-tegra/include/mach/powergate.h
+++ b/arch/arm/mach-tegra/include/mach/powergate.h
@@ -27,6 +27,16 @@
#define TEGRA_POWERGATE_VDEC 4
#define TEGRA_POWERGATE_L2 5
#define TEGRA_POWERGATE_MPE 6
+#define TEGRA_POWERGATE_HEG 7
+#define TEGRA_POWERGATE_SATA 8
+#define TEGRA_POWERGATE_CPU1 9
+#define TEGRA_POWERGATE_CPU2 10
+#define TEGRA_POWERGATE_CPU3 11
+#define TEGRA_POWERGATE_CELP 12
+#define TEGRA_POWERGATE_3D1 13
+
+#define TEGRA_POWERGATE_CPU0 TEGRA_POWERGATE_CPU
+#define TEGRA_POWERGATE_3D0 TEGRA_POWERGATE_3D
int tegra_powergate_is_powered(int id);
int tegra_powergate_power_on(int id);
diff --git a/arch/arm/mach-tegra/powergate.c b/arch/arm/mach-tegra/powergate.c
index 984bbdf..7120ad7 100644
--- a/arch/arm/mach-tegra/powergate.c
+++ b/arch/arm/mach-tegra/powergate.c
@@ -167,6 +167,9 @@ int __init tegra_powergate_init(void)
case TEGRA20:
tegra_num_powerdomains = 7;
break;
+ case TEGRA30:
+ tegra_num_powerdomains = 14;
+ break;
default:
/* Unknown Tegra variant. Disable powergating */
tegra_num_powerdomains = 0;
--
1.7.7.rc0.72.g4b5ea.dirty
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH v2 7/8] ARM: tegra: support for Tegra30 CPU powerdomains
2012-01-31 16:40 [PATCH v2 0/8] Add tegra30 support for secondary cores Peter De Schrijver
` (5 preceding siblings ...)
2012-01-31 16:40 ` [PATCH v2 6/8] ARM: tegra: add support for Tegra30 powerdomains Peter De Schrijver
@ 2012-01-31 16:40 ` Peter De Schrijver
2012-01-31 16:40 ` [PATCH v2 8/8] ARM: tegra: support for secondary cores on Tegra30 Peter De Schrijver
2012-02-01 8:33 ` [PATCH v2 0/8] Add tegra30 support for secondary cores Olof Johansson
8 siblings, 0 replies; 20+ messages in thread
From: Peter De Schrijver @ 2012-01-31 16:40 UTC (permalink / raw)
To: Peter De Schrijver
Cc: Colin Cross, Olof Johansson, Stephen Warren, Russell King,
Gary King, Arnd Bergmann, linux-tegra, linux-arm-kernel,
linux-kernel
Secondary CPU powerdomains can be powergated on Tegra30. Add the necessary
functions to do this. This will be used to boot the secondary CPUs later on.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
---
arch/arm/mach-tegra/common.c | 3 +++
arch/arm/mach-tegra/include/mach/powergate.h | 3 +++
arch/arm/mach-tegra/powergate.c | 19 ++++++++++++++++++-
3 files changed, 24 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c
index 51dcbdff..0ad5c23 100644
--- a/arch/arm/mach-tegra/common.c
+++ b/arch/arm/mach-tegra/common.c
@@ -28,6 +28,7 @@
#include <mach/iomap.h>
#include <mach/system.h>
+#include <mach/powergate.h>
#include "board.h"
#include "clock.h"
@@ -117,6 +118,7 @@ void __init tegra20_init_early(void)
tegra2_init_clocks();
tegra_clk_init_from_table(tegra20_clk_init_table);
tegra_init_cache(0x331, 0x441);
+ tegra_powergate_init();
}
#endif
#ifdef CONFIG_ARCH_TEGRA_3x_SOC
@@ -125,5 +127,6 @@ void __init tegra30_init_early(void)
tegra_init_fuse();
tegra30_init_clocks();
tegra_init_cache(0x441, 0x551);
+ tegra_powergate_init();
}
#endif
diff --git a/arch/arm/mach-tegra/include/mach/powergate.h b/arch/arm/mach-tegra/include/mach/powergate.h
index ca41186..4752b1a 100644
--- a/arch/arm/mach-tegra/include/mach/powergate.h
+++ b/arch/arm/mach-tegra/include/mach/powergate.h
@@ -38,6 +38,9 @@
#define TEGRA_POWERGATE_CPU0 TEGRA_POWERGATE_CPU
#define TEGRA_POWERGATE_3D0 TEGRA_POWERGATE_3D
+int __init tegra_powergate_init(void);
+
+int tegra_cpu_powergate_id(int cpuid);
int tegra_powergate_is_powered(int id);
int tegra_powergate_power_on(int id);
int tegra_powergate_power_off(int id);
diff --git a/arch/arm/mach-tegra/powergate.c b/arch/arm/mach-tegra/powergate.c
index 7120ad7..c238699 100644
--- a/arch/arm/mach-tegra/powergate.c
+++ b/arch/arm/mach-tegra/powergate.c
@@ -41,6 +41,14 @@
#define PWRGATE_STATUS 0x38
static int tegra_num_powerdomains;
+static int tegra_num_cpu_domains;
+static u8 *tegra_cpu_domains;
+static u8 tegra30_cpu_domains[] = {
+ TEGRA_POWERGATE_CPU0,
+ TEGRA_POWERGATE_CPU1,
+ TEGRA_POWERGATE_CPU2,
+ TEGRA_POWERGATE_CPU3,
+};
static DEFINE_SPINLOCK(tegra_powergate_lock);
@@ -161,6 +169,14 @@ err_power:
return ret;
}
+int tegra_cpu_powergate_id(int cpuid)
+{
+ if (cpuid > 0 && cpuid < tegra_num_cpu_domains)
+ return tegra_cpu_domains[cpuid];
+
+ return -EINVAL;
+}
+
int __init tegra_powergate_init(void)
{
switch (tegra_chip_id) {
@@ -169,6 +185,8 @@ int __init tegra_powergate_init(void)
break;
case TEGRA30:
tegra_num_powerdomains = 14;
+ tegra_num_cpu_domains = 4;
+ tegra_cpu_domains = tegra30_cpu_domains;
break;
default:
/* Unknown Tegra variant. Disable powergating */
@@ -178,7 +196,6 @@ int __init tegra_powergate_init(void)
return 0;
}
-arch_initcall(tegra_powergate_init);
#ifdef CONFIG_DEBUG_FS
--
1.7.7.rc0.72.g4b5ea.dirty
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH v2 8/8] ARM: tegra: support for secondary cores on Tegra30
2012-01-31 16:40 [PATCH v2 0/8] Add tegra30 support for secondary cores Peter De Schrijver
` (6 preceding siblings ...)
2012-01-31 16:40 ` [PATCH v2 7/8] ARM: tegra: support for Tegra30 CPU powerdomains Peter De Schrijver
@ 2012-01-31 16:40 ` Peter De Schrijver
2012-02-02 18:04 ` Stephen Warren
2012-02-02 18:17 ` Colin Cross
2012-02-01 8:33 ` [PATCH v2 0/8] Add tegra30 support for secondary cores Olof Johansson
8 siblings, 2 replies; 20+ messages in thread
From: Peter De Schrijver @ 2012-01-31 16:40 UTC (permalink / raw)
To: Peter De Schrijver
Cc: Colin Cross, Olof Johansson, Stephen Warren, Russell King,
Gary King, Arnd Bergmann, linux-tegra, linux-arm-kernel,
linux-kernel
Add support for bringing up secondary cores on Tegra30. On Tegra30 secondary
CPU cores are powergated, so we need to turn on the domains before we can bring
the CPU cores online. Bringing secondary cores online happens early during the
sytem boot, so we call powergating initialization from platform early_init
function.
Based on work by:
Scott Williams <scwilliams@nvidia.com>
Colin Cross <ccross@android.com>
Alex Frid <afrid@nvidia.com>
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
---
arch/arm/mach-tegra/headsmp.S | 32 +++++++++++++++++++++++++
arch/arm/mach-tegra/platsmp.c | 52 ++++++++++++++++++++++++++++++++++++++++-
2 files changed, 83 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mach-tegra/headsmp.S b/arch/arm/mach-tegra/headsmp.S
index bb13e22..925c4a0 100644
--- a/arch/arm/mach-tegra/headsmp.S
+++ b/arch/arm/mach-tegra/headsmp.S
@@ -188,6 +188,38 @@ __die:
str r1, [r7, #0x340] @ CLK_RST_CPU_CMPLX_SET
#endif
1:
+#ifdef CONFIG_ARCH_TEGRA_3x_SOC
+ mov32 r6, TEGRA_FLOW_CTRL_BASE
+
+ cmp r10, #0
+ moveq r1, #FLOW_CTRL_HALT_CPU0_EVENTS
+ moveq r2, #FLOW_CTRL_CPU0_CSR
+ movne r1, r10, lsl #3
+ addne r2, r1, #(FLOW_CTRL_CPU1_CSR-8)
+ addne r1, r1, #(FLOW_CTRL_HALT_CPU1_EVENTS-8)
+
+ /* Clear CPU "event" and "interrupt" flags and power gate
+ it when halting but not before it is in the "WFI" state. */
+ ldr r0, [r6, +r2]
+ orr r0, r0, #FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG
+ orr r0, r0, #FLOW_CTRL_CSR_ENABLE
+ str r0, [r6, +r2]
+
+ /* Unconditionally halt this CPU */
+ mov r0, #FLOW_CTRL_WAITEVENT
+ str r0, [r6, +r1]
+ ldr r0, [r6, +r1] @ memory barrier
+
+ dsb
+ isb
+ wfi @ CPU should be power gated here
+
+ /* If the CPU didn't power gate above just kill it's clock. */
+
+ mov r0, r11, lsl #8
+ str r0, [r7, #348] @ CLK_CPU_CMPLX_SET
+#endif
+
/* If the CPU still isn't dead, just spin here. */
b .
ENDPROC(__tegra_cpu_reset_handler)
diff --git a/arch/arm/mach-tegra/platsmp.c b/arch/arm/mach-tegra/platsmp.c
index 79a241a..1fe3f58 100644
--- a/arch/arm/mach-tegra/platsmp.c
+++ b/arch/arm/mach-tegra/platsmp.c
@@ -24,7 +24,9 @@
#include <asm/mach-types.h>
#include <asm/smp_scu.h>
+#include <mach/clk.h>
#include <mach/iomap.h>
+#include <mach/powergate.h>
#include "fuse.h"
#include "flowctrl.h"
@@ -42,6 +44,8 @@ static void __iomem *scu_base = IO_ADDRESS(TEGRA_ARM_PERIF_BASE);
(IO_ADDRESS(TEGRA_CLK_RESET_BASE) + 0x340)
#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR \
(IO_ADDRESS(TEGRA_CLK_RESET_BASE) + 0x344)
+#define CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR \
+ (IO_ADDRESS(TEGRA_CLK_RESET_BASE) + 0x34c)
#define CPU_CLOCK(cpu) (0x1<<(8+cpu))
#define CPU_RESET(cpu) (0x1111ul<<(cpu))
@@ -73,11 +77,54 @@ static int tegra20_power_up_cpu(unsigned int cpu)
return 0;
}
+static int tegra30_power_up_cpu(unsigned int cpu)
+{
+ u32 reg;
+ int ret, pwrgateid;
+ unsigned long timeout;
+
+ pwrgateid = tegra_cpu_powergate_id(cpu);
+ if (pwrgateid < 0)
+ return pwrgateid;
+
+ /* If this is the first boot, toggle powergates directly. */
+ if (!tegra_powergate_is_powered(pwrgateid)) {
+ ret = tegra_powergate_power_on(pwrgateid);
+ if (ret)
+ return ret;
+
+ /* Wait for the power to come up. */
+ timeout = jiffies + 10*HZ;
+ do {
+ if (tegra_powergate_is_powered(pwrgateid))
+ goto remove_clamps;
+ udelay(10);
+ } while (time_before(jiffies, timeout));
+ return -ETIMEDOUT;
+ }
+
+remove_clamps:
+ /* CPU partition is powered. Enable the CPU clock. */
+ writel(CPU_CLOCK(cpu), CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR);
+ reg = readl(CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR);
+ udelay(10);
+
+ /* Remove I/O clamps. */
+ ret = tegra_powergate_remove_clamping(pwrgateid);
+ udelay(10);
+
+ /* Clear flow controller CSR. */
+ flowctrl_write_cpu_csr(cpu, 0);
+
+ return 0;
+}
+
int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
{
int status;
- /* Force the CPU into reset. The CPU must remain in reset when the
+ /*
+ * Force the CPU into reset. The CPU must remain in reset when the
* flow controller state is cleared (which will cause the flow
* controller to stop driving reset if the CPU has been power-gated
* via the flow controller). This will have no effect on first boot
@@ -98,6 +145,9 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
case TEGRA20:
status = tegra20_power_up_cpu(cpu);
break;
+ case TEGRA30:
+ status = tegra30_power_up_cpu(cpu);
+ break;
default:
status = -EINVAL;
break;
--
1.7.7.rc0.72.g4b5ea.dirty
^ permalink raw reply related [flat|nested] 20+ messages in thread* RE: [PATCH v2 8/8] ARM: tegra: support for secondary cores on Tegra30
2012-01-31 16:40 ` [PATCH v2 8/8] ARM: tegra: support for secondary cores on Tegra30 Peter De Schrijver
@ 2012-02-02 18:04 ` Stephen Warren
2012-02-06 23:23 ` Peter De Schrijver
2012-02-02 18:17 ` Colin Cross
1 sibling, 1 reply; 20+ messages in thread
From: Stephen Warren @ 2012-02-02 18:04 UTC (permalink / raw)
To: Peter De Schrijver
Cc: Colin Cross, Olof Johansson, Russell King, Gary King,
Arnd Bergmann, linux-tegra, linux-arm-kernel, linux-kernel
Peter De Schrijver wrote at Tuesday, January 31, 2012 9:41 AM:
> Add support for bringing up secondary cores on Tegra30. On Tegra30 secondary
> CPU cores are powergated, so we need to turn on the domains before we can bring
> the CPU cores online. Bringing secondary cores online happens early during the
> sytem boot, so we call powergating initialization from platform early_init
> function.
>
> Based on work by:
>
> Scott Williams <scwilliams@nvidia.com>
> Colin Cross <ccross@android.com>
> Alex Frid <afrid@nvidia.com>
>
> Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
The series,
Tested-by: Stephen Warren <swarren@nvidia.com>
This time, since I now have the SD card working, I managed to test real
user-space processes running on all 4 cores.
Note, patch 3 shouldn't compile due to a typo in a .size directive. It
does for me, so I could test this! But, it didn't for Olof. Aside from
that (which perhaps Olof would fixup during patch application?),
Acked-by: Stephen Warren <swarren@nvidia.com>
I also have a query on patch 3 about enabling coresight, but that's more
for my education than something that'd block patch application.
--
nvpublic
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v2 8/8] ARM: tegra: support for secondary cores on Tegra30
2012-02-02 18:04 ` Stephen Warren
@ 2012-02-06 23:23 ` Peter De Schrijver
0 siblings, 0 replies; 20+ messages in thread
From: Peter De Schrijver @ 2012-02-06 23:23 UTC (permalink / raw)
To: Stephen Warren
Cc: Colin Cross, Olof Johansson, Russell King, Gary King,
Arnd Bergmann, linux-tegra, linux-arm-kernel, linux-kernel
On Thu, Feb 02, 2012 at 07:04:12PM +0100, Stephen Warren wrote:
> Peter De Schrijver wrote at Tuesday, January 31, 2012 9:41 AM:
> > Add support for bringing up secondary cores on Tegra30. On Tegra30 secondary
> > CPU cores are powergated, so we need to turn on the domains before we can bring
> > the CPU cores online. Bringing secondary cores online happens early during the
> > sytem boot, so we call powergating initialization from platform early_init
> > function.
> >
> > Based on work by:
> >
> > Scott Williams <scwilliams@nvidia.com>
> > Colin Cross <ccross@android.com>
> > Alex Frid <afrid@nvidia.com>
> >
> > Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
>
> The series,
>
> Tested-by: Stephen Warren <swarren@nvidia.com>
>
> This time, since I now have the SD card working, I managed to test real
> user-space processes running on all 4 cores.
>
> Note, patch 3 shouldn't compile due to a typo in a .size directive. It
> does for me, so I could test this! But, it didn't for Olof. Aside from
> that (which perhaps Olof would fixup during patch application?),
Indeed. The .size symbol is never used though, which might explain why it
compiled for you and me. I will leave it out in th enext version.
Cheers,
Peter.
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v2 8/8] ARM: tegra: support for secondary cores on Tegra30
2012-01-31 16:40 ` [PATCH v2 8/8] ARM: tegra: support for secondary cores on Tegra30 Peter De Schrijver
2012-02-02 18:04 ` Stephen Warren
@ 2012-02-02 18:17 ` Colin Cross
1 sibling, 0 replies; 20+ messages in thread
From: Colin Cross @ 2012-02-02 18:17 UTC (permalink / raw)
To: Peter De Schrijver
Cc: Olof Johansson, Stephen Warren, Russell King, Gary King,
Arnd Bergmann, linux-tegra, linux-arm-kernel, linux-kernel
On Tue, Jan 31, 2012 at 8:40 AM, Peter De Schrijver
<pdeschrijver@nvidia.com> wrote:
> Add support for bringing up secondary cores on Tegra30. On Tegra30 secondary
> CPU cores are powergated, so we need to turn on the domains before we can bring
> the CPU cores online. Bringing secondary cores online happens early during the
> sytem boot, so we call powergating initialization from platform early_init
> function.
>
> Based on work by:
>
> Scott Williams <scwilliams@nvidia.com>
> Colin Cross <ccross@android.com>
> Alex Frid <afrid@nvidia.com>
>
> Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
> ---
> arch/arm/mach-tegra/headsmp.S | 32 +++++++++++++++++++++++++
> arch/arm/mach-tegra/platsmp.c | 52 ++++++++++++++++++++++++++++++++++++++++-
> 2 files changed, 83 insertions(+), 1 deletions(-)
>
> diff --git a/arch/arm/mach-tegra/headsmp.S b/arch/arm/mach-tegra/headsmp.S
> index bb13e22..925c4a0 100644
> --- a/arch/arm/mach-tegra/headsmp.S
> +++ b/arch/arm/mach-tegra/headsmp.S
> @@ -188,6 +188,38 @@ __die:
> str r1, [r7, #0x340] @ CLK_RST_CPU_CMPLX_SET
> #endif
> 1:
> +#ifdef CONFIG_ARCH_TEGRA_3x_SOC
> + mov32 r6, TEGRA_FLOW_CTRL_BASE
> +
> + cmp r10, #0
> + moveq r1, #FLOW_CTRL_HALT_CPU0_EVENTS
> + moveq r2, #FLOW_CTRL_CPU0_CSR
> + movne r1, r10, lsl #3
> + addne r2, r1, #(FLOW_CTRL_CPU1_CSR-8)
> + addne r1, r1, #(FLOW_CTRL_HALT_CPU1_EVENTS-8)
> +
> + /* Clear CPU "event" and "interrupt" flags and power gate
> + it when halting but not before it is in the "WFI" state. */
> + ldr r0, [r6, +r2]
> + orr r0, r0, #FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG
> + orr r0, r0, #FLOW_CTRL_CSR_ENABLE
> + str r0, [r6, +r2]
> +
> + /* Unconditionally halt this CPU */
> + mov r0, #FLOW_CTRL_WAITEVENT
> + str r0, [r6, +r1]
> + ldr r0, [r6, +r1] @ memory barrier
> +
> + dsb
> + isb
> + wfi @ CPU should be power gated here
> +
> + /* If the CPU didn't power gate above just kill it's clock. */
> +
> + mov r0, r11, lsl #8
> + str r0, [r7, #348] @ CLK_CPU_CMPLX_SET
> +#endif
> +
> /* If the CPU still isn't dead, just spin here. */
> b .
> ENDPROC(__tegra_cpu_reset_handler)
> diff --git a/arch/arm/mach-tegra/platsmp.c b/arch/arm/mach-tegra/platsmp.c
> index 79a241a..1fe3f58 100644
> --- a/arch/arm/mach-tegra/platsmp.c
> +++ b/arch/arm/mach-tegra/platsmp.c
> @@ -24,7 +24,9 @@
> #include <asm/mach-types.h>
> #include <asm/smp_scu.h>
>
> +#include <mach/clk.h>
> #include <mach/iomap.h>
> +#include <mach/powergate.h>
>
> #include "fuse.h"
> #include "flowctrl.h"
> @@ -42,6 +44,8 @@ static void __iomem *scu_base = IO_ADDRESS(TEGRA_ARM_PERIF_BASE);
> (IO_ADDRESS(TEGRA_CLK_RESET_BASE) + 0x340)
> #define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR \
> (IO_ADDRESS(TEGRA_CLK_RESET_BASE) + 0x344)
> +#define CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR \
> + (IO_ADDRESS(TEGRA_CLK_RESET_BASE) + 0x34c)
>
> #define CPU_CLOCK(cpu) (0x1<<(8+cpu))
> #define CPU_RESET(cpu) (0x1111ul<<(cpu))
> @@ -73,11 +77,54 @@ static int tegra20_power_up_cpu(unsigned int cpu)
> return 0;
> }
>
> +static int tegra30_power_up_cpu(unsigned int cpu)
> +{
> + u32 reg;
> + int ret, pwrgateid;
> + unsigned long timeout;
> +
> + pwrgateid = tegra_cpu_powergate_id(cpu);
> + if (pwrgateid < 0)
> + return pwrgateid;
> +
> + /* If this is the first boot, toggle powergates directly. */
> + if (!tegra_powergate_is_powered(pwrgateid)) {
> + ret = tegra_powergate_power_on(pwrgateid);
> + if (ret)
> + return ret;
> +
> + /* Wait for the power to come up. */
> + timeout = jiffies + 10*HZ;
> + do {
> + if (tegra_powergate_is_powered(pwrgateid))
> + goto remove_clamps;
> + udelay(10);
> + } while (time_before(jiffies, timeout));
> + return -ETIMEDOUT;
> + }
This loop + goto seems convoluted. Why not untangle it:
timeout = jiffies + 10*HZ;
while (tegra_powergate_is_powered(pwrgateid)) {
if (time_after(jiffies, timeout))
return -ETIMEDOUT;
udelay(10);
}
> +
> +remove_clamps:
> + /* CPU partition is powered. Enable the CPU clock. */
> + writel(CPU_CLOCK(cpu), CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR);
> + reg = readl(CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR);
> + udelay(10);
> +
> + /* Remove I/O clamps. */
> + ret = tegra_powergate_remove_clamping(pwrgateid);
> + udelay(10);
> +
> + /* Clear flow controller CSR. */
> + flowctrl_write_cpu_csr(cpu, 0);
> +
> + return 0;
> +}
> +
> int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
> {
> int status;
>
> - /* Force the CPU into reset. The CPU must remain in reset when the
> + /*
> + * Force the CPU into reset. The CPU must remain in reset when the
> * flow controller state is cleared (which will cause the flow
> * controller to stop driving reset if the CPU has been power-gated
> * via the flow controller). This will have no effect on first boot
> @@ -98,6 +145,9 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
> case TEGRA20:
> status = tegra20_power_up_cpu(cpu);
> break;
> + case TEGRA30:
> + status = tegra30_power_up_cpu(cpu);
> + break;
> default:
> status = -EINVAL;
> break;
> --
> 1.7.7.rc0.72.g4b5ea.dirty
>
Other than that, Acked-by: Colin Cross <ccross@android.com>
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v2 0/8] Add tegra30 support for secondary cores
2012-01-31 16:40 [PATCH v2 0/8] Add tegra30 support for secondary cores Peter De Schrijver
` (7 preceding siblings ...)
2012-01-31 16:40 ` [PATCH v2 8/8] ARM: tegra: support for secondary cores on Tegra30 Peter De Schrijver
@ 2012-02-01 8:33 ` Olof Johansson
2012-02-01 10:10 ` Peter De Schrijver
8 siblings, 1 reply; 20+ messages in thread
From: Olof Johansson @ 2012-02-01 8:33 UTC (permalink / raw)
To: Peter De Schrijver
Cc: Colin Cross, Stephen Warren, Russell King, Gary King,
Arnd Bergmann, linux-tegra, linux-arm-kernel, linux-kernel
Hi,
On Tue, Jan 31, 2012 at 06:40:38PM +0200, Peter De Schrijver wrote:
> This patchset introduces support for secondary cores on tegra30. It also
> introduces some functions for the flowcontroller and adds basic support for
> tegra30 powerdomains.
It would be very useful to get a quick recap of what has changed since
previous versions in the cover email, if not detailed in the individual
patches (which it doesn't seem to be).
-Olof
^ permalink raw reply [flat|nested] 20+ messages in thread* Re: [PATCH v2 0/8] Add tegra30 support for secondary cores
2012-02-01 8:33 ` [PATCH v2 0/8] Add tegra30 support for secondary cores Olof Johansson
@ 2012-02-01 10:10 ` Peter De Schrijver
0 siblings, 0 replies; 20+ messages in thread
From: Peter De Schrijver @ 2012-02-01 10:10 UTC (permalink / raw)
To: Olof Johansson
Cc: Colin Cross, Stephen Warren, Russell King, Gary King,
Arnd Bergmann, linux-tegra, linux-arm-kernel, linux-kernel
On Wed, Feb 01, 2012 at 09:33:34AM +0100, Olof Johansson wrote:
> Hi,
>
> On Tue, Jan 31, 2012 at 06:40:38PM +0200, Peter De Schrijver wrote:
> > This patchset introduces support for secondary cores on tegra30. It also
> > introduces some functions for the flowcontroller and adds basic support for
> > tegra30 powerdomains.
>
> It would be very useful to get a quick recap of what has changed since
> previous versions in the cover email, if not detailed in the individual
> patches (which it doesn't seem to be).
>
Oops. I forgot about that.
Here it is:
Changes in v2:
* moved chip id reading to fuse.c and cleanup code
* don't set bit 1 of SB_CTRL on Tegra20
* removed unused variables in tegra_cpu_reset_handler_init()
Cheers,
Peter.
^ permalink raw reply [flat|nested] 20+ messages in thread