From: Robert Richter <rric@kernel.org>
To: Stephane Eranian <eranian@google.com>
Cc: Jacob Shin <jacob.shin@amd.com>,
Peter Zijlstra <a.p.zijlstra@chello.nl>,
Paul Mackerras <paulus@samba.org>, Ingo Molnar <mingo@redhat.com>,
Arnaldo Carvalho de Melo <acme@ghostprotocols.net>,
Thomas Gleixner <tglx@linutronix.de>,
"H. Peter Anvin" <hpa@zytor.com>, x86 <x86@kernel.org>,
LKML <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH 0/4] perf, amd: Enable AMD family 15h northbridge counters
Date: Mon, 12 Nov 2012 15:36:30 +0100 [thread overview]
Message-ID: <20121112143630.GB24433@rric.localhost> (raw)
In-Reply-To: <CABPqkBSdEsKwzni2VQcedV9tOFWWCVVV4WhmkWHRp6nFTo9wDA@mail.gmail.com>
On 11.11.12 19:17:07, Stephane Eranian wrote:
> On Sat, Nov 10, 2012 at 12:50 PM, Robert Richter <rric@kernel.org> wrote:
> > Peter's main concerns were that my patch set is not in the
> > Intel-uncore style. I started reworking this but was not able to
> > finish my work. This concerns still exist.
> >
> That was my concern too. I don't recall exactly why it could not
> be totally disconnected from the core PMU. I think hardware-wise,
> it was possible. Could you refresh my memory?
Current implementation only allows the use of a single x86 pmu.
Multiple instances of x86 pmus in a system like an additional pmu for
nb counters requires a complete rework. You need to remove global
variables and extend function interfaces by arguments pointing to a
struct x86_pmu. All this without adding overhead (e.g. pointer
chasing) compared to the existing code.
This is also the reason why the intel-uncore implemenation is
basically a copy-and-paste of generic x86 pmu code plus uncore
specific changes.
Avoiding code cuplication and a complex rework were the reasons for
simply extending the family 10h implementation to also support family
15h nb counters. This seemed to me the best approach that time.
-Robert
next prev parent reply other threads:[~2012-11-12 14:36 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-11-10 1:01 [PATCH 0/4] perf, amd: Enable AMD family 15h northbridge counters Jacob Shin
2012-11-10 1:01 ` [PATCH 1/4] perf, amd: Simplify northbridge event constraints handler Jacob Shin
2012-11-10 1:01 ` [PATCH 2/4] perf, amd: Refactor northbridge event constraints handler for code sharing Jacob Shin
2012-11-10 1:01 ` [PATCH 3/4] perf, x86: Move MSR address offset calculation to architecture specific files Jacob Shin
2012-11-10 1:01 ` [PATCH 4/4] perf, amd: Enable northbridge performance counters on AMD family 15h Jacob Shin
2012-11-10 11:50 ` [PATCH 0/4] perf, amd: Enable AMD family 15h northbridge counters Robert Richter
2012-11-11 18:17 ` Stephane Eranian
2012-11-12 14:36 ` Robert Richter [this message]
2012-11-11 18:44 ` Jacob Shin
2012-11-12 12:24 ` Stephane Eranian
2012-11-12 14:22 ` Robert Richter
2012-11-12 16:13 ` Jacob Shin
2012-11-12 21:08 ` Stephane Eranian
2012-11-12 14:55 ` Robert Richter
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