From: Stephane Eranian <eranian@google.com>
To: Robert Richter <rric@kernel.org>
Cc: Jacob Shin <jacob.shin@amd.com>,
Peter Zijlstra <a.p.zijlstra@chello.nl>,
Paul Mackerras <paulus@samba.org>, Ingo Molnar <mingo@redhat.com>,
Arnaldo Carvalho de Melo <acme@ghostprotocols.net>,
Thomas Gleixner <tglx@linutronix.de>,
"H. Peter Anvin" <hpa@zytor.com>, x86 <x86@kernel.org>,
LKML <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH 0/4] perf, amd: Enable AMD family 15h northbridge counters
Date: Sun, 11 Nov 2012 19:17:07 +0100 [thread overview]
Message-ID: <CABPqkBSdEsKwzni2VQcedV9tOFWWCVVV4WhmkWHRp6nFTo9wDA@mail.gmail.com> (raw)
In-Reply-To: <20121110115027.GC2777@rric.localhost>
On Sat, Nov 10, 2012 at 12:50 PM, Robert Richter <rric@kernel.org> wrote:
> On 09.11.12 19:01:34, Jacob Shin wrote:
>> The following patchset enables 4 additional performance counters in
>> AMD family 15h processors that counts northbridge events -- such as
>> DRAM accesses.
>>
>> This patchset is based on previous work done by Robert Richter
>> <rric@kernel.org> :
>>
>> https://lkml.org/lkml/2012/6/19/324
>
> The original patch set of this is here (a rebased version):
>
> http://git.kernel.org/?p=linux/kernel/git/rric/oprofile.git;a=shortlog;h=refs/heads/perf-nb
>
> This code was tested in detail.
>
>> The main differences are:
>>
>> - The northbridge counters are indexed contiguously right above the
>> core performance counters.
>>
>> - MSR address offset calculations are moved to architecture specific
>> files.
>>
>> - Interrups are set up to be delivered only to a single core.
>
> So I rather suggest to make delta patches on top of my patches.
>
> Peter's main concerns were that my patch set is not in the
> Intel-uncore style. I started reworking this but was not able to
> finish my work. This concerns still exist.
>
That was my concern too. I don't recall exactly why it could not
be totally disconnected from the core PMU. I think hardware-wise,
it was possible. Could you refresh my memory?
next prev parent reply other threads:[~2012-11-11 18:17 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-11-10 1:01 [PATCH 0/4] perf, amd: Enable AMD family 15h northbridge counters Jacob Shin
2012-11-10 1:01 ` [PATCH 1/4] perf, amd: Simplify northbridge event constraints handler Jacob Shin
2012-11-10 1:01 ` [PATCH 2/4] perf, amd: Refactor northbridge event constraints handler for code sharing Jacob Shin
2012-11-10 1:01 ` [PATCH 3/4] perf, x86: Move MSR address offset calculation to architecture specific files Jacob Shin
2012-11-10 1:01 ` [PATCH 4/4] perf, amd: Enable northbridge performance counters on AMD family 15h Jacob Shin
2012-11-10 11:50 ` [PATCH 0/4] perf, amd: Enable AMD family 15h northbridge counters Robert Richter
2012-11-11 18:17 ` Stephane Eranian [this message]
2012-11-12 14:36 ` Robert Richter
2012-11-11 18:44 ` Jacob Shin
2012-11-12 12:24 ` Stephane Eranian
2012-11-12 14:22 ` Robert Richter
2012-11-12 16:13 ` Jacob Shin
2012-11-12 21:08 ` Stephane Eranian
2012-11-12 14:55 ` Robert Richter
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