From: Thomas Gleixner <tglx@linutronix.de>
To: LKML <linux-kernel@vger.kernel.org>
Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>,
Russell King - ARM Linux <linux@arm.linux.org.uk>,
Grant Likely <grant.likely@linaro.org>,
Rob Herring <rob.herring@calxeda.com>,
Rob Landley <rob@landley.net>, Arnd Bergmann <arnd@arndb.de>,
Jason Cooper <jason@lakedaemon.net>, Andrew Lunn <andrew@lunn.ch>,
Jason Gunthorpe <jgunthorpe@obsidianresearch.com>,
Thomas Petazzoni <thomas.petazzoni@free-electrons.com>,
Gregory Clement <gregory.clement@free-electrons.com>,
Ezequiel Garcia <ezequiel.garcia@free-electrons.com>,
Maxime Ripard <maxime.ripard@free-electrons.com>,
Jean-Francois Moine <moinejf@free.fr>,
Gerlando Falauto <gerlando.falauto@keymile.com>,
devicetree-discuss@lists.ozlabs.org, linux-doc@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
Subject: [patch 4/8] genirq: generic chip: Cache per irq bit mask
Date: Mon, 06 May 2013 14:30:22 -0000 [thread overview]
Message-ID: <20130506142539.227119865@linutronix.de> (raw)
In-Reply-To: 20130506142348.321859745@linutronix.de
[-- Attachment #1: genirq-generic-chip-cache-mask.patch --]
[-- Type: text/plain, Size: 4856 bytes --]
Cache the per irq bit mask instead of recalculating it over and over.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
---
include/linux/irq.h | 4 ++++
kernel/irq/generic-chip.c | 23 ++++++++++++++---------
2 files changed, 18 insertions(+), 9 deletions(-)
Index: linux-2.6/include/linux/irq.h
===================================================================
--- linux-2.6.orig/include/linux/irq.h
+++ linux-2.6/include/linux/irq.h
@@ -119,6 +119,7 @@ struct irq_domain;
/**
* struct irq_data - per irq and irq chip data passed down to chip functions
+ * @mask: precomputed bitmask for accessing the chip registers
* @irq: interrupt number
* @hwirq: hardware interrupt number, local to the interrupt domain
* @node: node index useful for balancing
@@ -138,6 +139,7 @@ struct irq_domain;
* irq_data.
*/
struct irq_data {
+ u32 mask;
unsigned int irq;
unsigned long hwirq;
unsigned int node;
@@ -705,11 +707,13 @@ struct irq_chip_generic {
* irq chips which need to call irq_set_wake() on
* the parent irq. Usually GPIO implementations
* @IRQ_GC_MASK_CACHE_PER_TYPE: Mask cache is chip type private
+ * @IRQ_GC_NO_MASK: Do not calculate irq_data->mask
*/
enum irq_gc_flags {
IRQ_GC_INIT_MASK_CACHE = 1 << 0,
IRQ_GC_INIT_NESTED_LOCK = 1 << 1,
IRQ_GC_MASK_CACHE_PER_TYPE = 1 << 2,
+ IRQ_GC_NO_MASK = 1 << 3,
};
/* Generic chip callback functions */
Index: linux-2.6/kernel/irq/generic-chip.c
===================================================================
--- linux-2.6.orig/kernel/irq/generic-chip.c
+++ linux-2.6/kernel/irq/generic-chip.c
@@ -35,7 +35,7 @@ void irq_gc_mask_disable_reg(struct irq_
{
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
struct irq_chip_type *ct = irq_data_get_chip_type(d);
- u32 mask = 1 << (d->irq - gc->irq_base);
+ u32 mask = d->mask;
irq_gc_lock(gc);
irq_reg_writel(mask, gc->reg_base + ct->regs.disable);
@@ -54,7 +54,7 @@ void irq_gc_mask_set_bit(struct irq_data
{
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
struct irq_chip_type *ct = irq_data_get_chip_type(d);
- u32 mask = 1 << (d->irq - gc->irq_base);
+ u32 mask = d->mask;
irq_gc_lock(gc);
*ct->mask_cache |= mask;
@@ -73,7 +73,7 @@ void irq_gc_mask_clr_bit(struct irq_data
{
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
struct irq_chip_type *ct = irq_data_get_chip_type(d);
- u32 mask = 1 << (d->irq - gc->irq_base);
+ u32 mask = d->mask;
irq_gc_lock(gc);
*ct->mask_cache &= ~mask;
@@ -92,7 +92,7 @@ void irq_gc_unmask_enable_reg(struct irq
{
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
struct irq_chip_type *ct = irq_data_get_chip_type(d);
- u32 mask = 1 << (d->irq - gc->irq_base);
+ u32 mask = d->mask;
irq_gc_lock(gc);
irq_reg_writel(mask, gc->reg_base + ct->regs.enable);
@@ -108,7 +108,7 @@ void irq_gc_ack_set_bit(struct irq_data
{
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
struct irq_chip_type *ct = irq_data_get_chip_type(d);
- u32 mask = 1 << (d->irq - gc->irq_base);
+ u32 mask = d->mask;
irq_gc_lock(gc);
irq_reg_writel(mask, gc->reg_base + ct->regs.ack);
@@ -123,7 +123,7 @@ void irq_gc_ack_clr_bit(struct irq_data
{
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
struct irq_chip_type *ct = irq_data_get_chip_type(d);
- u32 mask = ~(1 << (d->irq - gc->irq_base));
+ u32 mask = ~d->mask;
irq_gc_lock(gc);
irq_reg_writel(mask, gc->reg_base + ct->regs.ack);
@@ -138,7 +138,7 @@ void irq_gc_mask_disable_reg_and_ack(str
{
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
struct irq_chip_type *ct = irq_data_get_chip_type(d);
- u32 mask = 1 << (d->irq - gc->irq_base);
+ u32 mask = d->mask;
irq_gc_lock(gc);
irq_reg_writel(mask, gc->reg_base + ct->regs.mask);
@@ -154,7 +154,7 @@ void irq_gc_eoi(struct irq_data *d)
{
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
struct irq_chip_type *ct = irq_data_get_chip_type(d);
- u32 mask = 1 << (d->irq - gc->irq_base);
+ u32 mask = d->mask;
irq_gc_lock(gc);
irq_reg_writel(mask, gc->reg_base + ct->regs.eoi);
@@ -172,7 +172,7 @@ void irq_gc_eoi(struct irq_data *d)
int irq_gc_set_wake(struct irq_data *d, unsigned int on)
{
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
- u32 mask = 1 << (d->irq - gc->irq_base);
+ u32 mask = d->mask;
if (!(mask & gc->wake_enabled))
return -EINVAL;
@@ -264,6 +264,11 @@ void irq_setup_generic_chip(struct irq_c
if (flags & IRQ_GC_INIT_NESTED_LOCK)
irq_set_lockdep_class(i, &irq_nested_lock_class);
+ if (!(flags & IRQ_GC_NO_MASK)) {
+ struct irq_data *d = irq_get_irq_data(i);
+
+ d->mask = 1 << (i - gc->irq_base);
+ }
irq_set_chip_and_handler(i, &ct->chip, ct->handler);
irq_set_chip_data(i, gc);
irq_modify_status(i, clr, set);
next prev parent reply other threads:[~2013-05-06 14:30 UTC|newest]
Thread overview: 79+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-05-02 18:25 [PATCH] irqchip: add support for Marvell Orion SoCs Sebastian Hesselbarth
2013-05-02 18:33 ` Sebastian Hesselbarth
2013-05-02 18:45 ` Russell King - ARM Linux
2013-05-02 18:54 ` Sebastian Hesselbarth
2013-05-02 18:56 ` Russell King - ARM Linux
2013-05-02 19:04 ` Sebastian Hesselbarth
2013-05-02 18:53 ` Jason Gunthorpe
2013-05-02 19:05 ` Sebastian Hesselbarth
2013-05-02 19:35 ` Jason Gunthorpe
2013-05-02 19:48 ` Sebastian Hesselbarth
2013-05-02 20:02 ` Andrew Lunn
2013-05-02 20:08 ` Gregory CLEMENT
2013-05-04 17:58 ` Jason Cooper
2013-05-02 19:11 ` Arnd Bergmann
2013-05-02 19:34 ` Sebastian Hesselbarth
2013-05-02 19:37 ` Jason Gunthorpe
2013-05-02 19:39 ` Sebastian Hesselbarth
2013-05-02 19:22 ` Jason Cooper
2013-05-02 21:34 ` Thomas Gleixner
2013-05-02 21:56 ` Sebastian Hesselbarth
2013-05-02 22:09 ` Arnd Bergmann
2013-05-02 22:37 ` Sebastian Hesselbarth
2013-05-04 18:12 ` Jason Cooper
2013-05-02 23:48 ` [PATCH v2 0/5] ARM: orion: add orion irqchip driver Sebastian Hesselbarth
2013-05-02 23:48 ` [PATCH v2 1/5] irqchip: add support for Marvell Orion SoCs Sebastian Hesselbarth
2013-05-03 12:55 ` Russell King - ARM Linux
2013-05-03 13:13 ` Sebastian Hesselbarth
2013-05-03 14:09 ` Thomas Gleixner
2013-05-03 21:50 ` [RFC patch 0/8] genirq: Support for irq domains in generic irq chip Thomas Gleixner
2013-05-03 21:50 ` [RFC patch 1/8] genirq: generic chip: Remove the local cur_regs() function Thomas Gleixner
2013-05-03 21:50 ` [RFC patch 3/8] genirq: generic chip: Handle separate mask registers Thomas Gleixner
2013-05-03 21:50 ` [RFC patch 4/8] genirq: generic chip: Cache per irq bit mask Thomas Gleixner
2013-05-03 22:24 ` Russell King - ARM Linux
2013-05-03 22:39 ` Thomas Gleixner
2013-05-03 21:50 ` [RFC patch 5/8] genirq: Add a mask calculation function Thomas Gleixner
2013-05-03 21:50 ` [RFC patch 6/8] genirq: Split out code in generic chip Thomas Gleixner
2013-05-27 13:45 ` Grant Likely
2013-05-03 21:50 ` [RFC patch 7/8] genirq: generic chip: Add linear irq domain support Thomas Gleixner
2013-05-03 22:23 ` Russell King - ARM Linux
2013-05-03 22:38 ` Thomas Gleixner
2013-05-04 2:30 ` Sebastian Hesselbarth
2013-05-04 8:04 ` Thomas Gleixner
2013-05-06 12:32 ` [RFC patch 7/8] fixup 1/2: " Sebastian Hesselbarth
2013-05-06 12:32 ` [RFC patch 7/8] fixup 2/2: " Sebastian Hesselbarth
2013-05-06 13:31 ` Thomas Gleixner
2013-05-06 13:25 ` [RFC patch 7/8] fixup 1/2: " Thomas Gleixner
2013-05-03 21:50 ` [RFC patch 8/8] irqchip: sun4i: Convert to generic irq chip Thomas Gleixner
2013-05-04 2:37 ` Sebastian Hesselbarth
2013-05-06 9:48 ` [RFC patch 0/8] genirq: Support for irq domains in " Uwe Kleine-König
2013-05-06 14:30 ` [patch 0/8] genirq: Support for irq domains in generic irq chip - V2 Thomas Gleixner
2013-05-06 14:30 ` [patch 1/8] genirq: generic chip: Remove the local cur_regs() function Thomas Gleixner
2013-05-29 9:14 ` [tip:irq/core] genirq: Generic " tip-bot for Gerlando Falauto
2013-05-06 14:30 ` [patch 3/8] genirq: generic chip: Handle separate mask registers Thomas Gleixner
2013-05-29 9:17 ` [tip:irq/core] genirq: Generic " tip-bot for Gerlando Falauto
2013-05-06 14:30 ` Thomas Gleixner [this message]
2013-05-29 9:18 ` [tip:irq/core] genirq: Generic chip: Cache per irq bit mask tip-bot for Thomas Gleixner
2013-05-06 14:30 ` [patch 5/8] genirq: Add a mask calculation function Thomas Gleixner
2013-05-29 9:19 ` [tip:irq/core] genirq: irqchip: " tip-bot for Thomas Gleixner
2013-05-06 14:30 ` [patch 6/8] genirq: Split out code in generic chip Thomas Gleixner
2013-05-29 9:21 ` [tip:irq/core] genirq: Generic chip: Split out code into separate functions tip-bot for Thomas Gleixner
2013-05-06 14:30 ` [patch 7/8] genirq: generic chip: Add linear irq domain support Thomas Gleixner
2013-05-29 2:22 ` Grant Likely
2013-05-29 8:23 ` Thomas Gleixner
2013-05-29 9:22 ` [tip:irq/core] genirq: Generic " tip-bot for Thomas Gleixner
2013-05-06 14:30 ` [patch 8/8] irqchip: sun4i: Convert to generic irq chip Thomas Gleixner
2013-05-06 15:18 ` Rob Herring
2013-05-12 14:05 ` [PATCH] irq-sun4i: Fix trivial build errors Maxime Ripard
2013-05-12 14:08 ` [patch 8/8] irqchip: sun4i: Convert to generic irq chip Maxime Ripard
2013-05-12 14:14 ` Maxime Ripard
2013-05-13 10:57 ` [patch 0/8] genirq: Support for irq domains in generic irq chip - V2 Gerlando Falauto
2013-05-13 12:01 ` Thomas Gleixner
2013-10-01 15:27 ` Gerlando Falauto
2013-05-02 23:48 ` [PATCH v2 2/5] ARM: dove: add DT parsing for legacy mv643xx_eth Sebastian Hesselbarth
2013-05-03 5:06 ` Andrew Lunn
2013-05-03 9:58 ` Sebastian Hesselbarth
2013-05-04 18:29 ` Jason Cooper
2013-05-02 23:48 ` [PATCH v2 3/5] ARM: dove: add DT parsing for legacy timer Sebastian Hesselbarth
2013-05-02 23:48 ` [PATCH v2 4/5] ARM: dove: move DT boards to orion irqchip driver Sebastian Hesselbarth
2013-05-02 23:48 ` [PATCH v2 5/5] ARM: dove: add DT nodes for irqchip conversion Sebastian Hesselbarth
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