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* RE: [PATCH] x86/tlb_info: detect more tlb configuration
       [not found] <1370358196-5699-1-git-send-email-kirill.shutemov@linux.intel.com>
@ 2013-06-04 15:09 ` Kirill A. Shutemov
  2013-06-05  1:09   ` Alex Shi
  0 siblings, 1 reply; 4+ messages in thread
From: Kirill A. Shutemov @ 2013-06-04 15:09 UTC (permalink / raw)
  To: Kirill A. Shutemov
  Cc: H. Peter Anvin, Thomas Gleixner, Ingo Molnar, Alex Shi,
	Kirill A. Shutemov, x86, linux-kernel

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Kirill A. Shutemov wrote:
> From: "Kirill A. Shutemov" <kirill.shutemov@linux.intel.com>
> 

Err.. Forgot CC lists.

> Software Developer’s Manual covers two more TLB configurations:
> 
> 63H Data TLB: 1 GByte pages, 4-way set associative, 4 entries
> 76H Instruction TLB: 2M/4M pages, fully associative, 8 entries
> 
> Let's detect them as well.
> 
> Signed-off-by: Kirill A. Shutemov <kirill.shutemov@linux.intel.com>
> ---
>  arch/x86/include/asm/processor.h |    1 +
>  arch/x86/kernel/cpu/common.c     |    7 ++++---
>  arch/x86/kernel/cpu/intel.c      |    6 ++++++
>  3 files changed, 11 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h
> index 3270116..1476a41 100644
> --- a/arch/x86/include/asm/processor.h
> +++ b/arch/x86/include/asm/processor.h
> @@ -72,6 +72,7 @@ extern u16 __read_mostly tlb_lli_4m[NR_INFO];
>  extern u16 __read_mostly tlb_lld_4k[NR_INFO];
>  extern u16 __read_mostly tlb_lld_2m[NR_INFO];
>  extern u16 __read_mostly tlb_lld_4m[NR_INFO];
> +extern u16 __read_mostly tlb_lld_1g[NR_INFO];
>  extern s8  __read_mostly tlb_flushall_shift;
>  
>  /*
> diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
> index d814772..ee2f15b 100644
> --- a/arch/x86/kernel/cpu/common.c
> +++ b/arch/x86/kernel/cpu/common.c
> @@ -470,6 +470,7 @@ u16 __read_mostly tlb_lli_4m[NR_INFO];
>  u16 __read_mostly tlb_lld_4k[NR_INFO];
>  u16 __read_mostly tlb_lld_2m[NR_INFO];
>  u16 __read_mostly tlb_lld_4m[NR_INFO];
> +u16 __read_mostly tlb_lld_1g[NR_INFO];
>  
>  /*
>   * tlb_flushall_shift shows the balance point in replacing cr3 write
> @@ -484,13 +485,13 @@ void __cpuinit cpu_detect_tlb(struct cpuinfo_x86 *c)
>  	if (this_cpu->c_detect_tlb)
>  		this_cpu->c_detect_tlb(c);
>  
> -	printk(KERN_INFO "Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n" \
> -		"Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d\n"	     \
> +	printk(KERN_INFO "Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n"
> +		"Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d, 1GB %d\n"
>  		"tlb_flushall_shift: %d\n",
>  		tlb_lli_4k[ENTRIES], tlb_lli_2m[ENTRIES],
>  		tlb_lli_4m[ENTRIES], tlb_lld_4k[ENTRIES],
>  		tlb_lld_2m[ENTRIES], tlb_lld_4m[ENTRIES],
> -		tlb_flushall_shift);
> +		tlb_lld_1g[ENTRIES], tlb_flushall_shift);
>  }
>  
>  void __cpuinit detect_ht(struct cpuinfo_x86 *c)
> diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
> index 1905ce9..1130519 100644
> --- a/arch/x86/kernel/cpu/intel.c
> +++ b/arch/x86/kernel/cpu/intel.c
> @@ -529,6 +529,8 @@ static const struct _tlb_table intel_tlb_table[] __cpuinitconst = {
>  	{ 0x5b, TLB_DATA_4K_4M,		64,	" TLB_DATA 4 KByte and 4 MByte pages" },
>  	{ 0x5c, TLB_DATA_4K_4M,		128,	" TLB_DATA 4 KByte and 4 MByte pages" },
>  	{ 0x5d, TLB_DATA_4K_4M,		256,	" TLB_DATA 4 KByte and 4 MByte pages" },
> +	{ 0x63, TLB_DATA_1G,		4,	" TLB_DATA 1 GByte pages, 4-way set associative" },
> +	{ 0x76, TLB_INST_2M_4M,		8,	" TLB_INST 2-MByte or 4-MByte pages, fully associative" },
>  	{ 0xb0, TLB_INST_4K,		128,	" TLB_INST 4 KByte pages, 4-way set associative" },
>  	{ 0xb1, TLB_INST_2M_4M,		4,	" TLB_INST 2M pages, 4-way, 8 entries or 4M pages, 4-way entries" },
>  	{ 0xb2, TLB_INST_4K,		64,	" TLB_INST 4KByte pages, 4-way set associative" },
> @@ -606,6 +608,10 @@ static void __cpuinit intel_tlb_lookup(const unsigned char desc)
>  		if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries)
>  			tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries;
>  		break;
> +	case TLB_DATA_1G:
> +		if (tlb_lld_1g[ENTRIES] < intel_tlb_table[k].entries)
> +			tlb_lld_1g[ENTRIES] = intel_tlb_table[k].entries;
> +		break;
>  	}
>  }
>  
> -- 
> 1.7.10.4

-- 
 Kirill A. Shutemov

^ permalink raw reply	[flat|nested] 4+ messages in thread
* Re: [PATCH] x86/tlb_info: detect more tlb configuration
  2013-06-04 15:09 ` [PATCH] x86/tlb_info: detect more tlb configuration Kirill A. Shutemov
@ 2013-06-05  1:09   ` Alex Shi
  2013-06-05  5:15     ` Kirill A. Shutemov
  0 siblings, 1 reply; 4+ messages in thread
From: Alex Shi @ 2013-06-05  1:09 UTC (permalink / raw)
  To: Kirill A. Shutemov
  Cc: H. Peter Anvin, Thomas Gleixner, Ingo Molnar, x86, linux-kernel

On 06/04/2013 11:09 PM, Kirill A. Shutemov wrote:
> 
> Kirill A. Shutemov wrote:
>> From: "Kirill A. Shutemov" <kirill.shutemov@linux.intel.com>
>>
> 
> Err.. Forgot CC lists.
> 
>> Software Developer’s Manual covers two more TLB configurations:
>>
>> 63H Data TLB: 1 GByte pages, 4-way set associative, 4 entries
>> 76H Instruction TLB: 2M/4M pages, fully associative, 8 entries

Acked-by: Alex Shi <alex.shi@intel.com>

BTW,
What the new CPU has them?

>>
>> Let's detect them as well.
>>
>> Signed-off-by: Kirill A. Shutemov <kirill.shutemov@linux.intel.com>
>> ---
>>  arch/x86/include/asm/processor.h |    1 +
>>  arch/x86/kernel/cpu/common.c     |    7 ++++---
>>  arch/x86/kernel/cpu/intel.c      |    6 ++++++
>>  3 files changed, 11 insertions(+), 3 deletions(-)
>>
>> diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h
>> index 3270116..1476a41 100644
>> --- a/arch/x86/include/asm/processor.h
>> +++ b/arch/x86/include/asm/processor.h
>> @@ -72,6 +72,7 @@ extern u16 __read_mostly tlb_lli_4m[NR_INFO];
>>  extern u16 __read_mostly tlb_lld_4k[NR_INFO];
>>  extern u16 __read_mostly tlb_lld_2m[NR_INFO];
>>  extern u16 __read_mostly tlb_lld_4m[NR_INFO];
>> +extern u16 __read_mostly tlb_lld_1g[NR_INFO];
>>  extern s8  __read_mostly tlb_flushall_shift;
>>  
>>  /*
>> diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
>> index d814772..ee2f15b 100644
>> --- a/arch/x86/kernel/cpu/common.c
>> +++ b/arch/x86/kernel/cpu/common.c
>> @@ -470,6 +470,7 @@ u16 __read_mostly tlb_lli_4m[NR_INFO];
>>  u16 __read_mostly tlb_lld_4k[NR_INFO];
>>  u16 __read_mostly tlb_lld_2m[NR_INFO];
>>  u16 __read_mostly tlb_lld_4m[NR_INFO];
>> +u16 __read_mostly tlb_lld_1g[NR_INFO];
>>  
>>  /*
>>   * tlb_flushall_shift shows the balance point in replacing cr3 write
>> @@ -484,13 +485,13 @@ void __cpuinit cpu_detect_tlb(struct cpuinfo_x86 *c)
>>  	if (this_cpu->c_detect_tlb)
>>  		this_cpu->c_detect_tlb(c);
>>  
>> -	printk(KERN_INFO "Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n" \
>> -		"Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d\n"	     \
>> +	printk(KERN_INFO "Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n"
>> +		"Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d, 1GB %d\n"
>>  		"tlb_flushall_shift: %d\n",
>>  		tlb_lli_4k[ENTRIES], tlb_lli_2m[ENTRIES],
>>  		tlb_lli_4m[ENTRIES], tlb_lld_4k[ENTRIES],
>>  		tlb_lld_2m[ENTRIES], tlb_lld_4m[ENTRIES],
>> -		tlb_flushall_shift);
>> +		tlb_lld_1g[ENTRIES], tlb_flushall_shift);
>>  }
>>  
>>  void __cpuinit detect_ht(struct cpuinfo_x86 *c)
>> diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
>> index 1905ce9..1130519 100644
>> --- a/arch/x86/kernel/cpu/intel.c
>> +++ b/arch/x86/kernel/cpu/intel.c
>> @@ -529,6 +529,8 @@ static const struct _tlb_table intel_tlb_table[] __cpuinitconst = {
>>  	{ 0x5b, TLB_DATA_4K_4M,		64,	" TLB_DATA 4 KByte and 4 MByte pages" },
>>  	{ 0x5c, TLB_DATA_4K_4M,		128,	" TLB_DATA 4 KByte and 4 MByte pages" },
>>  	{ 0x5d, TLB_DATA_4K_4M,		256,	" TLB_DATA 4 KByte and 4 MByte pages" },
>> +	{ 0x63, TLB_DATA_1G,		4,	" TLB_DATA 1 GByte pages, 4-way set associative" },
>> +	{ 0x76, TLB_INST_2M_4M,		8,	" TLB_INST 2-MByte or 4-MByte pages, fully associative" },
>>  	{ 0xb0, TLB_INST_4K,		128,	" TLB_INST 4 KByte pages, 4-way set associative" },
>>  	{ 0xb1, TLB_INST_2M_4M,		4,	" TLB_INST 2M pages, 4-way, 8 entries or 4M pages, 4-way entries" },
>>  	{ 0xb2, TLB_INST_4K,		64,	" TLB_INST 4KByte pages, 4-way set associative" },
>> @@ -606,6 +608,10 @@ static void __cpuinit intel_tlb_lookup(const unsigned char desc)
>>  		if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries)
>>  			tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries;
>>  		break;
>> +	case TLB_DATA_1G:
>> +		if (tlb_lld_1g[ENTRIES] < intel_tlb_table[k].entries)
>> +			tlb_lld_1g[ENTRIES] = intel_tlb_table[k].entries;
>> +		break;
>>  	}
>>  }
>>  
>> -- 
>> 1.7.10.4
> 


-- 
Thanks
    Alex

^ permalink raw reply	[flat|nested] 4+ messages in thread
* Re: [PATCH] x86/tlb_info: detect more tlb configuration
  2013-06-05  1:09   ` Alex Shi
@ 2013-06-05  5:15     ` Kirill A. Shutemov
  0 siblings, 0 replies; 4+ messages in thread
From: Kirill A. Shutemov @ 2013-06-05  5:15 UTC (permalink / raw)
  To: Alex Shi
  Cc: Kirill A. Shutemov, H. Peter Anvin, Thomas Gleixner, Ingo Molnar,
	x86, linux-kernel

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Alex Shi wrote:
> On 06/04/2013 11:09 PM, Kirill A. Shutemov wrote:
> > 
> > Kirill A. Shutemov wrote:
> >> From: "Kirill A. Shutemov" <kirill.shutemov@linux.intel.com>
> >>
> > 
> > Err.. Forgot CC lists.
> > 
> >> Software Developer’s Manual covers two more TLB configurations:
> >>
> >> 63H Data TLB: 1 GByte pages, 4-way set associative, 4 entries
> >> 76H Instruction TLB: 2M/4M pages, fully associative, 8 entries
> 
> Acked-by: Alex Shi <alex.shi@intel.com>
> 
> BTW,
> What the new CPU has them?

All starting from SandyBridge, I believe.

-- 
 Kirill A. Shutemov

^ permalink raw reply	[flat|nested] 4+ messages in thread
* [PATCH] x86/tlb_info: detect more tlb configuration
@ 2013-12-23 12:16 Kirill A. Shutemov
  0 siblings, 0 replies; 4+ messages in thread
From: Kirill A. Shutemov @ 2013-12-23 12:16 UTC (permalink / raw)
  To: Thomas Gleixner, Ingo Molnar, H. Peter Anvin, x86
  Cc: linux-kernel, linux-mm, Joseph Nuzman, Andi Kleen, Dave Hansen,
	Kirill A. Shutemov

Software Developer’s Manual covers few more TLB configurations:

61H Instruction TLB: 4 KByte pages, fully associative, 48 entries
63H Data TLB: 1 GByte pages, 4-way set associative, 4 entries
76H Instruction TLB: 2M/4M pages, fully associative, 8 entries
B5H Instruction TLB: 4KByte pages, 8-way set associative, 64 entries
B6H Instruction TLB: 4KByte pages, 8-way set associative, 128 entries
C1H Shared 2nd-Level TLB: 4 KByte/2MByte pages, 8-way associative, 1024 entries
C2H DTLB DTLB: 2 MByte/$MByte pages, 4-way associative, 16 entries

Let's detect them as well.

Signed-off-by: Kirill A. Shutemov <kirill.shutemov@linux.intel.com>
---
 arch/x86/include/asm/processor.h |  1 +
 arch/x86/kernel/cpu/common.c     |  7 ++++---
 arch/x86/kernel/cpu/intel.c      | 26 ++++++++++++++++++++++++++
 3 files changed, 31 insertions(+), 3 deletions(-)

diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h
index 7b034a4057f9..1dd6260ed940 100644
--- a/arch/x86/include/asm/processor.h
+++ b/arch/x86/include/asm/processor.h
@@ -72,6 +72,7 @@ extern u16 __read_mostly tlb_lli_4m[NR_INFO];
 extern u16 __read_mostly tlb_lld_4k[NR_INFO];
 extern u16 __read_mostly tlb_lld_2m[NR_INFO];
 extern u16 __read_mostly tlb_lld_4m[NR_INFO];
+extern u16 __read_mostly tlb_lld_1g[NR_INFO];
 extern s8  __read_mostly tlb_flushall_shift;
 
 /*
diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index 6abc172b8258..24b6fd10625a 100644
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -472,6 +472,7 @@ u16 __read_mostly tlb_lli_4m[NR_INFO];
 u16 __read_mostly tlb_lld_4k[NR_INFO];
 u16 __read_mostly tlb_lld_2m[NR_INFO];
 u16 __read_mostly tlb_lld_4m[NR_INFO];
+u16 __read_mostly tlb_lld_1g[NR_INFO];
 
 /*
  * tlb_flushall_shift shows the balance point in replacing cr3 write
@@ -486,13 +487,13 @@ void cpu_detect_tlb(struct cpuinfo_x86 *c)
 	if (this_cpu->c_detect_tlb)
 		this_cpu->c_detect_tlb(c);
 
-	printk(KERN_INFO "Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n" \
-		"Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d\n"	     \
+	printk(KERN_INFO "Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n"
+		"Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d, 1GB %d\n"
 		"tlb_flushall_shift: %d\n",
 		tlb_lli_4k[ENTRIES], tlb_lli_2m[ENTRIES],
 		tlb_lli_4m[ENTRIES], tlb_lld_4k[ENTRIES],
 		tlb_lld_2m[ENTRIES], tlb_lld_4m[ENTRIES],
-		tlb_flushall_shift);
+		tlb_lld_1g[ENTRIES], tlb_flushall_shift);
 }
 
 void detect_ht(struct cpuinfo_x86 *c)
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index dc1ec0dff939..5c68eeb11435 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -505,6 +505,7 @@ static unsigned int intel_size_cache(struct cpuinfo_x86 *c, unsigned int size)
 #define TLB_DATA0_2M_4M	0x23
 
 #define STLB_4K		0x41
+#define STLB_4K_2M	0x42
 
 static const struct _tlb_table intel_tlb_table[] = {
 	{ 0x01, TLB_INST_4K,		32,	" TLB_INST 4 KByte pages, 4-way set associative" },
@@ -525,13 +526,20 @@ static const struct _tlb_table intel_tlb_table[] = {
 	{ 0x5b, TLB_DATA_4K_4M,		64,	" TLB_DATA 4 KByte and 4 MByte pages" },
 	{ 0x5c, TLB_DATA_4K_4M,		128,	" TLB_DATA 4 KByte and 4 MByte pages" },
 	{ 0x5d, TLB_DATA_4K_4M,		256,	" TLB_DATA 4 KByte and 4 MByte pages" },
+	{ 0x61, TLB_INST_4K,		48,	" TLB_INST 4 KByte pages, full associative" },
+	{ 0x63, TLB_DATA_1G,		4,	" TLB_DATA 1 GByte pages, 4-way set associative" },
+	{ 0x76, TLB_INST_2M_4M,		8,	" TLB_INST 2-MByte or 4-MByte pages, fully associative" },
 	{ 0xb0, TLB_INST_4K,		128,	" TLB_INST 4 KByte pages, 4-way set associative" },
 	{ 0xb1, TLB_INST_2M_4M,		4,	" TLB_INST 2M pages, 4-way, 8 entries or 4M pages, 4-way entries" },
 	{ 0xb2, TLB_INST_4K,		64,	" TLB_INST 4KByte pages, 4-way set associative" },
 	{ 0xb3, TLB_DATA_4K,		128,	" TLB_DATA 4 KByte pages, 4-way set associative" },
 	{ 0xb4, TLB_DATA_4K,		256,	" TLB_DATA 4 KByte pages, 4-way associative" },
+	{ 0xb5, TLB_INST_4K,		64,	" TLB_INST 4 KByte pages, 8-way set ssociative" },
+	{ 0xb6, TLB_INST_4K,		128,	" TLB_INST 4 KByte pages, 8-way set ssociative" },
 	{ 0xba, TLB_DATA_4K,		64,	" TLB_DATA 4 KByte pages, 4-way associative" },
 	{ 0xc0, TLB_DATA_4K_4M,		8,	" TLB_DATA 4 KByte and 4 MByte pages, 4-way associative" },
+	{ 0xc1, STLB_4K_2M,		1024,	" STLB 4 KByte and 2 MByte pages, 8-way associative" },
+	{ 0xc2, TLB_DATA_2M_4M,		16,	" DTLB 2 MByte/4MByte pages, 4-way associative" },
 	{ 0xca, STLB_4K,		512,	" STLB 4 KByte pages, 4-way associative" },
 	{ 0x00, 0, 0 }
 };
@@ -557,6 +565,20 @@ static void intel_tlb_lookup(const unsigned char desc)
 		if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries)
 			tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries;
 		break;
+	case STLB_4K_2M:
+		if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries)
+			tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries;
+		if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries)
+			tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries;
+		if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries)
+			tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries;
+		if (tlb_lld_2m[ENTRIES] < intel_tlb_table[k].entries)
+			tlb_lld_2m[ENTRIES] = intel_tlb_table[k].entries;
+		if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries)
+			tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries;
+		if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries)
+			tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries;
+		break;
 	case TLB_INST_ALL:
 		if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries)
 			tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries;
@@ -602,6 +624,10 @@ static void intel_tlb_lookup(const unsigned char desc)
 		if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries)
 			tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries;
 		break;
+	case TLB_DATA_1G:
+		if (tlb_lld_1g[ENTRIES] < intel_tlb_table[k].entries)
+			tlb_lld_1g[ENTRIES] = intel_tlb_table[k].entries;
+		break;
 	}
 }
 
-- 
1.8.5.2


^ permalink raw reply related	[flat|nested] 4+ messages in thread
end of thread, other threads:[~2013-12-23 12:17 UTC | newest]

Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
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     [not found] <1370358196-5699-1-git-send-email-kirill.shutemov@linux.intel.com>
2013-06-04 15:09 ` [PATCH] x86/tlb_info: detect more tlb configuration Kirill A. Shutemov
2013-06-05  1:09   ` Alex Shi
2013-06-05  5:15     ` Kirill A. Shutemov
2013-12-23 12:16 Kirill A. Shutemov

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