[PATCH 0/3] clk: tegra: T114: add DFLL prerequisites

[PATCH 0/3] clk: tegra: T114: add DFLL prerequisites

[Paul Walmsley]

Add the CAR IP block infrastructure needed to support the DFLL clocksource
to the Tegra114 clock code and data files.

Based on linux-next master.  Mike, please let me know if you want the
patches based on a v3.10-rc.

Boot-tested on Tegra114 Dalmore; log follows.


- Paul


---

Paul Walmsley (3):
      clk: tegra: T114: add FCPU clock shaper programming, needed by the DFLL
      clk: tegra: T114: add DFLL source clocks
      clk: tegra: T114: add DFLL DVCO reset control


 drivers/clk/tegra/clk-tegra114.c |  166 ++++++++++++++++++++++++++++++++++++++
 drivers/clk/tegra/clk.h          |    6 +
 2 files changed, 172 insertions(+)


---------------------------------------------------------------------


U-Boot SPL 2013.04-rc1-ga0618e4 (May 27 2013 - 02:41:17)


U-Boot 2013.04-rc1-ga0618e4 (May 27 2013 - 02:41:17)

TEGRA114
Board: NVIDIA Puppy
DRAM:  256 MiB
WARNING: Caches not enabled
MMC:   Tegra SD/MMC: 0, Tegra SD/MMC: 1
*** Warning - bad CRC, using default environment

In:    serial
Out:   serial
Err:   serial
Net:   Net Initialization Skipped
No ethernet found.
(Re)start USB...
USB0:   USB EHCI 1.10
scanning bus 0 for devices... 2 USB Device(s) found
       scanning usb for storage devices... 0 Storage Device(s) found
       scanning usb for ethernet devices... 
Warning: asx0 using MAC address from net device
1 Ethernet Device(s) found
Hit any key to stop autoboot:  2 \b\b\b 0 
Tegra114 (Puppy) # 
Tegra114 (Puppy) # 
Tegra114 (Puppy) # 
Tegra114 (Puppy) # 
Tegra114 (Puppy) # setenv bootargs 'ignore_loglevel console=ttyS0,115200n8'
Tegra114 (Puppy) # setenv ipaddr 192.168.100.100; setenv serverip 192.168.100.1; setenv tftpserverip 192.168.100.1
Tegra114 (Puppy) # tftpboot 0x8040e000 fit_image_2; bootm 0x8040e000
Waiting for Ethernet connection... done.
Using asx0 device
TFTP from server 192.168.100.1; our IP address is 192.168.100.100
Filename 'fit_image_2'.
Load address: 0x8040e000
Loading: *\b#################################################################
	 #################################################################
	 #################################################################
	 #################################################################
	 #################################################################
	 #################################################################
	 #################################################################
	 #################################################################
	 #################################################################
	 #################################################################
	 #################################################################
	 #################################################################
	 #################################################################
	 #################################################################
	 #################################################################
	 #################################################################
	 #################################################################
	 #################################################################
	 #################################################################
	 #################################################################
	 ####################################
	 1.4 MiB/s
done
Bytes transferred = 19598020 (12b0ac4 hex)
## Loading kernel from FIT Image at 8040e000 ...
   Using 'conf@1' configuration
   Trying 'kernel@1' kernel subimage
     Description:  unavailable
     Type:         Kernel Image (no loading done)
     Compression:  uncompressed
     Data Start:   0x8040e0c8
     Data Size:    4299472 Bytes = 4.1 MiB
   Verifying Hash Integrity ... OK
## Loading ramdisk from FIT Image at 8040e000 ...
   Using 'conf@1' configuration
   Trying 'ramdisk@1' ramdisk subimage
     Description:  unavailable
     Type:         RAMDisk Image
     Compression:  gzip compressed
     Data Start:   0x8082d80c
     Data Size:    15273879 Bytes = 14.6 MiB
     Architecture: ARM
     OS:           Linux
     Load Address: 0x82100000
     Entry Point:  0x00000038
   Verifying Hash Integrity ... OK
   Loading ramdisk from 0x8082d80c to 0x82100000
## Loading fdt from FIT Image at 8040e000 ...
   Using 'conf@1' configuration
   Trying 'fdt@1' fdt subimage
     Description:  tegra114-dalmore.dtb
     Type:         Flat Device Tree
     Compression:  uncompressed
     Data Start:   0x80827c4c
     Data Size:    23332 Bytes = 22.8 KiB
     Architecture: ARM
     Hash algo:    sha1
     Hash value:   8b9883d7da439600ba30365e683897dfa97cc4d7
   Verifying Hash Integrity ... sha1+ OK
   Booting using the fdt blob at 0x80827c4c
   XIP Kernel Image (no loading done) ... OK
OK
   Loading Device Tree to 8fb27000, end 8fb34b23 ... OK
boot_kernel.c: ft_board_setup: warning: g_crossystem_data is NULL

Starting kernel ...

[    0.000000] Booting Linux on physical CPU 0x0
[    0.000000] Initializing cgroup subsys cpu
[    0.000000] Initializing cgroup subsys cpuacct
[    0.000000] Linux version 3.10.0-rc4-next-20130607-00003-geb0f105 (pwalmsley@baseline) (gcc version 4.5.1 (Sourcery G++ Lite 2010.09-50) ) #8 SMP PREEMPT Fri Jun 7 04:48:48 PDT 2013
[    0.000000] CPU: ARMv7 Processor [412fc0f2] revision 2 (ARMv7), cr=10c5387d
[    0.000000] CPU: PIPT / VIPT nonaliasing data cache, PIPT instruction cache
[    0.000000] Machine: NVIDIA Tegra SoC (Flattened Device Tree), model: NVIDIA Tegra114 Dalmore evaluation board
[    0.000000] debug: ignoring loglevel setting.
[    0.000000] cma: CMA: reserved 16 MiB at 8e800000
[    0.000000] Memory policy: ECC disabled, Data cache writealloc
[    0.000000] On node 0 totalpages: 65536
[    0.000000] free_area_init_node: node 0, pgdat c07ebe00, node_mem_map c0843000
[    0.000000]   Normal zone: 512 pages used for memmap
[    0.000000]   Normal zone: 0 pages reserved
[    0.000000]   Normal zone: 65536 pages, LIFO batch:15
[    0.000000] Tegra Revision: A01 SKU: 0 CPU Process: 1 Core Process: 0
[    0.000000] PERCPU: Embedded 8 pages/cpu @c0a50000 s9024 r8192 d15552 u32768
[    0.000000] pcpu-alloc: s9024 r8192 d15552 u32768 alloc=8*4096
[    0.000000] pcpu-alloc: [0] 0 [0] 1 [0] 2 [0] 3 
[    0.000000] Built 1 zonelists in Zone order, mobility grouping on.  Total pages: 65024
[    0.000000] Kernel command line: ignore_loglevel console=ttyS0,115200n8
[    0.000000] PID hash table entries: 1024 (order: 0, 4096 bytes)
[    0.000000] Dentry cache hash table entries: 32768 (order: 5, 131072 bytes)
[    0.000000] Inode-cache hash table entries: 16384 (order: 4, 65536 bytes)
[    0.000000] Memory: 219884K/262144K available (5845K kernel code, 293K rwdata, 1704K rodata, 232K init, 340K bss, 42260K reserved, 0K highmem)
[    0.000000] Virtual kernel memory layout:
[    0.000000]     vector  : 0xffff0000 - 0xffff1000   (   4 kB)
[    0.000000]     fixmap  : 0xfff00000 - 0xfffe0000   ( 896 kB)
[    0.000000]     vmalloc : 0xd0800000 - 0xff000000   ( 744 MB)
[    0.000000]     lowmem  : 0xc0000000 - 0xd0000000   ( 256 MB)
[    0.000000]     pkmap   : 0xbfe00000 - 0xc0000000   (   2 MB)
[    0.000000]     modules : 0xbf000000 - 0xbfe00000   (  14 MB)
[    0.000000]       .text : 0xc0008000 - 0xc0767acc   (7551 kB)
[    0.000000]       .init : 0xc0768000 - 0xc07a2340   ( 233 kB)
[    0.000000]       .data : 0xc07a4000 - 0xc07ed6a0   ( 294 kB)
[    0.000000]        .bss : 0xc07ed6a0 - 0xc08427d0   ( 341 kB)
[    0.000000] Preemptible hierarchical RCU implementation.
[    0.000000] NR_IRQS:16 nr_irqs:16 16
[    0.000000] sched_clock: 32 bits at 1000kHz, resolution 1000ns, wraps every 4294967ms
[    0.000000] Architected local timer running at 12.00MHz (virt).
[    0.000000] Switching to timer-based delay loop
[    0.000000] sched_clock: ARM arch timer >56 bits at 12000kHz, resolution 83ns
[    0.000000] Console: colour dummy device 80x30
[   32.509433] Calibrating delay loop (skipped), value calculated using timer frequency.. 24.00 BogoMIPS (lpj=120000)
[   32.509449] pid_max: default: 32768 minimum: 301
[   32.509883] Mount-cache hash table entries: 512
[   32.525337] Initializing cgroup subsys debug
[   32.525352] Initializing cgroup subsys freezer
[   32.525400] CPU: Testing write buffer coherency: ok
[   32.525707] /cpus/cpu@0 missing clock-frequency property
[   32.525720] /cpus/cpu@1 missing clock-frequency property
[   32.525730] /cpus/cpu@2 missing clock-frequency property
[   32.525739] /cpus/cpu@3 missing clock-frequency property
[   32.525753] CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
[   32.525777] Setting up static identity map for 0xc058fb40 - 0xc058fbd8
[   32.579918] CPU1: Booted secondary processor
[   32.579943] CPU1: thread -1, cpu 1, socket 0, mpidr 80000001
[   32.599827] CPU2: Booted secondary processor
[   32.599851] CPU2: thread -1, cpu 2, socket 0, mpidr 80000002
[   32.619759] CPU3: Booted secondary processor
[   32.619782] CPU3: thread -1, cpu 3, socket 0, mpidr 80000003
[   32.619889] Brought up 4 CPUs
[   32.619918] SMP: Total of 4 processors activated (96.00 BogoMIPS).
[   32.619925] CPU: All CPU(s) started in SVC mode.
[   32.620918] devtmpfs: initialized
[   32.634447] pinctrl core: initialized pinctrl subsystem
[   32.634971] regulator-dummy: no parameters
[   32.635803] NET: Registered protocol family 16
[   32.637418] DMA: preallocated 256 KiB pool for atomic coherent allocations
[   32.648266] No ATAGs?
[   32.648295] hw-breakpoint: found 5 (+1 reserved) breakpoint and 4 watchpoint registers.
[   32.648305] hw-breakpoint: maximum watchpoint size is 8 bytes.
[   32.659264] bio: create slab <bio-0> at 0
[   32.660500] vdd_ac_bat: 5000 mV 
[   32.660802] dvdd_ts: Failed to request enable GPIO61: -517
[   32.660966] reg-fixed-voltage 1.regulator: Failed to register regulator: -517
[   32.660990] platform 1.regulator: Driver reg-fixed-voltage requests probe deferral
[   32.661190] lcd_bl_en: Failed to request enable GPIO58: -517
[   32.661340] reg-fixed-voltage 2.regulator: Failed to register regulator: -517
[   32.661363] platform 2.regulator: Driver reg-fixed-voltage requests probe deferral
[   32.661559] usb1_vbus: Failed to request enable GPIO108: -517
[   32.661706] reg-fixed-voltage 3.regulator: Failed to register regulator: -517
[   32.661729] platform 3.regulator: Driver reg-fixed-voltage requests probe deferral
[   32.661924] usb2_vbus: Failed to request enable GPIO86: -517
[   32.662072] reg-fixed-voltage 4.regulator: Failed to register regulator: -517
[   32.662094] platform 4.regulator: Driver reg-fixed-voltage requests probe deferral
[   32.662289] vdd_hdmi_5v0: Failed to request enable GPIO81: -517
[   32.662435] reg-fixed-voltage 5.regulator: Failed to register regulator: -517
[   32.662457] platform 5.regulator: Driver reg-fixed-voltage requests probe deferral
[   32.663438] vgaarb: loaded
[   32.664617] SCSI subsystem initialized
[   32.664995] usbcore: registered new interface driver usbfs
[   32.665090] usbcore: registered new interface driver hub
[   32.665232] usbcore: registered new device driver usb
[   32.667551] vdd-cpu: 500 <--> 1520 mV at 1100 mV 
[   32.668178] tps65090 1-0048: No cache defaults, reading back from HW
[   32.669461] vdd-sys-5v0: no parameters
[   32.669508] vdd-sys-5v0: supplied by vdd_ac_bat
[   32.669802] vdd-sys-3v3: no parameters
[   32.669839] vdd-sys-3v3: supplied by vdd_ac_bat
[   32.670097] vdd-ao: no parameters
[   32.670134] vdd-ao: supplied by vdd_ac_bat
[   32.670403] vdd-lcd-bl: no parameters
[   32.670438] vdd-lcd-bl: supplied by vdd_ac_bat
[   32.670684] TPS65090_RAILSFET2: no parameters
[   32.670720] TPS65090_RAILSFET2: supplied by vdd_ac_bat
[   32.670974] vdd-modem-3v3: no parameters
[   32.671020] vdd-modem-3v3: supplied by vdd-sys-3v3
[   32.671280] avdd-lcd: no parameters
[   32.671315] avdd-lcd: supplied by vdd-sys-3v3
[   32.671567] vdd-lvds: no parameters
[   32.671600] vdd-lvds: supplied by vdd-sys-3v3
[   32.671876] vdd-sd-slot: no parameters
[   32.671911] vdd-sd-slot: supplied by vdd-sys-3v3
[   32.672180] vdd-com-3v3: no parameters
[   32.672218] vdd-com-3v3: supplied by vdd-sys-3v3
[   32.672471] vdd-sby-5v0: no parameters
[   32.672503] vdd-sby-5v0: supplied by vdd_ac_bat
[   32.672758] vdd-sby-3v3: no parameters
[   32.672792] vdd-sby-3v3: supplied by vdd_ac_bat
[   32.673228] Linux video capture interface: v2.00
[   32.673915] platform 7000f010.iommu: Driver tegra-smmu requests probe deferral
[   32.674217] Advanced Linux Sound Architecture Driver Initialized.
[   32.674993] Bluetooth: Core ver 2.16
[   32.675063] NET: Registered protocol family 31
[   32.675071] Bluetooth: HCI device and connection manager initialized
[   32.675096] Bluetooth: HCI socket layer initialized
[   32.675117] Bluetooth: L2CAP socket layer initialized
[   32.675165] Bluetooth: SCO socket layer initialized
[   32.675775] cfg80211: Calling CRDA to update world regulatory domain
[   32.676771] Switching to clocksource arch_sys_counter
[   32.691263] NET: Registered protocol family 2
[   32.692155] TCP established hash table entries: 2048 (order: 2, 16384 bytes)
[   32.692225] TCP bind hash table entries: 2048 (order: 2, 16384 bytes)
[   32.692276] TCP: Hash tables configured (established 2048 bind 2048)
[   32.692533] TCP: reno registered
[   32.692548] UDP hash table entries: 256 (order: 1, 8192 bytes)
[   32.692575] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
[   32.692971] NET: Registered protocol family 1
[   32.693636] RPC: Registered named UNIX socket transport module.
[   32.693646] RPC: Registered udp transport module.
[   32.693653] RPC: Registered tcp transport module.
[   32.693661] RPC: Registered tcp NFSv4.1 backchannel transport module.
[   32.693671] PCI: CLS 0 bytes, default 64
[   32.694359] Unpacking initramfs...
[   34.522719] Freeing initrd memory: 14912K (c2100000 - c2f90000)
[   34.526581] squashfs: version 4.0 (2009/01/31) Phillip Lougher
[   34.528975] io scheduler noop registered (default)
[   34.540503] tegra-apbdma 6000a000.dma: Tegra20 APB DMA driver register 32 channels
[   34.540998] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
[   34.543028] 70006300.serial: ttyS0 at MMIO 0x70006300 (irq = 122) is a Tegra
[   35.363293] console [ttyS0] enabled
[   35.367532] [drm] Initialized drm 1.1.0 20060810
[   35.377913] loop: module loaded
[   35.388509] m25p80 spi32766.0: w25q32dw (4096 Kbytes)
[   35.399535] pegasus: v0.9.3 (2013/04/25), Pegasus/Pegasus II USB Ethernet driver
[   35.406990] usbcore: registered new interface driver pegasus
[   35.412704] usbcore: registered new interface driver asix
[   35.418172] usbcore: registered new interface driver ax88179_178a
[   35.424296] usbcore: registered new interface driver cdc_ether
[   35.430271] usbcore: registered new interface driver smsc75xx
[   35.436103] usbcore: registered new interface driver smsc95xx
[   35.441884] usbcore: registered new interface driver net1080
[   35.447600] usbcore: registered new interface driver cdc_subset
[   35.453563] usbcore: registered new interface driver zaurus
[   35.459255] usbcore: registered new interface driver cdc_ncm
[   35.464922] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
[   35.471598] ehci-pci: EHCI PCI platform driver
[   35.476203] usbcore: registered new interface driver cdc_acm
[   35.481829] cdc_acm: USB Abstract Control Model driver for USB modems and ISDN adapters
[   35.489877] usbcore: registered new interface driver cdc_wdm
[   35.495621] usbcore: registered new interface driver usb-storage
[   35.502221] mousedev: PS/2 mouse device common for all mice
[   35.509150] tegra_rtc 7000e000.rtc: rtc core: registered 7000e000.rtc as rtc0
[   35.516295] tegra_rtc 7000e000.rtc: Tegra internal Real Time Clock
[   35.523469] sbs-battery 0-000b: sbs_probe: Failed to get device status
[   35.530010] sbs-battery: probe of 0-000b failed with error -121
[   35.537450] cpuidle: using governor ladder
[   35.541527] cpuidle: using governor menu
[   35.545575] sdhci: Secure Digital Host Controller Interface driver
[   35.551720] sdhci: Copyright(c) Pierre Ossman
[   35.556066] sdhci-pltfm: SDHCI platform and OF driver helper
[   35.562098] sdhci-tegra 78000400.sdhci: Got CD GPIO #170.
[   35.568539] mmc0: no vqmmc regulator found
[   35.572616] mmc0: no vmmc regulator found
[   35.576618] mmc0: Invalid maximum block size, assuming 512 bytes
[   35.625009] mmc0: SDHCI controller on 78000400.sdhci [78000400.sdhci] using ADMA
[   35.632556] mmc1: no vqmmc regulator found
[   35.638694] mmc1: no vmmc regulator found
[   35.645792] mmc1: Invalid maximum block size, assuming 512 bytes
[   35.694736] mmc1: SDHCI controller on 78000600.sdhci [78000600.sdhci] using ADMA
[   35.702745] usbcore: registered new interface driver usbhid
[   35.708304] usbhid: USB HID core driver
[   35.715950] TCP: cubic registered
[   35.719546] NET: Registered protocol family 10
[   35.726787] mip6: Mobile IPv6
[   35.729741] sit: IPv6 over IPv4 tunneling driver
[   35.736030] NET: Registered protocol family 17
[   35.740488] NET: Registered protocol family 15
[   35.745088] Bluetooth: RFCOMM socket layer initialized
[   35.750198] Bluetooth: RFCOMM ver 1.11
[   35.753925] Bluetooth: BNEP (Ethernet Emulation) ver 1.3
[   35.759240] Bluetooth: BNEP socket layer initialized
[   35.764175] Bluetooth: HIDP (Human Interface Emulation) ver 1.2
[   35.770089] Bluetooth: HIDP socket layer initialized
[   35.775194] VFP support v0.3: implementor 41 architecture 4 part 30 variant f rev 0
[   35.783072] Registering SWP/SWPB emulation handler
[   35.788503] vdd-com-3v3: disabling
[   35.792009] vdd-lvds: disabling
[   35.797305] avdd-lcd: disabling
[   35.800547] vdd-lcd-bl: disabling
[   35.806560] dvdd_ts: 1800 mV 
[   35.809861] lcd_bl_en: 5000 mV 
[   35.815407] usb1_vbus: 5000 mV 
[   35.818573] usb1_vbus: supplied by vdd-sys-5v0
[   35.825415] usb2_vbus: 5000 mV 
[   35.828570] usb2_vbus: supplied by vdd-sys-5v0
[   35.835395] vdd_hdmi_5v0: 5000 mV 
[   35.838810] vdd_hdmi_5v0: supplied by vdd-sys-5v0
[   35.846556] tegra_rtc 7000e000.rtc: setting system clock to 1970-01-01 00:00:36 UTC (36)
[   35.854970] ALSA device list:
[   35.857921]   No soundcards found.
[   35.861842] Freeing unused kernel memory: 232K (c0768000 - c07a2000)
/init: 0: can't access tty; job control turned off
# [   36.367522] mmc1: BKOPS_EN bit is not set
[   36.378786] mmc1: new high speed MMC card at address 0001
[   36.384764] mmcblk0: mmc1:0001 SEM32G 29.1 GiB 
[   36.389573] mmcblk0boot0: mmc1:0001 SEM32G partition 1 4.00 MiB
[   36.395767] mmcblk0boot1: mmc1:0001 SEM32G partition 2 4.00 MiB
[   36.401934] mmcblk0rpmb: mmc1:0001 SEM32G partition 3 4.00 MiB
[   36.408964]  mmcblk0: unknown partition table
[   36.415507]  mmcblk0boot1: unknown partition table
[   36.421822]  mmcblk0boot0: unknown partition table

[PATCH 1/3] clk: tegra: T114: add FCPU clock shaper programming, needed by the DFLL

[Paul Walmsley]

Add clock functions to initialize, enable, and disable the FCPU clock
shapers, based on the FCPU voltage rail state.  These will be used by
the DFLL clocksource driver code.

This version of the patch contains a fix for a problem noticed by Andrew
Chew <achew@nvidia.com>, where some of the FINETRIM_R bitfields were
incorrectly defined.

Based on code originally written by Aleksandr Frid <afrid@nvidia.com>.

Signed-off-by: Paul Walmsley <pwalmsley@nvidia.com>
Cc: Andrew Chew <achew@nvidia.com>
Reviewed-by: Andrew Chew <achew@nvidia.com>
Cc: Matthew Longnecker <mlongnecker@nvidia.com>
Cc: Aleksandr Frid <afrid@nvidia.com>
---
 drivers/clk/tegra/clk-tegra114.c |  118 ++++++++++++++++++++++++++++++++++++++
 drivers/clk/tegra/clk.h          |    4 +
 2 files changed, 122 insertions(+)

diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c
index eb27764..c6e35d4 100644
--- a/drivers/clk/tegra/clk-tegra114.c
+++ b/drivers/clk/tegra/clk-tegra114.c
@@ -21,6 +21,7 @@
 #include <linux/of.h>
 #include <linux/of_address.h>
 #include <linux/delay.h>
+#include <linux/export.h>
 #include <linux/clk/tegra.h>
 
 #include "clk.h"
@@ -41,8 +42,33 @@
 #define RST_DEVICES_CLR_V		0x434
 #define RST_DEVICES_SET_W		0x438
 #define RST_DEVICES_CLR_W		0x43c
+#define CPU_FINETRIM_SELECT		0x4d4	/* override default prop dlys */
+#define CPU_FINETRIM_DR			0x4d8	/* rise->rise prop dly A */
+#define CPU_FINETRIM_R			0x4e4	/* rise->rise prop dly inc A */
 #define RST_DEVICES_NUM			5
 
+/* CPU_FINETRIM_SELECT and CPU_FINETRIM_DR bitfields */
+#define CPU_FINETRIM_1_FCPU_1		BIT(0)	/* fcpu0 */
+#define CPU_FINETRIM_1_FCPU_2		BIT(1)	/* fcpu1 */
+#define CPU_FINETRIM_1_FCPU_3		BIT(2)	/* fcpu2 */
+#define CPU_FINETRIM_1_FCPU_4		BIT(3)	/* fcpu3 */
+#define CPU_FINETRIM_1_FCPU_5		BIT(4)	/* fl2 */
+#define CPU_FINETRIM_1_FCPU_6		BIT(5)	/* ftop */
+
+/* CPU_FINETRIM_R bitfields */
+#define CPU_FINETRIM_R_FCPU_1_SHIFT	0		/* fcpu0 */
+#define CPU_FINETRIM_R_FCPU_1_MASK	(0x3 << CPU_FINETRIM_R_FCPU_1_SHIFT)
+#define CPU_FINETRIM_R_FCPU_2_SHIFT	2		/* fcpu1 */
+#define CPU_FINETRIM_R_FCPU_2_MASK	(0x3 << CPU_FINETRIM_R_FCPU_2_SHIFT)
+#define CPU_FINETRIM_R_FCPU_3_SHIFT	4		/* fcpu2 */
+#define CPU_FINETRIM_R_FCPU_3_MASK	(0x3 << CPU_FINETRIM_R_FCPU_3_SHIFT)
+#define CPU_FINETRIM_R_FCPU_4_SHIFT	6		/* fcpu3 */
+#define CPU_FINETRIM_R_FCPU_4_MASK	(0x3 << CPU_FINETRIM_R_FCPU_4_SHIFT)
+#define CPU_FINETRIM_R_FCPU_5_SHIFT	8		/* fl2 */
+#define CPU_FINETRIM_R_FCPU_5_MASK	(0x3 << CPU_FINETRIM_R_FCPU_5_SHIFT)
+#define CPU_FINETRIM_R_FCPU_6_SHIFT	10		/* ftop */
+#define CPU_FINETRIM_R_FCPU_6_MASK	(0x3 << CPU_FINETRIM_R_FCPU_6_SHIFT)
+
 #define CLK_OUT_ENB_L			0x010
 #define CLK_OUT_ENB_H			0x014
 #define CLK_OUT_ENB_U			0x018
@@ -2054,6 +2080,98 @@ static void __init tegra114_clock_apply_init_table(void)
 	tegra_init_from_table(init_table, clks, clk_max);
 }
 
+
+/**
+ * tegra114_car_barrier - wait for pending writes to the CAR to complete
+ *
+ * Wait for any outstanding writes to the CAR MMIO space from this CPU
+ * to complete before continuing execution.  No return value.
+ */
+static void tegra114_car_barrier(void)
+{
+	wmb();		/* probably unnecessary */
+	readl_relaxed(clk_base + CPU_FINETRIM_SELECT);
+}
+
+/**
+ * tegra114_clock_tune_cpu_trimmers_high - use high-voltage propagation delays
+ *
+ * When the CPU rail voltage is in the high-voltage range, use the
+ * built-in hardwired clock propagation delays in the CPU clock
+ * shaper.  No return value.
+ */
+void tegra114_clock_tune_cpu_trimmers_high(void)
+{
+	u32 select = 0;
+
+	/* Use hardwired rise->rise & fall->fall clock propagation delays */
+	select |= ~(CPU_FINETRIM_1_FCPU_1 | CPU_FINETRIM_1_FCPU_2 |
+		    CPU_FINETRIM_1_FCPU_3 | CPU_FINETRIM_1_FCPU_4 |
+		    CPU_FINETRIM_1_FCPU_5 | CPU_FINETRIM_1_FCPU_6);
+	writel_relaxed(select, clk_base + CPU_FINETRIM_SELECT);
+
+	tegra114_car_barrier();
+}
+EXPORT_SYMBOL(tegra114_clock_tune_cpu_trimmers_high);
+
+/**
+ * tegra114_clock_tune_cpu_trimmers_low - use low-voltage propagation delays
+ *
+ * When the CPU rail voltage is in the low-voltage range, use the
+ * extended clock propagation delays set by
+ * tegra114_clock_tune_cpu_trimmers_init().  The intention is to
+ * maintain the input clock duty cycle that the FCPU subsystem
+ * expects.  No return value.
+ */
+void tegra114_clock_tune_cpu_trimmers_low(void)
+{
+	u32 select = 0;
+
+	/*
+	 * Use software-specified rise->rise & fall->fall clock
+	 * propagation delays (from
+	 * tegra114_clock_tune_cpu_trimmers_init()
+	 */
+	select |= (CPU_FINETRIM_1_FCPU_1 | CPU_FINETRIM_1_FCPU_2 |
+		   CPU_FINETRIM_1_FCPU_3 | CPU_FINETRIM_1_FCPU_4 |
+		   CPU_FINETRIM_1_FCPU_5 | CPU_FINETRIM_1_FCPU_6);
+	writel_relaxed(select, clk_base + CPU_FINETRIM_SELECT);
+
+	tegra114_car_barrier();
+}
+EXPORT_SYMBOL(tegra114_clock_tune_cpu_trimmers_low);
+
+/**
+ * tegra114_clock_tune_cpu_trimmers_init - set up and enable clk prop delays
+ *
+ * Program extended clock propagation delays into the FCPU clock
+ * shaper and enable them.  XXX Define the purpose - peak current
+ * reduction?  No return value.
+ */
+/* XXX Initial voltage rail state assumption issues? */
+void tegra114_clock_tune_cpu_trimmers_init(void)
+{
+	u32 dr = 0, r = 0;
+
+	/* Increment the rise->rise clock delay by four steps */
+	r |= (CPU_FINETRIM_R_FCPU_1_MASK | CPU_FINETRIM_R_FCPU_2_MASK |
+	      CPU_FINETRIM_R_FCPU_3_MASK | CPU_FINETRIM_R_FCPU_4_MASK |
+	      CPU_FINETRIM_R_FCPU_5_MASK | CPU_FINETRIM_R_FCPU_6_MASK);
+	writel_relaxed(r, clk_base + CPU_FINETRIM_R);
+
+	/*
+	 * Use the rise->rise clock propagation delay specified in the
+	 * r field
+	 */
+	dr |= (CPU_FINETRIM_1_FCPU_1 | CPU_FINETRIM_1_FCPU_2 |
+	       CPU_FINETRIM_1_FCPU_3 | CPU_FINETRIM_1_FCPU_4 |
+	       CPU_FINETRIM_1_FCPU_5 | CPU_FINETRIM_1_FCPU_6);
+	writel_relaxed(dr, clk_base + CPU_FINETRIM_DR);
+
+	tegra114_clock_tune_cpu_trimmers_low();
+}
+EXPORT_SYMBOL(tegra114_clock_tune_cpu_trimmers_init);
+
 static void __init tegra114_clock_init(struct device_node *np)
 {
 	struct device_node *node;
diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
index 11278a8..c0b72fc 100644
--- a/drivers/clk/tegra/clk.h
+++ b/drivers/clk/tegra/clk.h
@@ -571,6 +571,10 @@ void tegra_init_from_table(struct tegra_clk_init_table *tbl,
 void tegra_init_dup_clks(struct tegra_clk_duplicate *dup_list,
 		struct clk *clks[], int clk_max);
 
+void tegra114_clock_tune_cpu_trimmers_high(void);
+void tegra114_clock_tune_cpu_trimmers_low(void);
+void tegra114_clock_tune_cpu_trimmers_init(void);
+
 typedef void (*tegra_clk_apply_init_table_func)(void);
 extern tegra_clk_apply_init_table_func tegra_clk_apply_init_table;
 

[PATCH 2/3] clk: tegra: T114: add DFLL source clocks

[Paul Walmsley]

Add the input clocks needed by the DFLL IP blocks.  Initialize them to
51MHz (as required by the DFLL GFD) and to use the PLL_P clock source.

This patch is a collaboration with Peter De Schrijver
<pdeschrijver@nvidia.com>.

Thanks to Laxman Dewangan <ldewangan@nvidia.com> for identifying the
requirement to keep the DFLL clocks enabled to resolve PWR_I2C timeout
issues.

Signed-off-by: Paul Walmsley <pwalmsley@nvidia.com>
Cc: Peter De Schrijver <pdeschrijver@nvidia.com>
Reviewed-by: Andrew Chew <achew@nvidia.com>
Cc: Matthew Longnecker <mlongnecker@nvidia.com>
Cc: Laxman Dewangan <ldewangan@nvidia.com>
---
 drivers/clk/tegra/clk-tegra114.c |   11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c
index c6e35d4..b35c78d 100644
--- a/drivers/clk/tegra/clk-tegra114.c
+++ b/drivers/clk/tegra/clk-tegra114.c
@@ -269,6 +269,8 @@
 #define CLK_SOURCE_I2CSLOW 0x3fc
 #define CLK_SOURCE_SE 0x42c
 #define CLK_SOURCE_MSELECT 0x3b4
+#define CLK_SOURCE_DFLL_REF 0x62c
+#define CLK_SOURCE_DFLL_SOC 0x630
 #define CLK_SOURCE_SOC_THERM 0x644
 #define CLK_SOURCE_XUSB_HOST_SRC 0x600
 #define CLK_SOURCE_XUSB_FALCON_SRC 0x604
@@ -792,6 +794,7 @@ enum tegra114_clk {
 	audio1, audio2, audio3, audio4, spdif, clk_out_1, clk_out_2, clk_out_3,
 	blink, xusb_host_src = 252, xusb_falcon_src, xusb_fs_src, xusb_ss_src,
 	xusb_dev_src, xusb_dev, xusb_hs_src, sclk, hclk, pclk, cclk_g, cclk_lp,
+	dfll_ref = 264, dfll_soc,
 
 	/* Mux clocks */
 
@@ -1796,6 +1799,8 @@ static struct tegra_periph_init_data tegra_periph_clk_list[] = {
 	TEGRA_INIT_DATA_MUX("i2cslow", NULL, "i2cslow", mux_pllp_pllc_clk32_clkm, CLK_SOURCE_I2CSLOW, 81, &periph_u_regs, TEGRA_PERIPH_ON_APB, i2cslow),
 	TEGRA_INIT_DATA_INT8("se", NULL, "se", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SE, 127, &periph_v_regs, TEGRA_PERIPH_ON_APB, se),
 	TEGRA_INIT_DATA_INT_FLAGS("mselect", NULL, "mselect", mux_pllp_clkm, CLK_SOURCE_MSELECT, 99, &periph_v_regs, 0, mselect, CLK_IGNORE_UNUSED),
+	TEGRA_INIT_DATA_MUX("dfll_ref", "ref", "t114_dfll", mux_pllp_clkm, CLK_SOURCE_DFLL_REF, 155, &periph_w_regs, TEGRA_PERIPH_ON_APB, dfll_ref),
+	TEGRA_INIT_DATA_MUX("dfll_soc", "soc", "t114_dfll", mux_pllp_clkm, CLK_SOURCE_DFLL_SOC, 155, &periph_w_regs, TEGRA_PERIPH_ON_APB, dfll_soc),
 	TEGRA_INIT_DATA_MUX8("soc_therm", NULL, "soc_therm", mux_pllm_pllc_pllp_plla, CLK_SOURCE_SOC_THERM, 78, &periph_u_regs, TEGRA_PERIPH_ON_APB, soc_therm),
 	TEGRA_INIT_DATA_XUSB("xusb_host_src", "host_src", "tegra_xhci", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_HOST_SRC, 143, &periph_w_regs, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, xusb_host_src),
 	TEGRA_INIT_DATA_XUSB("xusb_falcon_src", "falcon_src", "tegra_xhci", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_FALCON_SRC, 143, &periph_w_regs, TEGRA_PERIPH_NO_RESET, xusb_falcon_src),
@@ -2057,6 +2062,10 @@ static const struct of_device_id pmc_match[] __initconst = {
 	{},
 };
 
+/*
+ * dfll_soc/dfll_ref apparently must be kept enabled, otherwise I2C5
+ * breaks
+ */
 static __initdata struct tegra_clk_init_table init_table[] = {
 	{uarta, pll_p, 408000000, 0},
 	{uartb, pll_p, 408000000, 0},
@@ -2072,6 +2081,8 @@ static __initdata struct tegra_clk_init_table init_table[] = {
 	{i2s2, pll_a_out0, 11289600, 0},
 	{i2s3, pll_a_out0, 11289600, 0},
 	{i2s4, pll_a_out0, 11289600, 0},
+	{dfll_soc, pll_p, 51000000, 1},
+	{dfll_ref, pll_p, 51000000, 1},
 	{clk_max, clk_max, 0, 0}, /* This MUST be the last entry. */
 };
 

[PATCH 3/3] clk: tegra: T114: add DFLL DVCO reset control

[Paul Walmsley]

Add DFLL DVCO reset line control functions to the CAR IP block driver.

The DVCO present in the DFLL IP block has a separate reset line,
exposed via the CAR IP block.  This reset line is asserted upon SoC
reset.  Unless something (such as the DFLL driver) deasserts this
line, the DVCO will not oscillate, although reads and writes to the
DFLL IP block will complete.

Thanks to Aleksandr Frid <afrid@nvidia.com> for identifying this and
saving hours of debugging time.

Signed-off-by: Paul Walmsley <pwalmsley@nvidia.com>
Cc: Aleksandr Frid <afrid@nvidia.com>
Cc: Peter De Schrijver <pdeschrijver@nvidia.com>
---
 drivers/clk/tegra/clk-tegra114.c |   37 +++++++++++++++++++++++++++++++++++++
 drivers/clk/tegra/clk.h          |    2 ++
 2 files changed, 39 insertions(+)

diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c
index b35c78d..4ab15e3 100644
--- a/drivers/clk/tegra/clk-tegra114.c
+++ b/drivers/clk/tegra/clk-tegra114.c
@@ -29,6 +29,7 @@
 #define RST_DEVICES_L			0x004
 #define RST_DEVICES_H			0x008
 #define RST_DEVICES_U			0x00C
+#define RST_DFLL_DVCO			0x2F4
 #define RST_DEVICES_V			0x358
 #define RST_DEVICES_W			0x35C
 #define RST_DEVICES_X			0x28C
@@ -47,6 +48,9 @@
 #define CPU_FINETRIM_R			0x4e4	/* rise->rise prop dly inc A */
 #define RST_DEVICES_NUM			5
 
+/* RST_DFLL_DVCO bitfields */
+#define DVFS_DFLL_RESET_SHIFT		0
+
 /* CPU_FINETRIM_SELECT and CPU_FINETRIM_DR bitfields */
 #define CPU_FINETRIM_1_FCPU_1		BIT(0)	/* fcpu0 */
 #define CPU_FINETRIM_1_FCPU_2		BIT(1)	/* fcpu1 */
@@ -2183,6 +2187,39 @@ void tegra114_clock_tune_cpu_trimmers_init(void)
 }
 EXPORT_SYMBOL(tegra114_clock_tune_cpu_trimmers_init);
 
+/**
+ * tegra114_clock_assert_dfll_dvco_reset - assert the DFLL's DVCO reset
+ *
+ * Assert the reset line of the DFLL's DVCO.  No return value.
+ */
+void tegra114_clock_assert_dfll_dvco_reset(void)
+{
+	u32 v;
+
+	v = readl_relaxed(clk_base + RST_DFLL_DVCO);
+	v |= (1 << DVFS_DFLL_RESET_SHIFT);
+	writel_relaxed(v, clk_base + RST_DFLL_DVCO);
+	tegra114_car_barrier();
+}
+EXPORT_SYMBOL(tegra114_clock_assert_dfll_dvco_reset);
+
+/**
+ * tegra114_clock_deassert_dfll_dvco_reset - deassert the DFLL's DVCO reset
+ *
+ * Deassert the reset line of the DFLL's DVCO, allowing the DVCO to
+ * operate.  No return value.
+ */
+void tegra114_clock_deassert_dfll_dvco_reset(void)
+{
+	u32 v;
+
+	v = readl_relaxed(clk_base + RST_DFLL_DVCO);
+	v &= ~(1 << DVFS_DFLL_RESET_SHIFT);
+	writel_relaxed(v, clk_base + RST_DFLL_DVCO);
+	tegra114_car_barrier();
+}
+EXPORT_SYMBOL(tegra114_clock_deassert_dfll_dvco_reset);
+
 static void __init tegra114_clock_init(struct device_node *np)
 {
 	struct device_node *node;
diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
index c0b72fc..c2d84a1 100644
--- a/drivers/clk/tegra/clk.h
+++ b/drivers/clk/tegra/clk.h
@@ -574,6 +574,8 @@ void tegra_init_dup_clks(struct tegra_clk_duplicate *dup_list,
 void tegra114_clock_tune_cpu_trimmers_high(void);
 void tegra114_clock_tune_cpu_trimmers_low(void);
 void tegra114_clock_tune_cpu_trimmers_init(void);
+void tegra114_clock_assert_dfll_dvco_reset(void);
+void tegra114_clock_deassert_dfll_dvco_reset(void);
 
 typedef void (*tegra_clk_apply_init_table_func)(void);
 extern tegra_clk_apply_init_table_func tegra_clk_apply_init_table;

Re: [PATCH 2/3] clk: tegra: T114: add DFLL source clocks

[Stephen Warren]

On 06/07/2013 06:19 AM, Paul Walmsley wrote:
> Add the input clocks needed by the DFLL IP blocks.  Initialize them to
> 51MHz (as required by the DFLL GFD) and to use the PLL_P clock source.
> 
> This patch is a collaboration with Peter De Schrijver
> <pdeschrijver@nvidia.com>.
> 
> Thanks to Laxman Dewangan <ldewangan@nvidia.com> for identifying the
> requirement to keep the DFLL clocks enabled to resolve PWR_I2C timeout
> issues.

> diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c

> @@ -792,6 +794,7 @@ enum tegra114_clk {
>  	audio1, audio2, audio3, audio4, spdif, clk_out_1, clk_out_2, clk_out_3,
>  	blink, xusb_host_src = 252, xusb_falcon_src, xusb_fs_src, xusb_ss_src,
>  	xusb_dev_src, xusb_dev, xusb_hs_src, sclk, hclk, pclk, cclk_g, cclk_lp,
> +	dfll_ref = 264, dfll_soc,

Those values need to be added to the DT binding documentation, or rather
the header file that now defines the constants for that binding.

BTW, I was rather hoping that Hiroshi would have converted the clock
drivers to actually use that header file by now... Then this requirement
would have been a lot more obvious. Hiroshi, are patches for that coming
soon? Paul, if not, are you able to do that?

For reference, include/dt-bindings/clock/tegra*-car.h.

Re: [PATCH 3/3] clk: tegra: T114: add DFLL DVCO reset control

[Stephen Warren]

On 06/07/2013 06:19 AM, Paul Walmsley wrote:
> Add DFLL DVCO reset line control functions to the CAR IP block driver.
> 
> The DVCO present in the DFLL IP block has a separate reset line,
> exposed via the CAR IP block.  This reset line is asserted upon SoC
> reset.  Unless something (such as the DFLL driver) deasserts this
> line, the DVCO will not oscillate, although reads and writes to the
> DFLL IP block will complete.
> 
> Thanks to Aleksandr Frid <afrid@nvidia.com> for identifying this and
> saving hours of debugging time.

> diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h

>  void tegra114_clock_tune_cpu_trimmers_high(void);
>  void tegra114_clock_tune_cpu_trimmers_low(void);
>  void tegra114_clock_tune_cpu_trimmers_init(void);
> +void tegra114_clock_assert_dfll_dvco_reset(void);
> +void tegra114_clock_deassert_dfll_dvco_reset(void);

Where/what is the code that will call these new APIs? If it's going to
be something in drivers/clk, that seems fine. If not, then this seems to
be inventing a bunch of new custom APIs exported by the clock driver.
I'm not sure if that's a good idea. (Although I guess that
include/linux/clk/tegra.h has a bunch of other custom APIs to support
CPU hotplug and related functionality, so perhaps it's not a big deael).

The reset assert/de-assert functions at least might be worth exposing
using the new generic module reset API. I believe Prashant Gaikwad is
working on converting the Tegra clock driver to be a module reset
provider, hence removing the existing custom
tegra_periph_reset_{de,}assert() APIs.

Re: [PATCH 3/3] clk: tegra: T114: add DFLL DVCO reset control

[Paul Walmsley]

[-- Attachment #1: Type: TEXT/PLAIN, Size: 1945 bytes --]

Hi Stephen,

On Fri, 7 Jun 2013, Stephen Warren wrote:

> On 06/07/2013 06:19 AM, Paul Walmsley wrote:
> > Add DFLL DVCO reset line control functions to the CAR IP block driver.
> > 
> > The DVCO present in the DFLL IP block has a separate reset line,
> > exposed via the CAR IP block.  This reset line is asserted upon SoC
> > reset.  Unless something (such as the DFLL driver) deasserts this
> > line, the DVCO will not oscillate, although reads and writes to the
> > DFLL IP block will complete.
> > 
> > Thanks to Aleksandr Frid <afrid@nvidia.com> for identifying this and
> > saving hours of debugging time.
> 
> > diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
> 
> >  void tegra114_clock_tune_cpu_trimmers_high(void);
> >  void tegra114_clock_tune_cpu_trimmers_low(void);
> >  void tegra114_clock_tune_cpu_trimmers_init(void);
> > +void tegra114_clock_assert_dfll_dvco_reset(void);
> > +void tegra114_clock_deassert_dfll_dvco_reset(void);
> 
> Where/what is the code that will call these new APIs? If it's going to
> be something in drivers/clk, that seems fine.

That's correct - they'll be used by the DFLL clocksource code, which will 
live in drivers/clk/tegra.  You've seen the patches already ;-)

> The reset assert/de-assert functions at least might be worth exposing
> using the new generic module reset API. I believe Prashant Gaikwad is
> working on converting the Tegra clock driver to be a module reset
> provider, hence removing the existing custom
> tegra_periph_reset_{de,}assert() APIs.

OK, will take a look to see if this can be done without getting in the way 
of Prashant's work.  I'd naïvely assume that it might be best to convert 
these as part of his series - that way we won't duplicate effort.

Prashant, what stage are you at in the conversion?  If you're close to 
completion, maybe we can just add this functionality in with your patches?


- Paul

Re: [PATCH 3/3] clk: tegra: T114: add DFLL DVCO reset control

[Prashant Gaikwad]

On Friday 07 June 2013 10:36 PM, Paul Walmsley wrote:
> Hi Stephen,
>
> On Fri, 7 Jun 2013, Stephen Warren wrote:
>
>> On 06/07/2013 06:19 AM, Paul Walmsley wrote:
>>> Add DFLL DVCO reset line control functions to the CAR IP block driver.
>>>
>>> The DVCO present in the DFLL IP block has a separate reset line,
>>> exposed via the CAR IP block.  This reset line is asserted upon SoC
>>> reset.  Unless something (such as the DFLL driver) deasserts this
>>> line, the DVCO will not oscillate, although reads and writes to the
>>> DFLL IP block will complete.
>>>
>>> Thanks to Aleksandr Frid <afrid@nvidia.com> for identifying this and
>>> saving hours of debugging time.
>>> diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
>>>   void tegra114_clock_tune_cpu_trimmers_high(void);
>>>   void tegra114_clock_tune_cpu_trimmers_low(void);
>>>   void tegra114_clock_tune_cpu_trimmers_init(void);
>>> +void tegra114_clock_assert_dfll_dvco_reset(void);
>>> +void tegra114_clock_deassert_dfll_dvco_reset(void);
>> Where/what is the code that will call these new APIs? If it's going to
>> be something in drivers/clk, that seems fine.
> That's correct - they'll be used by the DFLL clocksource code, which will
> live in drivers/clk/tegra.  You've seen the patches already ;-)

Why not implement these APIs in DFLL clock driver itself and pass RST 
address register to driver?

>> The reset assert/de-assert functions at least might be worth exposing
>> using the new generic module reset API. I believe Prashant Gaikwad is
>> working on converting the Tegra clock driver to be a module reset
>> provider, hence removing the existing custom
>> tegra_periph_reset_{de,}assert() APIs.
> OK, will take a look to see if this can be done without getting in the way
> of Prashant's work.  I'd naïvely assume that it might be best to convert
> these as part of his series - that way we won't duplicate effort.
>
> Prashant, what stage are you at in the conversion?  If you're close to
> completion, maybe we can just add this functionality in with your patches?
>

You can continue with this patch. I do not see any need to add this 
reset control to generic reset module.

> - Paul

Re: [PATCH 3/3] clk: tegra: T114: add DFLL DVCO reset control

[Paul Walmsley]

On Tue, 11 Jun 2013, Prashant Gaikwad wrote:

> Why not implement these APIs in DFLL clock driver itself and pass RST address
> register to driver?

The DFLL DVCO reset registers are CAR registers, not DFLL registers.  
Functions that operate on registers in one IP block shouldn't be located 
in another IP block's driver.


- Paul

Re: [PATCH 3/3] clk: tegra: T114: add DFLL DVCO reset control

[Mike Turquette]

Quoting Paul Walmsley (2013-06-11 02:47:13)
> On Tue, 11 Jun 2013, Prashant Gaikwad wrote:
> 
> > Why not implement these APIs in DFLL clock driver itself and pass RST address
> > register to driver?
> 
> The DFLL DVCO reset registers are CAR registers, not DFLL registers.  
> Functions that operate on registers in one IP block shouldn't be located 
> in another IP block's driver.

Paul & Co.,

These patches appear fine to me but I did not see any Acks, nor could I
tell if a v2 was necessary based on the comments. Will there be another
version? If not an Acked-by or Reviewed-by would be cool.

Regards,
Mike

> 
> 
> - Paul

Re: [PATCH 3/3] clk: tegra: T114: add DFLL DVCO reset control

[Paul Walmsley]

Hi,

On Sat, 15 Jun 2013, Mike Turquette wrote:

> These patches appear fine to me but I did not see any Acks, nor could I
> tell if a v2 was necessary based on the comments. Will there be another
> version?

I'm not planning to do another version at this time.

> If not an Acked-by or Reviewed-by would be cool.

Hmm, not sure who the right people would be.  Looks like the 
drivers/clk/tegra directory is unmaintained, so not sure who could ack it?

Peter or Stephen, care to review these patches and send a Reviewed-by?


- Paul

Re: [PATCH 3/3] clk: tegra: T114: add DFLL DVCO reset control

[Mike Turquette]

Quoting Paul Walmsley (2013-06-17 13:22:48)
> Hi,
> 
> On Sat, 15 Jun 2013, Mike Turquette wrote:
> 
> > These patches appear fine to me but I did not see any Acks, nor could I
> > tell if a v2 was necessary based on the comments. Will there be another
> > version?
> 
> I'm not planning to do another version at this time.

Thanks for clarifying.  I couldn't tell based on the discussion.

Anyways I've taken these into clk-next now.  There is not maintainer for
that directory as you pointed out, so no need to wait for Acks.

Regards,
Mike

> 
> > If not an Acked-by or Reviewed-by would be cool.
> 
> Hmm, not sure who the right people would be.  Looks like the 
> drivers/clk/tegra directory is unmaintained, so not sure who could ack it?
> 
> Peter or Stephen, care to review these patches and send a Reviewed-by?
> 
> 
> - Paul
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Re: [PATCH 3/3] clk: tegra: T114: add DFLL DVCO reset control

[Paul Walmsley]

On 06/18/2013 11:28 AM, Mike Turquette wrote:
> Thanks for clarifying. I couldn't tell based on the discussion.

No worries :-)

> Anyways I've taken these into clk-next now. There is not maintainer 
> for that directory as you pointed out, so no need to wait for Acks.

Great, thanks.  Or if you'd prefer to wait for a Reviewed-by:, Peter 
mentioned today that he might take a look at them.  Either way is fine 
with me.


- Paul

Re: [PATCH 3/3] clk: tegra: T114: add DFLL DVCO reset control

[Peter De Schrijver]

On Fri, Jun 07, 2013 at 02:19:09PM +0200, Paul Walmsley wrote:
> Add DFLL DVCO reset line control functions to the CAR IP block driver.
> 
> The DVCO present in the DFLL IP block has a separate reset line,
> exposed via the CAR IP block.  This reset line is asserted upon SoC
> reset.  Unless something (such as the DFLL driver) deasserts this
> line, the DVCO will not oscillate, although reads and writes to the
> DFLL IP block will complete.
> 
> Thanks to Aleksandr Frid <afrid@nvidia.com> for identifying this and
> saving hours of debugging time.
> 
> Signed-off-by: Paul Walmsley <pwalmsley@nvidia.com>
> Cc: Aleksandr Frid <afrid@nvidia.com>
> Cc: Peter De Schrijver <pdeschrijver@nvidia.com>
Reviewed-by: <pdeschrijver@nvidia.com>

Cheers,

Peter.