[PATCH V10 0/4] PCIe support for Samsung Exynos5440 SoC

[PATCH V10 0/4] PCIe support for Samsung Exynos5440 SoC

[Jingoo Han]

Hi,

This series of patches introduces PCIe support for Samsung Exynos5440,
and is based on the latest 'linux-next' tree (20130620).
These patches was tested with Intel e1000e LAN card on Exynos5440.

This PATCH v10 follows:
 * PATCH v9, sent on June, 21st 2013
 * PATCH v8, sent on June, 20th 2013
 * PATCH v7, sent on June, 20th 2013
 * PATCH v6, sent on June, 20th 2013
 * PATCH v5, sent on June, 13th 2013
 * PATCH v4, sent on June, 12th 2013
 * PATCH v3, sent on June, 6th 2013
 * PATCH v2, sent on March, 23rd 2013
 * PATCH v1, sent on March, 4th 2013

Changes between v9 and v10:
  * Changed the file name from 'pci-designware.c' to 'pcie-designware.c'
    guided by Pratyush Anand, because synopsis pcie and pci controllers
    are different.
  * Fixed the typos of document, reported by Sachin Kamat.

Changes between v8 and v9:
  * Changed the file name from 'exynos-pcie.txt' to 'designware-pcie.txt'.
  * Added 'snps,dw-pcie' string to compatible property.

Changes between v7 and v8:
  * Changed the file name from 'pci-exynos.c' to 'pci-designware.c',
    and added a generic string for compatible property to exynos-pcie.txt
  * Moved pci_add_resource_offset() for I/O space to the 'if' clause
  * Added Arnd's Acked-by

Changes between v6 and v7:
  * Split ARM DT patch to two patches
  * Fixed node naming
  * Added Arnd's Acked-by

Changes between v5 and v6:
  * Replaced phys_addr_t with u64 for physical addresses of regions
  * Removed unnecessary inbound functions
  * Added handling of io_offset, mem_offset as Arnd Bergmann guided
  * Fixed calculating 'io' resource
  * Removed module_exit() in order not to allow module unload

Changes between v4 and v5:
  * Used gpio binding in DT
  * Increased the size of MEM region to 512 MB including CFG and IO regions in DT
  * Reduced the size of CFG region to 4096 byte in DT
  * Used the size of MEM region instead of hard-coded in_mem_size
  * Fixed exynos_pcie_prog_viewport_{mem/io}_{outbound/inbound} functions
    to use both translated addresses and untranslated addresses
  * Replaced pci_add_resource_offset() with pci_add_resource()
  * Added values from the DT individually to io_base, mem_base

Changes between v3 and v4:
  * Added support for multi domains as reviewed by Jason Gunthorpe,
    and Arnd Bergmann.
  * Fixed both MEM space and I/O space in DT.
  * Removed redundant physical addresses from struct pcie_port,
    added devm_ioremap_resource() to make add_pcie_port() simpler.
  * Added clock names and clock enable/disable.

Changes between v2 and v3:
  * Rebased on the top of 3.10-rc4
  * Updated names of PCIe PHY registers

Changes between v1 and v2:
  * Moved Exynos PCIe driver from arch/arm to drivers/pci/host.
  * Added DT properties of PCI DT standard.


Here is the lspci -vv output.

0000:00:00.0 PCI bridge: Samsung Electronics Co Ltd Device a549 (rev 01) (prog-if 00 [Normal decode])
        Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- DisINTx-
        Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
        Latency: 0, Cache Line Size: 64 bytes
        Bus: primary=00, secondary=01, subordinate=01, sec-latency=0
        I/O behind bridge: 00001000-00001fff
        Memory behind bridge: 40100000-401fffff
        Prefetchable memory behind bridge: 40200000-402fffff
        Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR-
        BridgeCtl: Parity+ SERR- NoISA- VGA- MAbort- >Reset- FastB2B-
                PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-
        Capabilities: [40] Power Management version 3
                Flags: PMEClk- DSI- D1+ D2- AuxCurrent=375mA PME(D0+,D1+,D2-,D3hot+,D3cold-)
                Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-
        Capabilities: [50] MSI: Enable- Count=1/1 Maskable- 64bit+
                Address: 0000000000000000  Data: 0000
        Capabilities: [70] Express (v2) Root Port (Slot-), MSI 00
                DevCap: MaxPayload 512 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us
                        ExtTag+ RBE+ FLReset-
                DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported-
                        RlxdOrd+ ExtTag+ PhantFunc- AuxPwr- NoSnoop-
                        MaxPayload 128 bytes, MaxReadReq 512 bytes
                DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend-
                LnkCap: Port #0, Speed 5GT/s, Width x4, ASPM L0s L1, Latency L0 <64ns, L1 <2us
                        ClockPM- Surprise- LLActRep+ BwNot+
                LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk-
                        ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
                LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk- DLActive+ BWMgmt+ ABWMgmt-
                RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible-
                RootCap: CRSVisible-
                RootSta: PME ReqID 0000, PMEStatus- PMEPending-
                DevCap2: Completion Timeout: Range ABCD, TimeoutDis+ ARIFwd-
                DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis- ARIFwd-
                LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis-, Selectable De-emphasis: -6dB
                         Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-
                         Compliance De-emphasis: -6dB
                LnkSta2: Current De-emphasis Level: -3.5dB, EqualizationComplete-, EqualizationPhase1-
                         EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest-
        Capabilities: [100 v2] Advanced Error Reporting
                UESta:  DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
                UEMsk:  DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
                UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol-
                CESta:  RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr-
                CEMsk:  RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+
                AERCap: First Error Pointer: 00, GenCap+ CGenEn- ChkCap+ ChkEn-
        Capabilities: [148 v1] Virtual Channel
                Caps:   LPEVC=0 RefClk=100ns PATEntryBits=1
                Arb:    Fixed- WRR32- WRR64- WRR128-
                Ctrl:   ArbSelect=Fixed
                Status: InProgress-
                VC0:    Caps:   PATOffset=00 MaxTimeSlots=1 RejSnoopTrans-
                        Arb:    Fixed- WRR32- WRR64- WRR128- TWRR128- WRR256-
                        Ctrl:   Enable+ ID=0 ArbSelect=Fixed TC/VC=ff
                        Status: NegoPending- InProgress-
        Kernel driver in use: pcieport

0000:01:00.0 Ethernet controller: Intel Corporation 82574L Gigabit Network Connection
        Subsystem: Intel Corporation Gigabit CT Desktop Adapter
        Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- DisINTx-
        Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
        Latency: 0, Cache Line Size: 64 bytes
        Interrupt: pin A routed to IRQ 53
        Region 0: Memory at 40180000 (32-bit, non-prefetchable) [size=128K]
        Region 1: Memory at 40100000 (32-bit, non-prefetchable) [size=512K]
        Region 2: I/O ports at 1000 [size=32]
        Region 3: Memory at 401a0000 (32-bit, non-prefetchable) [size=16K]
        [virtual] Expansion ROM at 40200000 [disabled] [size=256K]
        Capabilities: [c8] Power Management version 2
                Flags: PMEClk- DSI+ D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+)
                Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=1 PME-
        Capabilities: [d0] MSI: Enable- Count=1/1 Maskable- 64bit+
                Address: 0000000000000000  Data: 0000
        Capabilities: [e0] Express (v1) Endpoint, MSI 00
                DevCap: MaxPayload 256 bytes, PhantFunc 0, Latency L0s <512ns, L1 <64us
                        ExtTag- AttnBtn- AttnInd- PwrInd- RBE+ FLReset-
                DevCtl: Report errors: Correctable+ Non-Fatal+ Fatal+ Unsupported+
                        RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+
                        MaxPayload 128 bytes, MaxReadReq 512 bytes
                DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr+ TransPend-
                LnkCap: Port #4, Speed 2.5GT/s, Width x1, ASPM L0s L1, Latency L0 <128ns, L1 <64us
                        ClockPM- Surprise- LLActRep- BwNot-
                LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk-
                        ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
                LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-
        Capabilities: [a0] MSI-X: Enable- Count=5 Masked-
                Vector table: BAR=3 offset=00000000
                PBA: BAR=3 offset=00002000
        Capabilities: [100 v1] Advanced Error Reporting
                UESta:  DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
                UEMsk:  DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
                UESvrt: DLP+ SDES- TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol-
                CESta:  RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr-
                CEMsk:  RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+
                AERCap: First Error Pointer: 00, GenCap- CGenEn- ChkCap- ChkEn-
        Capabilities: [140 v1] Device Serial Number 68-05-ca-ff-ff-11-5e-75
        Kernel driver in use: e1000e

0001:00:00.0 PCI bridge: Samsung Electronics Co Ltd Device a549 (rev 01) (prog-if 00 [Normal decode])
        Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- DisINTx-
        Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
        Latency: 0, Cache Line Size: 64 bytes
        Bus: primary=00, secondary=01, subordinate=01, sec-latency=0
        I/O behind bridge: 00000000-00000fff
        Memory behind bridge: 60100000-601fffff
        Prefetchable memory behind bridge: 60200000-602fffff
        Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR-
        BridgeCtl: Parity+ SERR- NoISA- VGA- MAbort- >Reset- FastB2B-
                PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-
        Capabilities: [40] Power Management version 3
                Flags: PMEClk- DSI- D1+ D2- AuxCurrent=375mA PME(D0+,D1+,D2-,D3hot+,D3cold-)
                Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-
        Capabilities: [50] MSI: Enable- Count=1/1 Maskable- 64bit+
                Address: 0000000000000000  Data: 0000
        Capabilities: [70] Express (v2) Root Port (Slot-), MSI 00
                DevCap: MaxPayload 512 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us
                        ExtTag+ RBE+ FLReset-
                DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported-
                        RlxdOrd+ ExtTag+ PhantFunc- AuxPwr- NoSnoop-
                        MaxPayload 128 bytes, MaxReadReq 512 bytes
                DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend-
                LnkCap: Port #0, Speed 5GT/s, Width x4, ASPM L0s L1, Latency L0 <64ns, L1 <2us
                        ClockPM- Surprise- LLActRep+ BwNot+
                LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk-
                        ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
                LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk- DLActive+ BWMgmt+ ABWMgmt-
                RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible-
                RootCap: CRSVisible-
                RootSta: PME ReqID 0000, PMEStatus- PMEPending-
                DevCap2: Completion Timeout: Range ABCD, TimeoutDis+ ARIFwd-
                DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis- ARIFwd-
                LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis-, Selectable De-emphasis: -6dB
                         Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-
                         Compliance De-emphasis: -6dB
                LnkSta2: Current De-emphasis Level: -3.5dB, EqualizationComplete-, EqualizationPhase1-
                         EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest-
        Capabilities: [100 v2] Advanced Error Reporting
                UESta:  DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
                UEMsk:  DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
                UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol-
                CESta:  RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr-
                CEMsk:  RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+
                AERCap: First Error Pointer: 00, GenCap+ CGenEn- ChkCap+ ChkEn-
        Capabilities: [148 v1] Virtual Channel
                Caps:   LPEVC=0 RefClk=100ns PATEntryBits=1
                Arb:    Fixed- WRR32- WRR64- WRR128-
                Ctrl:   ArbSelect=Fixed
                Status: InProgress-
                VC0:    Caps:   PATOffset=00 MaxTimeSlots=1 RejSnoopTrans-
                        Arb:    Fixed- WRR32- WRR64- WRR128- TWRR128- WRR256-
                        Ctrl:   Enable+ ID=0 ArbSelect=Fixed TC/VC=ff
                        Status: NegoPending- InProgress-
        Kernel driver in use: pcieport

0001:01:00.0 Ethernet controller: Intel Corporation 82574L Gigabit Network Connection
        Subsystem: Intel Corporation Gigabit CT Desktop Adapter
        Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- DisINTx-
        Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
        Latency: 0, Cache Line Size: 64 bytes
        Interrupt: pin A routed to IRQ 56
        Region 0: Memory at 60180000 (32-bit, non-prefetchable) [size=128K]
        Region 1: Memory at 60100000 (32-bit, non-prefetchable) [size=512K]
        Region 2: I/O ports at 10000 [size=32]
        Region 3: Memory at 601a0000 (32-bit, non-prefetchable) [size=16K]
        [virtual] Expansion ROM at 60200000 [disabled] [size=256K]
        Capabilities: [c8] Power Management version 2
                Flags: PMEClk- DSI+ D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+)
                Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=1 PME-
        Capabilities: [d0] MSI: Enable- Count=1/1 Maskable- 64bit+
                Address: 0000000000000000  Data: 0000
        Capabilities: [e0] Express (v1) Endpoint, MSI 00
                DevCap: MaxPayload 256 bytes, PhantFunc 0, Latency L0s <512ns, L1 <64us
                        ExtTag- AttnBtn- AttnInd- PwrInd- RBE+ FLReset-
                DevCtl: Report errors: Correctable+ Non-Fatal+ Fatal+ Unsupported+
                        RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+
                        MaxPayload 128 bytes, MaxReadReq 512 bytes
                DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr+ TransPend-
                LnkCap: Port #4, Speed 2.5GT/s, Width x1, ASPM L0s L1, Latency L0 <128ns, L1 <64us
                        ClockPM- Surprise- LLActRep- BwNot-
                LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk-
                        ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
                LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-
        Capabilities: [a0] MSI-X: Enable- Count=5 Masked-
                Vector table: BAR=3 offset=00000000
                PBA: BAR=3 offset=00002000
        Capabilities: [100 v1] Advanced Error Reporting
                UESta:  DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
                UEMsk:  DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
                UESvrt: DLP+ SDES- TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol-
                CESta:  RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr-
                CEMsk:  RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+
                AERCap: First Error Pointer: 00, GenCap- CGenEn- ChkCap- ChkEn-
        Capabilities: [140 v1] Device Serial Number 68-05-ca-ff-ff-18-44-c5
        Kernel driver in use: e1000e


Thank you.

Best regards,
Jingoo Han


Jingoo Han (4):
  pci: Add PCIe driver for Samsung Exynos
  ARM: EXYNOS: Enable PCIe support for Exynos5440
  ARM: dts: Add pcie controller node for Samsung EXYNOS5440 SoC
  ARM: dts: Add pcie controller node for exynos5440-ssdk5440

 arch/arm/boot/dts/exynos5440-ssdk5440.dts          |    8 ++++++
 arch/arm/boot/dts/exynos5440.dtsi                  |   40 ++++++++++++++++++++++++++++-
 arch/arm/Kconfig                                   |    1 +
 arch/arm/mach-exynos/Kconfig                       |    2 ++
 .../devicetree/bindings/pci/designware-pcie.txt    |   73 ++
 drivers/pci/host/Kconfig                           |    9 +
 drivers/pci/host/Makefile                          |    1 +
 drivers/pci/host/pcie-designware.c                 | 1057 ++++++++++++++++++++
 8 files changed, 1190 insertions(+), 1 deletion(-)
 create mode 100644 Documentation/devicetree/bindings/pci/designware-pcie.txt
 create mode 100644 drivers/pci/host/pcie-designware.c
-- 
1.7.10.4

Re: [PATCH V10 0/4] PCIe support for Samsung Exynos5440 SoC

[Arnd Bergmann]

On Friday 21 June 2013, Jingoo Han wrote:
> Changes between v9 and v10:
>   * Changed the file name from 'pci-designware.c' to 'pcie-designware.c'
>     guided by Pratyush Anand, because synopsis pcie and pci controllers
>     are different.
>   * Fixed the typos of document, reported by Sachin Kamat.
> 
> Changes between v8 and v9:
>   * Changed the file name from 'exynos-pcie.txt' to 'designware-pcie.txt'.
>   * Added 'snps,dw-pcie' string to compatible property.
> 
> Changes between v7 and v8:
>   * Changed the file name from 'pci-exynos.c' to 'pci-designware.c',
>     and added a generic string for compatible property to exynos-pcie.txt
>   * Moved pci_add_resource_offset() for I/O space to the 'if' clause
>   * Added Arnd's Acked-by
> 
> Changes between v6 and v7:
>   * Split ARM DT patch to two patches
>   * Fixed node naming
>   * Added Arnd's Acked-by

Ok, that takes care of all my comments.

Bjorn, are you still considering to merge this for 3.11 or have you
closed your tree for the merge window? I think it would be good to get
it in.

	Arnd

Re: [PATCH V10 0/4] PCIe support for Samsung Exynos5440 SoC

[Thomas Petazzoni]

Dear Arnd Bergmann,

On Fri, 21 Jun 2013 09:31:58 +0200, Arnd Bergmann wrote:

> Bjorn, are you still considering to merge this for 3.11 or have you
> closed your tree for the merge window? I think it would be good to get
> it in.

Note that the of/pci changes needed for this driver are merged through
the arm-soc tree, with the of maintainers ACKs. They are already in
arm-soc for-next, through Jason Cooper's tree.

4e23d3f505e8acfeac7cc33d4113fbb5a25c3090 of/pci: Add of_pci_parse_bus_range() function
45ab9702fb47d18dca116b3a0509efa19fbcb27a of/pci: Add of_pci_get_devfn() function
29b635c00f3ebcdaf7a52c4948f6d948ad3757d3 of/pci: Provide support for parsing PCI DT ranges property

Also, it depends on the Marvell PCIe driver (but to a lesser extent),
which is the one that creates the drivers/pci/host/Kconfig and
drivers/pci/host/Makefile.

45361a4fe4464180815157654aabbd2afb4848ad pci: PCIe driver for Marvell Armada 370/XP systems

I am by far not an expert on how to solve merge strategies and so on,
but to avoid conflicts at Linus's level while merging the arm-soc and
pci trees, it would be better if this Samsung PCIe driver could go
through arm-soc (with Bjorn ACK, of course), so that Arnd/Olof can
make sure the ordering is correct with regard to the of/pci changes and
the mvebu/pci driver.

I'll let you discuss that with Jason Cooper.

Best regards,

Thomas
-- 
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

Re: [PATCH V10 0/4] PCIe support for Samsung Exynos5440 SoC

[Arnd Bergmann]

On Friday 21 June 2013, Thomas Petazzoni wrote:
> I am by far not an expert on how to solve merge strategies and so on,
> but to avoid conflicts at Linus's level while merging the arm-soc and
> pci trees, it would be better if this Samsung PCIe driver could go
> through arm-soc (with Bjorn ACK, of course), so that Arnd/Olof can
> make sure the ordering is correct with regard to the of/pci changes and
> the mvebu/pci driver.

Yes, good point.

The alternative would be that Bjorn also takes the PCI branch dependencies
that are already in arm-soc into his tree. Either way works, but I agree
that what you suggest would be simpler.

	Arnd

Re: [PATCH V10 0/4] PCIe support for Samsung Exynos5440 SoC

[Jason Cooper]

On Fri, Jun 21, 2013 at 10:30:47AM +0200, Arnd Bergmann wrote:
> On Friday 21 June 2013, Thomas Petazzoni wrote:
> > I am by far not an expert on how to solve merge strategies and so on,
> > but to avoid conflicts at Linus's level while merging the arm-soc and
> > pci trees, it would be better if this Samsung PCIe driver could go
> > through arm-soc (with Bjorn ACK, of course), so that Arnd/Olof can
> > make sure the ordering is correct with regard to the of/pci changes and
> > the mvebu/pci driver.
> 
> Yes, good point.
> 
> The alternative would be that Bjorn also takes the PCI branch dependencies
> that are already in arm-soc into his tree. Either way works, but I agree
> that what you suggest would be simpler.

Yes, that is why we did it this way.  It was my understanding based on
previous comments by yourself and LinusW that you both had patches
depending on (now called) mvebu/of_pci.  So we got it into arm-soc
early so those branches could depend on it.

hth,

Jason.

Re: [PATCH V10 0/4] PCIe support for Samsung Exynos5440 SoC

[Arnd Bergmann]

On Friday 21 June 2013, Jason Cooper wrote:
> On Fri, Jun 21, 2013 at 10:30:47AM +0200, Arnd Bergmann wrote:
> > On Friday 21 June 2013, Thomas Petazzoni wrote:
> > > I am by far not an expert on how to solve merge strategies and so on,
> > > but to avoid conflicts at Linus's level while merging the arm-soc and
> > > pci trees, it would be better if this Samsung PCIe driver could go
> > > through arm-soc (with Bjorn ACK, of course), so that Arnd/Olof can
> > > make sure the ordering is correct with regard to the of/pci changes and
> > > the mvebu/pci driver.
> > 
> > Yes, good point.
> > 
> > The alternative would be that Bjorn also takes the PCI branch dependencies
> > that are already in arm-soc into his tree. Either way works, but I agree
> > that what you suggest would be simpler.
> 
> Yes, that is why we did it this way.  It was my understanding based on
> previous comments by yourself and LinusW that you both had patches
> depending on (now called) mvebu/of_pci.  So we got it into arm-soc
> early so those branches could depend on it.

Right. I wasn't paying enough attention for the early merges that
Olof did.

	Arnd

Re: [PATCH V10 0/4] PCIe support for Samsung Exynos5440 SoC

[Jingoo Han]

On Friday, June 21, 2013 11:15 PM, Arnd Bergmann wrote:
> On Friday 21 June 2013, Jason Cooper wrote:
> > On Fri, Jun 21, 2013 at 10:30:47AM +0200, Arnd Bergmann wrote:
> > > On Friday 21 June 2013, Thomas Petazzoni wrote:
> > > > I am by far not an expert on how to solve merge strategies and so on,
> > > > but to avoid conflicts at Linus's level while merging the arm-soc and
> > > > pci trees, it would be better if this Samsung PCIe driver could go
> > > > through arm-soc (with Bjorn ACK, of course), so that Arnd/Olof can
> > > > make sure the ordering is correct with regard to the of/pci changes and
> > > > the mvebu/pci driver.

Yes, right.
That is the reason why I based on 'linu-next' tree,
instead of 'PCI' -next branch.


Bjorn Helgaas,
Could you give your ACK?
Thank you.


Best regards,
Jingoo Han

> > >
> > > Yes, good point.
> > >
> > > The alternative would be that Bjorn also takes the PCI branch dependencies
> > > that are already in arm-soc into his tree. Either way works, but I agree
> > > that what you suggest would be simpler.
> >
> > Yes, that is why we did it this way.  It was my understanding based on
> > previous comments by yourself and LinusW that you both had patches
> > depending on (now called) mvebu/of_pci.  So we got it into arm-soc
> > early so those branches could depend on it.
> 
> Right. I wasn't paying enough attention for the early merges that
> Olof did.
> 
> 	Arnd